CN107818922A - 制造半导体封装的方法 - Google Patents
制造半导体封装的方法 Download PDFInfo
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- CN107818922A CN107818922A CN201710730431.7A CN201710730431A CN107818922A CN 107818922 A CN107818922 A CN 107818922A CN 201710730431 A CN201710730431 A CN 201710730431A CN 107818922 A CN107818922 A CN 107818922A
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Abstract
一种制造半导体封装的方法包括:在支撑衬底上形成初步封装,所述初步封装包括连接衬底、半导体芯片、以及位于所述连接衬底及所述半导体芯片上的模制图案;在所述模制图案上形成缓冲图案;以及在所述缓冲图案上形成载体衬底,所述载体衬底包括与所述缓冲图案接触的第一部分及与所述模制图案接触的第二部分。
Description
[相关申请的交叉参考]
本申请基于35U.S.C.§119主张在2016年9月13日在韩国知识产权局提出申请的韩国专利申请第10-2016-0117915号的优先权,所述韩国专利申请的公开内容全文并入本案供参考。
技术领域
本发明的示例性实施例涉及制造半导体封装的方法,更具体来说,涉及形成及移除载体衬底的方法。
背景技术
半导体封装可通过将半导体芯片安装在印刷电路板衬底上以及通过例如打线结合或凸块将半导体芯片电连接到印刷电路板衬底来制造。由于随着电子产业的发展,对功能强、速度较快、且较小的电子组件的需求增大,因而已出现其中将多个半导体芯片堆叠在单个封装衬底上的安装方法或将封装彼此堆叠的方法。
发明内容
根据本发明概念的示例性实施例,一种制造半导体封装的方法可包括:在支撑衬底上形成初步封装,所述初步封装包括连接衬底、半导体芯片、以及位于所述连接衬底及所述半导体芯片上的模制图案;在所述模制图案上形成缓冲图案;以及在所述缓冲图案及所述模制图案上形成载体衬底,所述载体衬底包括与所述缓冲图案接触的第一部分及与所述模制图案接触的第二部分。
根据本发明概念的示例性实施例,一种制造半导体封装的方法可包括:提供初步封装,所述初步封装包括连接衬底、半导体芯片及模制图案;在所述模制图案的第一部分上提供缓冲图案,所述缓冲图案暴露出所述模制图案的第二部分的上表面;在所述缓冲图案及所述模制图案上提供载体衬底,所述载体衬底接触所述模制图案的所述第二部分的所述上表面;以及移除所述模制图案的所述第二部分,以将所述载体衬底自所述模制图案分开。
根据本发明概念的示例性实施例,一种制造半导体封装的方法可包括:在支撑衬底上形成封装,所述封装包括:连接衬底,所述连接衬底包括暴露出所述支撑衬底的多个开口;分别位于所述多个开口中的各个开口中的多个半导体芯片;以及模制图案,覆盖所述支撑衬底及所述多个半导体芯片;在所述封装上形成缓冲图案,所述缓冲图案暴露出所述模制图案;以及在所述缓冲图案及所述模制图案上形成载体衬底,所述载体衬底与所述缓冲图案的上表面及所述暴露出的模制图案的上表面接触。
根据本发明概念的示例性实施例,一种制造半导体封装的方法可包括:在支撑衬底上提供连接衬底,其中所述连接衬底具有多个开口。可在所述支撑衬底上以及所述连接衬底的所述多个开口中的每一个开口中配置半导体芯片。可将模制图案形成为覆盖每一所述半导体芯片的上表面及所述连接衬底的上表面。可在所述模制图案上将载体衬底配置成使得在每一所述半导体芯片的所述上表面及所述连接衬底的所述上表面之上延伸。所述载体衬底可在每一所述半导体芯片的所述上表面之上的区处与所述模制图案间隔开,且可在所述连接衬底的所述上表面之上的区处粘合到所述模制图案。在如上所述配置所述载体衬底之后,可移除所述支撑衬底。
附图说明
图1A、图2A及图3A是说明根据示例性实施例的制造半导体封装的方法的俯视图。
图1B至图1E、图2B至图2E、图3B及图4是说明根据示例性实施例的制造半导体封装的方法的剖视图。
图5A及图5B是说明根据示例性实施例的移除载体衬底的工艺的剖视图。
图5C是说明根据示例性实施例的移除载体衬底的第一移除工艺的剖视图。
图6A、图7A及图8A是说明根据示例性实施例的制造半导体封装的方法的俯视图。
图6B是沿图6A中的线I-I'截取的剖视图。
图6C是说明根据示例性实施例的初步封装的剖视图。
图7B及图8B分别是沿图7A及图8A中的线I-I'截取的剖视图。
图9A及图9C是说明根据示例性实施例的制造半导体封装的方法的剖视图。
图9B是说明图9A中的区II的放大图。
图10A及图11A是说明根据示例性实施例的制造半导体封装的方法的俯视图。
图10B及图11B分别是沿图10A及图11A中的线I-I'截取的剖视图。
图12A及图12B是说明根据示例性实施例的初步封装的俯视图。
图13是说明根据示例性实施例的载体衬底的剖视图。
具体实施方式
现将参照附图来更充分地阐述各种示例性实施例,在附图中示出一些示例性实施例。然而,本文所述的概念可实施为许多替代形式且不应被视为仅限于本文所述示例性实施例。
图1A、图2A及图3A是说明根据示例性实施例的制造半导体封装的方法的俯视图。图1B至图1E、图2B至图2E、图3B及图4是说明根据示例性实施例的制造半导体封装的方法的剖视图。图1B至图1E是沿图1A中的线I-I'截取的剖视图。图2B至图2E是沿图2A中的线I-I'截取的剖视图。图3B是沿图3A中的线I-I'截取的剖视图。
参照图1A及图1B,可在支撑衬底100上形成初步封装P。初步封装P可以面板级别形成。初步封装P可包括连接衬底200、第一半导体芯片300及模制图案400。当在俯视图中观察时,初步封装P可包括多个第一区R1及第二区R2。初步封装P的第一区R1可设置在初步封装P的中心区中。初步封装P的第二区R2可设置在初步封装P的边缘区中且可环绕第一区R1。
连接衬底200可设置在支撑衬底100上。连接衬底200可通过粘合层110贴合在支撑衬底100上。作为实例,连接衬底200可包括印刷电路板(printed circuit board,PCB)衬底。连接衬底200可包括基底层210及导电构件220。基底层210可包含非导电材料。在实施例中,基底层210可包含硅酮系材料、聚合物等或其任意组合。可在基底层210中设置导电构件220。导电构件220可包括第一垫221、配线图案222、通路223及第二垫224。第一垫221可设置在连接衬底200的下表面200b上。通路223可穿透基底层210。配线图案222可设置在基底层210之间且可直接连接至通路223。第二垫224可设置在连接衬底200的上表面200a上且可连接至通路223中的至少一个。第二垫224可不在第三方向D3上与第一垫221对准。第三方向D3可为与连接衬底200的下表面200b垂直的方向。第一方向D1及第二方向D2可平行于连接衬底200的下表面200b。第一方向D1可正交於第二方向D2。
导电构件220可包含例如铜、铝、镍等金属、或其合金。可在连接衬底200中形成开口250。开口250可暴露出支撑衬底100。
第一半导体芯片300可设置在支撑衬底100上。第一半导体芯片300可分别设置在初步封装P的第一区R1中。第一半导体芯片300可分别设置在连接衬底200的开口250中。连接衬底200可环绕各自的第一半导体芯片300。可在半导体芯片300中的每一个的下表面300b上设置芯片垫350。
模制图案400可形成在连接衬底200的上表面200a上及第一半导体芯片300的上表面300a上。模制图案400可在连接衬底200与第一半导体芯片300之间的空隙中延伸或填充连接衬底200与第一半导体芯片300之间的空隙。模制图案400可包含软材料,例如绝缘聚合物。模制图案400可利用例如聚合物片材形成。在一些实施例中,模制图案400可包括增层膜或层叠的多个层(laminated multiple layer)。
模制图案400可包括第一部分410及第二部分420。当在俯视图中观察时,模制图案400的第一部分410可设置在初步封装P的中心区上且可与所述多个第一区R1重叠。当在俯视图中观察时,模制图案400的第二部分420可与第二区R2重叠。模制图案400的第二部分420可连接到模制图案400的第一部分410。
参照图1A及图1C,可在初步封装P的第一区R1上设置缓冲图案500。缓冲图案500可覆盖模制图案400的第一部分410且可暴露出模制图案400的第二部分420。缓冲图案500可包含非粘性材料(即,以下论述的不粘合至(或不显著地粘合至)模制图案400的材料(或载体衬底600的材料)的材料)。缓冲图案500可在不贴合至模制图案400的条件下设置在模制图案400上。缓冲图案500的下表面可不结合至模制图案400的上表面。缓冲图案500可不通过沉积工艺形成。作为实例,缓冲图案500可包含特氟龙(Teflon)片材。
参照图1A及图1D,可在缓冲图案500上设置载体衬底600。在形成载体衬底600的过程中,可对缓冲图案500及模制图案400的第一部分410施加压力。由于模制图案400是软的,因此模制图案400的第一部分410可通过所施加的压力被压缩。模制图案400的第二部分420的上表面420a可与缓冲图案500的上表面500a至少实质上共面。载体衬底600可与缓冲图案500的上表面500a以及模制图案400的第二部分420的上表面420a接触。载体衬底600可包括第一部分及第二部分。载体衬底600的第一部分可与缓冲图案500实体接触,但缓冲图案500可不贴合至载体衬底600。而是,载体衬底600的第二部分可与模制图案400的第二部分420接触并贴合至模制图案400的第二部分420。因此,载体衬底600可通过模制图案400的第二部分420贴合至初步封装P。由于模制图案400的第二部分420设置在初步封装P的边缘区内,载体衬底600可稳定地固定至初步封装P。在一些实施例中,在设置载体衬底600之前,可不将模制图案400固化,且可在设置载体衬底600之后将模制图案400固化。
可移除支撑衬底100及粘合层110(例如,由虚线所表示)以暴露出初步封装P的下表面(例如,第一半导体芯片300的下表面300b及连接衬底200的下表面200b)。
参照图1A及图1E,可在初步封装P的下表面上(例如,在第一半导体芯片300的下表面300b及连接衬底200的下表面200b上)形成绝缘图案710、重布线图案720、及保护层715,以由此形成第一衬底700(在本文中也被称为“重布线衬底”)。重布线图案720可包括位于各绝缘图案710之间的导电图案721以及穿透绝缘图案710的导电通路722。重布线图案720可包含铜、铝、等或其任意组合。重布线图案720可连接至第一半导体芯片300的芯片垫350及连接衬底200的第一垫221。保护层715可形成在绝缘图案710的下表面上。保护层715可包含绝缘材料。举例来说,保护层715可包含与模制图案400相同的材料。然而,应认识到,保护层715是可选的且可被省略。由于第一衬底700被用作重布线衬底,因此与连接衬底200相比,第一衬底700可具有薄的厚度。
可在第一衬底700的下表面上形成外部端子730。外部端子730可连接到重布线图案720。外部端子730可包含金属。外部端子730可包含焊料球。外部端子730可通过重布线图案720及导电构件220电连接到第二垫224。外部端子730可不在第三方向D3上与第二垫224对准。外部端子730的数目可不同于第二垫224的数目。第二垫224的配置自由度可通过导电构件220及重布线图案720而得到提高。
参照图2A及图2B,可执行载体衬底600的第一移除工艺。载体衬底600的第一移除工艺可包括对初步封装P及载体衬底600执行锯切工艺(例如,将初步封装P的第二区R2从初步封装P的第一区R1分离)。举例来说,可在初步封装P的第二区R2处(在模制图案400的第二部分420处)执行锯切工艺以将第二区R2从初步封装P的第一区R1分离,从而将第二区R2从初步封装P移除。此时,位于模制图案400的第二部分420上的载体衬底600也可从初步封装P的第一区R1分离。在下文中,在示例性实施例中,在载体衬底600的第一移除工艺之后剩余的模制图案400的部分可包括模制图案400的第一部分410。在锯切工艺之后,载体衬底600可从模制图案400分离。由于载体衬底600不粘合到缓冲图案500,因此可容易地将载体衬底600从初步封装P分开。
参照图2A及图2C,可执行载体衬底600的第二移除工艺以将载体衬底600从缓冲图案500分开。作为实例,载体衬底600可被固定到移除设备1000的真空抽吸头1100,且因此可将载体衬底600从缓冲图案500分开。根据示例性实施例,由于缓冲图案500包含非粘性材料,因此,可在无需施加过大压力(缓冲图案500由粘性材料形成时所需要的压力)便可将载体衬底600从缓冲图案500分离。由于在载体衬底600的移除工艺中未对初步封装P施加过大压力,因此可减少或完全防止对初步封装P及第一衬底700造成的损坏。
参照图2A及图2D,可将缓冲图案500从模制图案400分开。作为实例,缓冲图案500可被固定到移除设备1000的真空抽吸头1100,且因此可容易地将缓冲图案500从模制图案400分开。可使用与在图2C中的载体衬底600的第二移除工艺中使用的移除设备1000不同或相同的移除设备来执行缓冲图案500的移除。如果缓冲图案500粘合到模制图案400,则模制图案400的上表面可在缓冲图案500的移除工艺中被损坏。举例来说,在模制图案400的上表面上可能会产生裂纹。在这种情形中,模制图案400的上表面可具有例如大于5μm的高的中心线平均表面粗糙度(central-line average surface roughness)Ra。可进一步执行缓冲图案500的额外的移除工艺(例如,蚀刻工艺)。然而,根据示例性实施例,缓冲图案500未粘合到模制图案400,且因此模制图案400可不在缓冲图案500的移除工艺中被损坏。因此,在载体衬底600的第二移除工艺之后,模制图案400的上表面可具有0.1μm至3μm的中心线平均表面粗糙度Ra。在缓冲图案500的移除工艺中,第一衬底700、连接衬底200、第一半导体芯片300及模制图案400可不受到损坏。因此,所制造的半导体封装可具有提高的可靠性。可省略缓冲图案500的额外的移除工艺,且因此可简化缓冲图案500的移除工艺。
参照图2A及图2E,在移除缓冲图案500之后,可在模制图案400中形成凹槽401以暴露出第二垫224。
参照图3A及图3B,可将图2A及图2B的初步封装P单体化,且因此,初步封装P的第一区R1可彼此分离。初步封装P的单体化可通过对第一衬底700、连接衬底200及模制图案400进行锯切来执行。初步封装P的经分离的第一区R1可分别形成第一封装P1。第一封装P1可分别包括第一衬底700、第一半导体芯片300中的每一个及模制图案400。在一些实施例中,初步封装P的单体化可通过单个工艺来执行(例如,与图2B所阐述的载体衬底600的第一移除工艺一起)。在这种情形中,载体衬底600及缓冲图案500可余留在第一封装P1中的每一个上,且可对每一个第一封装P1执行载体衬底600的第二移除工艺及缓冲图案500的移除工艺。
参照图4,可在图3B所示的第一封装P1上安装第二封装P2以制造半导体封装。第二封装P2可包括第二衬底800、第二半导体芯片810、及第二模制图案820。第二半导体芯片810可通过倒装芯片方法(flip chip method)安装在第二衬底800上。在一些实施例中,第二半导体芯片810可通过打线接合来电连接到第二衬底800。模制图案820可形成在第二衬底800上以覆盖第二半导体芯片810。
可在第一封装P1与第二封装P2之间形成连接端子900(例如,焊料凸块)。连接端子900可连接到第二衬底800及第二垫224。第二封装P2可通过连接端子900电连接到第一封装P1。图5A及图5B是说明根据示例性实施例的载体衬底的移除工艺的剖视图。在下文中,可不再对与上述重复的说明予以赘述。
参照图5A,可提供初步封装P。初步封装P可包括连接衬底200、多个第一半导体芯片300、模制图案400、缓冲图案500及载体衬底600。连接衬底200、所述多个第一半导体芯片300、模制图案400、缓冲图案500及载体衬底600的形成可与在图1B至图1E所阐述的相同。
之后,可执行载体衬底600的第一移除工艺。举例来说,载体衬底600的第一移除工艺可通过将化学物质涂在模制图案400的侧壁上来执行。所述化学物质可与模制图案400反应,且因此可移除模制图案400的第二部分420(由虚线所包围的区表示)。之后,载体衬底600可从模制图案400分离且可从初步封装P分开。
参照图5B,可执行载体衬底600的第二移除工艺。载体衬底600的第二移除工艺可通过与图2C所述的工艺相同的工艺来执行。举例来说,可使用移除设备1000来将载体衬底600从模制图案400分开。在载体衬底600的第二移除工艺之后,可通过与图2D至图3B所阐述的工艺实质上相同的工艺来制造第一封装P1。然而,在图3A及图3B所述的单体化工艺期间可移除初步封装P的第二区R2。
图5C是说明根据示例性实施例的载体衬底的第一移除工艺的剖视图。在下文中,不再对与上述重复的说明予以赘述。
参照图5C,可如以上针对图5A所述来对初步封装P进行处理。也就是说,可执行载体衬底600的第一移除工艺。载体衬底600的第一移除工艺可通过将化学物质涂在模制图案400的侧壁上来执行。之后,可对初步封装P及载体衬底600执行锯切工艺。初步封装P的第二区R2可通过锯切工艺来与初步封装P的第一区R1分离。此时,可如上所论述移除载体衬底600的一部分及缓冲图案500。
图6A、图7A及图8A是说明根据示例性实施例的制造半导体封装的方法的俯视图。图6B、图7B及图8B分别是沿图6A、图7A及图8A中的线I-I'截取的剖视图。在下文中,不再对与上述重复的说明予以赘述。图6C是说明根据示例性实施例的初步封装的剖视图。在下文中,不再对与上述重复的说明予以赘述。
参照图6A及图6B,可制备初步封装P。初步封装P可通过与图1A及图1B所述工艺实质上相同的工艺来形成。然而,如示例性地所示,初步封装P可包括第一区R1、第二区R2及虚设区DR。虚设区DR可设置在各第一区R1之间。作为实例,当在俯视图中观察时,初步封装P的虚设区DR可在第二方向D2上延伸。在其他实施例中,初步封装P的虚设区DR可包括在第一方向D1上延伸的第一部分及在第二方向D2上延伸的第二部分,如图6C所示。然而,应认识到,虚设区DR的布局(当在俯视图中观察时)可根据需要或以其他适合的方式加以改变。
可在初步封装P上设置缓冲图案500及载体衬底600。可在第一半导体芯片300的下表面300b及连接衬底200的下表面200b上形成第一衬底700。
可在虚设区DR中的第一衬底700的下表面上形成测试垫740。测试垫740可电连接到重布线图案720。可在虚设区DR中的连接衬底200中设置测试电路。所述测试电路可电连接到测试垫740。
可对第一衬底700的电连接进行测试。举例来说,可将探针与测试垫740接触来测试重布线图案720的电连接。重布线图案720的电连接的测试可包括电短路或断线(disconnection)测试。
参照图7A及图7B,可移除载体衬底600及缓冲图案500。可通过与上述工艺实质上相同的工艺来执行载体衬底600的移除工艺。举例来说,在载体衬底600的第一移除工艺中,可对初步封装P及载体衬底600进行锯切以将初步封装P的第二区R2、以及与第二区R2对应的载体衬底600的第二部分从初步封装P的第一区R1分离,从而将第二区R2从初步封装P移除。再举例来说,可通过图5A中所阐述的化学蚀刻工艺来移除模制图案400的第二部分420。在载体衬底600的第一移除工艺之后,载体衬底600可从初步封装P分开。接下来,可将载体衬底600及缓冲图案500从初步封装P移除。
参照图8A及图8B,可将初步封装P单体化以使初步封装P的各第一区R1彼此分离。因此,初步封装P的经分离的第一区R1可分别形成第一封装P1。初步封装P的虚设区DR可从初步封装的第一区R1分离。因此,可移除初步封装P的虚设区DR。可在模制图案400中形成凹槽401以暴露出第二垫224。凹槽401可在初步封装P的单体化之前或之后形成。
图9A及图9C是说明根据示例性实施例的制造半导体封装的方法的剖视图。图9A是沿图6A所示线I-I'截取的剖视图。图9B是说明图9A中的区II的放大图。图9C是沿图8A所示线I-I'截取的剖视图。在下文中,不再对与上述重复的说明予以赘述。
参照图6A、图9A、及图9B,可在虚设区DR中的第一衬底700中形成对准键750。对准键750可形成于第一衬底700的绝缘图案710中。可通过蚀刻绝缘图案710以形成通路孔725以及利用导电材料填充通路孔来形成重布线图案720的导电通路722。可在绝缘图案710中的每一个上形成导电层且可对所述导电层进行蚀刻以形成导电图案721。可利用对准键750来执行用于形成通路孔725及导电图案721的蚀刻工艺,且因此,可确认光掩模是否对准。
在形成第一衬底700之后,可移除载体衬底600及缓冲图案500。可对初步封装P及载体衬底600进行锯切以将初步封装P的第二区R2及载体衬底600从初步封装P的第一区R1分离,从而将初步封装P的第二区R2及载体衬底600从初步封装P分离。
参照图8A及图9C,可将初步封装P单体化以制造第一封装P1。此时,初步封装P的各第一区R1可分别形成第一封装P1,且可移除初步封装P的虚设区DR。
图10A及图11A是说明根据示例性实施例的制造半导体封装的方法的俯视图。图10B及图11B分别是沿图10A及图11A中的线I-I'截取的剖视图。在下文中,不再对与上述重复的说明予以赘述。
参照图10A及图10B,初步封装P的第二区R2可在俯视图中观察时与初步封装P的边缘区重叠,且可在初步封装P的各第一区R1之间延伸。初步封装P的第二区R2可沿第二方向D2与初步封装P的中心区交叉。可在初步封装P上设置多个缓冲图案500。缓冲图案500可与初步封装P的第一区R1重叠。缓冲图案500可不设置在初步封装P的第二区R2上。在俯视图中,缓冲图案500可在第一方向D1上彼此间隔开。模制图案400的第二部分420可通过缓冲图案500暴露出。载体衬底600可通过模制图案400的第二部分420来贴合到初步封装P。
参照图11A及图11B,可通过对载体衬底600及初步封装P进行锯切来执行载体衬底600的第一移除工艺。初步封装P的第二区R2以及位于初步封装P的第二区R2上的载体衬底600可如上所论述被移除。在一些实施例中,载体衬底600的第一移除工艺可进一步包括在执行载体衬底600及初步封装P的锯切工艺之前利用化学蚀刻工艺(例如,如上所述)来对初步封装P的侧壁进行处理。之后可通过与图2C至图4中所阐述的工艺实质上相同的工艺来制造半导体封装。
图12A及图12B是说明根据示例性实施例的初步封装的俯视图。在下文中,不再对与上述重复的说明予以赘述。
参照图12A及图12B,可在初步封装P的各第一区R1之间进一步提供初步封装P的第二区R2。可在初步封装P上设置多个缓冲图案500。当在俯视图中观察时,缓冲图案500可在第二方向D2上彼此间隔开。在一些实施例中,如图12A所示,初步封装P的第二区R2可在第一方向D1上与初步封装P的中心区交叉。在一些实施例中,如图12B所示,初步封装P的第二区R2在第一方向D1及第二方向D2两个方向上均与初步封装P的中心区交叉。不论初步封装P的第二区R2与初步封装P的中心区在哪一个(或哪一些)方向上交叉,载体衬底600的第一移除工艺均可通过与图11A及图11B阐述的工艺实质上相同的工艺来执行。
图13是说明根据示例性实施例的载体衬底的剖视图。在下文中,不再对与上述重复的说明予以赘述。
参照图13,载体衬底600可包括依序堆叠的第一层610、第二层620、及第三层630。举例来说,第一层610及第三层630可包含例如铜等金属。第二层620可包含例如玻璃纤维等无机材料。
再次参照图1C,可使用图13中所阐述的载体衬底600。在这种情形中,第一层610可被设置成面朝初步封装P且可贴合到缓冲图案500。然而,载体衬底600可有所变化,而并非仅限于此。
尽管已参照本发明概念的示例性实施例具体显示并阐述了本发明概念,然而所属领域中的普通技术人员应理解,在不背离由以上权利要求界定的本发明的精神及范围的条件下可在本文中作出形式及细节上的各种改变。
[符号的说明]
100:支撑衬底
110:粘合层
200:连接衬底
200a、300a、420a、500a:上表面
200b、300b:下表面
210:基底层
220:导电构件
221:第一垫
222:配线图案
223:通路
224:第二垫
250:开口
300:第一半导体芯片/半导体芯片
350:芯片垫
400:模制图案
401:凹槽
410:第一部分
420:第二部分
500:缓冲图案
600:载体衬底
610:第一层
620:第二层
630:第三层
700:第一衬底
710:绝缘图案
715:保护层
720:重布线图案
721:导电图案
722:导电通路
725:通路孔
730:外部端子
740:测试垫
750:对准键
800:第二衬底
810:第二半导体芯片
820:第二模制图案/模制图案
900:连接端子
1000:移除设备
1100:真空抽吸头
D1:第一方向
D2:第二方向
D3:第三方向
DR:虚设区
I-I':线
II:区
P:初步封装
P1:第一封装
P2:第二封装
R1:第一区
R2:第二区
Claims (25)
1.一种制造半导体封装的方法,其特征在于,所述方法包括:
在支撑衬底上形成初步封装,所述初步封装包括连接衬底、半导体芯片、以及位于所述连接衬底及所述半导体芯片上的模制图案;
在所述模制图案上形成缓冲图案;以及
在所述缓冲图案及所述模制图案上形成载体衬底,所述载体衬底包括与所述缓冲图案接触的第一部分及与所述模制图案接触的第二部分。
2.根据权利要求1所述的方法,其特征在于,所述缓冲图案包括非粘性材料。
3.根据权利要求1所述的方法,其特征在于,进一步包括移除所述载体衬底,
其中移除所述载体衬底包括:
第一移除工艺,通过对所述载体衬底执行锯切工艺来移除所述载体衬底的所述第二部分;以及
第二移除工艺,将所述载体衬底从所述缓冲图案分离。
4.根据权利要求3所述的方法,其特征在于,进一步包括:
移除所述支撑衬底,以暴露出所述初步封装的下表面;以及
在所述初步封装的所述下表面上形成重布线衬底,
其中移除所述载体衬底是在形成所述重布线衬底之后执行。
5.根据权利要求4所述的方法,其特征在于,所述重布线衬底包括绝缘图案及重布线图案。
6.根据权利要求5所述的方法,其特征在于,所述重布线图案电连接到所述半导体芯片及所述连接衬底。
7.根据权利要求1所述的方法,其特征在于,在俯视图中,所述载体衬底的所述第二部分与所述初步封装的边缘区重叠。
8.一种制造半导体封装的方法,其特征在于,所述方法包括:
提供初步封装,所述初步封装包括连接衬底、半导体芯片及模制图案;
在所述模制图案的第一部分上提供缓冲图案,所述缓冲图案暴露出所述模制图案的第二部分的上表面;
在所述缓冲图案及所述模制图案上提供载体衬底,所述载体衬底接触所述模制图案的所述第二部分的所述上表面;以及
移除所述模制图案的所述第二部分,以将所述载体衬底自所述模制图案分开。
9.根据权利要求8所述的方法,其特征在于,所述载体衬底通过所述模制图案的所述第二部分贴合到所述初步封装。
10.根据权利要求8所述的方法,其特征在于,进一步包括:在将所述载体衬底分开之后,从所述初步封装移除所述载体衬底。
11.根据权利要求10所述的方法,其特征在于,进一步包括:在移除所述载体衬底之后,将上部封装设置在所述模制图案上,
其中所述连接衬底包括基础层及位于所述基础层中的导电构件,且
其中所述上部封装电连接到所述导电构件。
12.根据权利要求8所述的方法,其特征在于,所述模制图案的所述第二部分设置在所述初步封装的边缘区中。
13.根据权利要求8所述的方法,其特征在于,移除所述模制图案的所述第二部分包括锯切所述载体衬底及所述初步封装,以使所述模制图案的所述第二部分从所述模制图案的所述第一部分分离。
14.根据权利要求8所述的方法,其特征在于,移除所述模制图案的所述第二部分包括对所述初步封装的侧壁进行化学蚀刻。
15.根据权利要求8所述的方法,其特征在于,在提供所述载体衬底之后,所述模制图案的所述第二部分的所述上表面与所述缓冲图案的上表面实质上共面。
16.一种制造半导体封装的方法,其特征在于,所述方法包括:
在支撑衬底上形成封装,所述封装包括:连接衬底,所述连接衬底包括暴露出所述支撑衬底的多个开口;分别位于所述多个开口中的多个半导体芯片;以及模制图案,覆盖所述支撑衬底及所述多个半导体芯片;
在所述封装上形成缓冲图案,所述缓冲图案暴露出所述模制图案;以及
在所述缓冲图案及所述模制图案上形成载体衬底,所述载体衬底与所述缓冲图案的上表面及所述暴露出的模制图案的上表面接触。
17.根据权利要求16所述的方法,其特征在于,所述缓冲图案包括非粘性材料。
18.根据权利要求16所述的方法,其特征在于,所述缓冲图案包括彼此间隔开的多个缓冲图案,且
其中所述模制图案存在于所述多个缓冲图案之间的间隙中。
19.根据权利要求16所述的方法,其特征在于,进一步包括在所述封装的下表面上形成衬底,
其中所述衬底包括多个第一区、及位于所述多个第一区之间的虚设区,在俯视图中,所述第一区分别与所述多个半导体芯片重叠,且
其中在所述衬底的所述虚设区中形成有测试垫及/或对准键。
20.根据权利要求16所述的方法,其特征在于,所述载体衬底接触所述封装的边缘区中的所述模制图案。
21.一种制造半导体封装的方法,其特征在于,所述方法包括:
在支撑衬底上提供连接衬底,所述连接衬底具有多个开口;
在所述支撑衬底上、所述连接衬底的所述多个开口中的每一个开口中配置半导体芯片;
形成模制图案,所述模制图案覆盖每一所述半导体芯片的上表面及所述连接衬底的上表面;
在所述模制图案上配置载体衬底,其中所述载体衬底在每一所述半导体芯片的所述上表面及所述连接衬底的所述上表面之上延伸,其中所述载体衬底在每一所述半导体芯片的所述上表面之上与所述模制图案间隔开,且其中所述载体衬底在所述连接衬底的所述上表面之上粘合到所述模制图案;以及
在配置所述载体衬底之后,移除所述支撑衬底。
22.根据权利要求21所述的方法,其特征在于,形成所述模制图案包括将所述模制图案的上表面成形为具有在所述半导体芯片中的每一所述半导体芯片的所述上表面之上延伸的至少一个凹槽。
23.根据权利要求22所述的方法,其特征在于,将所述模制图案的所述上表面成形包括:
在所述模制图案上配置缓冲图案;以及
将所述缓冲图案按压到所述模制图案中。
24.根据权利要求23所述的方法,其特征在于,将所述缓冲图案按压到所述模制图案中包括:
使所述载体衬底接触所述缓冲图案;以及
按压所述载体衬底以抵压所述缓冲图案。
25.根据权利要求24所述的方法,其特征在于,所述缓冲图案与所述载体衬底之间的粘着性小于所述模制图案与所述载体衬底之间的粘着性。
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KR20180029614A (ko) | 2018-03-21 |
CN107818922B (zh) | 2020-11-17 |
TW201822285A (zh) | 2018-06-16 |
US9922897B1 (en) | 2018-03-20 |
KR102600106B1 (ko) | 2023-11-09 |
TWI730117B (zh) | 2021-06-11 |
US20180076108A1 (en) | 2018-03-15 |
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