CN112652609A - 具有互连桥接的分隔基板 - Google Patents

具有互连桥接的分隔基板 Download PDF

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CN112652609A
CN112652609A CN202011085341.5A CN202011085341A CN112652609A CN 112652609 A CN112652609 A CN 112652609A CN 202011085341 A CN202011085341 A CN 202011085341A CN 112652609 A CN112652609 A CN 112652609A
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substrates
chips
interconnect
interconnect bridge
chip
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W·索特
M·W·库伊默勒
E·W·特雷姆布勒
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Marvell International Ltd
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Marvell International Ltd
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Abstract

本公开涉及半导体结构，并且更具体地涉及具有互连桥接结构的分隔基板及制造方法。一种结构，包括：多个基板；至少一个芯片，该至少一个芯片被接合且电连接到多个基板中的每个基板；以及互连桥接，互连桥接，物理地连接多个基板，并且电连接与多个基板中的每一个基板接合的多个芯片中的每个芯片。

Description

具有互连桥接的分隔基板
技术领域
本公开涉及半导体结构，并且更具体地涉及具有互连桥接结构的分隔基板以及制造方法。
背景技术
在有线网络交换应用中使用的封装大小不断增长。例如，下一代有线网络交换应用需要较大的封装才能以更高的速度摆脱越来越多的串行器/解串器(Serializer/Deserializer(SerDes))通道。例如，每个SerDes通道要求四(4)个信号球栅阵列(BGA)外加大量隔离BGA。同样，增加SerDes信号的速度会增加所需的隔离BGA的数目。这导致需要更大的基板。
用于高信号计数应用的基板大小的增长导致产品成本的指数增加。例如，速度为30Gbps的SerDes需要总共12个BGA/通道；而60Gbps则需要总共13.5个BGA/通道，而116Gbps需要总共15个BGA/通道。为了适应增加的BGA/通道数目，需要更大的基板；然而，基板大小是增加成本的主要驱动力。即，用于高信号计数应用的基板尺寸增长导致产品成本的指数增加。实际上，最近的数据表明，超过75毫米的基板大小会显著增加基板成本。
发明内容
在本公开的方面中，一种结构，包括：多个基板；至少一个芯片，被接合且电连接到多个基板中的每个基板；以及互连桥接，互连桥接物理地连接多个基板，并且电连接与多个基板中的每一个基板接合的多个芯片中的每个芯片。
在本公开的一个方面，结构包括：具有布线层的多个基板；芯片，通过布线层被电连接到多个基板中的每个基板；互连桥接，将多个芯片彼此电连接并且将多个基板彼此物理地电连接；以及盖板，覆盖多个基板中的每个基板上的芯片。
在本公开的一个方面，结构包括：系统卡；具有布线层的多个基板，多个基板被附接到系统卡；芯片，通过布线层中的至少一个布线层被电连接到多个基板中的每个基板；互连桥接，互连桥接将多个基板中的每个基板的芯片彼此电连接并且从底侧或顶侧将多个基板彼此物理地连接；热界面材料，覆盖互连桥接和多个基板中的每个基板的芯片；以及盖板，被粘附到多个基板中的所选择的基板，并覆盖多个基板中的芯片和热界面材料。
附图说明
在下文的详细描述中，通过本公开的示例性实施例的非限制性示例，参考所提到的多个附图来描述本公开。
图1A示出了根据本公开的方面的分隔基板和互连桥接组件的俯视图。
图1B示出了根据本公开的各方面的图1A的分隔基板和互连桥接组件的截面图。
图2A示出了根据本公开的附加方面的分隔基板和互连桥接组件的俯视图。
图2B示出了根据本公开的方面的图2A的分隔基板和互连桥接组件的截面图。
图3示出了根据本公开的方面的附加分隔基板和互连桥接组件的俯视图。
图4示出了根据本公开的方面的分隔基板和具有盖板的互连桥接组件。
图5A和图5B示出了根据本公开的各方面具有盖板的的分隔基板和互连桥接组件，盖板具有开口。
图6示出了根据本公开的方面的互连桥接组件的截面图。
图7A-图7D示出了根据本公开的方面的用于分隔基板、互连桥接组件和盖板的组装过程。
具体实施方式
本公开涉及半导体结构，并且更具体地涉及具有互连桥接结构的分隔基板及制造方法。更具体地，本公开提供了具有高密度互连桥接的较小的分隔基板，该高密度互连桥接将分隔基板物理地连接。有利的是，较小的分隔基板提供了成本的显著降低，针对下一代联网产品，成本可以降低约50％。
在实施例中，高密度互连桥接将被安装到封装基板上的相邻集成芯片进行电连接。互连桥接包括具有布线的刚性基板，该布线用于将相邻集成芯片电互连并且将分隔基板彼此物理地连接。互连桥接使例如封装基板在各种配置中的大小能等于或小于75mm。在更具体的实施例中，分隔基板可以是约60mm的基板，同时仍允许芯片之间的高密度互连并保持针对热解决方案的能力(例如，盖板/加强板)。
例如，两个60mm的基板可以利用单个高密度互连桥接而被连接在一起。两个60mm的基板可以容纳与单个85mm的基板大约相同数目的球栅阵列(BGA)(例如，大约7000BGA)，但是成本显著降低。类似于单个较大尺寸的基板，两个60mm的基板也可以容纳两个或多个芯片。
本公开的具有互连桥接结构的分隔基板可以使用多种不同的工具以多种方式来制造。但是，通常，这些方法和工具被用于形成尺寸在微米和纳米级的结构。已从集成电路(IC)技术中采用了用于制造本公开的具有互连桥接结构的分隔基板的方法(即，技术)。具体地，具有互连桥接结构的分隔基板的制造使用三个基本构建块：(i)在基板上沉积材料的薄膜；(ii)通过光刻成像在膜的顶部施加经图案化的掩模；以及(iii)将膜选择性地蚀刻至掩模。
图1A示出了根据本公开的各方面的分隔基板和互连桥接组件的俯视图；而图1B示出了图1A的分隔基板和互连桥接组件的截面图。更具体地，图1A和图1B中所示的封装组件10包括多个基板12a、12b。在实施例中，基板12a、12b可以是用于在其上安装集成芯片16的任何已知类型的基板。例如，基板12a、12b可以包括芯部，布线层15在芯部之上和之下形成。在实施例中，基板12a、12b(例如，分隔基板)的尺寸优选地小于75mm，并且更优选地不大于60mm。
基板12a、12b包括球栅阵列(BGA)14和布线层15。如本领域技术人员将认识到的，BGA 14是表面安装型封装的类型(芯片载体)，使得本文中不需要进一步的解释。布线层15被用于经由互连桥接20，将基板12a、12b布线(例如，连接)到芯片16，并且将不同基板12a、12b的芯片16彼此连接。芯片16通过任何常规的安装型连接18(例如，焊锡凸块或可控塌陷芯片连接(C4))而被安装到基板12a、12b。
如图1A至图1B进一步所示，互连桥接20从顶表面将两个基板12a、12b连接在一起。在实施例中，互连桥接20可以由与基板12a、12b相同或不同的材料(如图6所示)组成。互连桥接20可以是高密度互连桥接，高密度互连桥接将分隔基板12a、12b连接在一起并且重要地是允许不同基板12a、12b上的不同芯片16之间经由布线15进行电通信。相应地，通过使用互连桥接20，现在可以减小基板12a、12b的大小，从而保持较小基板12a、12b的成本节省，同时还提供不同芯片16的功能。而且，特别是在布线15不穿过基板12a、12b的芯部的配置视图中，组件10保持信号完整性。此外，互连桥接20实现在板级别的简易组装，同时还由于到中性点(DNP)的距离较小而降低了应力。
图2A示出了根据本公开的附加方面的分隔基板和互连桥接组件的俯视图；而图2B示出了图2A的分隔基板和互连桥接组件的截面图。在图2A和图2B中，互连桥接20从组件10b(基板12a、12b)的底侧(例如，与BGA 14相同的表面)将基板12a、12b连接在一起。在该配置中，现在在基板12a、12b的顶侧上具有附加空间。其余特征类似于图1A和图1B中所示的组件10。
图3示出了根据本公开的各方面的分隔基板和互连桥接组件的俯视图。更具体地，图3中所示的组件10b包括其上安装有相应芯片16、16a的多个基板12a、12b、12c、12c、12d、12e。在实施例中，芯片16a可以大于其余芯片16；但是本文中也考虑了其他配置。在该配置中，基板12a、12b、12c、12c、12d、12e通过多个相应的互连桥接20被连接在一起。如关于图1A-图2B所述，互连桥接20是高密度互连桥接，高密度互连桥接允许经由利用基板12a、12b、12c、12c、12d、12e嵌入的布线在不同基板12a、12b、12c、12c、12d、12e上的不同芯片16、16a之间进行通信。
应当认识到，图3所示的组件10b仅是例示性示例，并且在本文中预想了其他配置。通过例示性的非限制性示例，可以利用由相应互连桥接20连接在一起的不同基板的组合来制造105mm(或其他尺寸)的封装大小。此外，互连桥接20可以在顶侧上、下侧上或其组合上。相应地，通过实现将较小的基板与互连桥接20一起使用，组件可以取决于期望的架构而进行缩放。
图4示出了根据本公开的各方面的分隔基板和具有盖板22的互连桥接组件。在该组件10c中，盖板22被放置在芯片16和互连桥接20之上。在实施例中，盖板22可以为封装组件10c提供进一步的刚性。盖板22可以利用密封粘合剂而被接合到基板12a、12b。热界面材料(TIM)24可以被提供在盖板22的外壳内(例如，在盖板22的下侧上)。例如，TIM 24可以被放置在基板12a、12b、芯片16和互连桥接20之上。TIM 24可以通过任何常规分配器(例如，针头分配器)而被施加到芯片16和互连桥接20与连接件18相对的顶侧。在实施例中，底部填充材料可以被施加到连接件18、芯片16、互连桥接20和基板12a、12b，以至少减小对封装的应力。此后，盖板22被放置在基板12a、12b上，通常通过TIM 24而与密封粘合剂和芯片16接触。
图5A和图5B示出了根据本公开的附加方面的分隔基板和具有盖板的互连桥接组件。图5A是盖板组件的俯视图，且图5B是图5A的盖板组件的截面图。在该组件10c中，盖板22a是具有开口22b的铰接或锁定盖板，以用于将互连桥接20放置在基板12a、12b上。在实施例中，在放置互连桥接20之前，盖板22a可以被放置在基板12a、12b之上并利用密封粘合剂被接合到基板12a、12b。在实施例中，盖板的两侧可以通过如附图标记27示意性所示的机械配合、弹簧或其他锁定机构而被锁定在一起。在放置互连桥接20之后，使用任何常规的分配器(例如，针头分配器)，TIM 24可以被提供(经由开口22b)在盖板22a的外壳内。在实施例中，例如，开口22b可以可选地使用插接帽(cap)25密封。插接帽25可以使用粘合剂而被密封到盖板22a的上侧。本领域技术人员应理解，当互连桥接20被安装在基板12a、12b的下侧上时，也可以使用图4和图5所示的盖板。
图6示出了互连桥接20的截面图。在实施例中，互连桥接20的总高度将小于如图1A至图2A所示的BGA的高度(当从下侧安装时)和/或总高度小于如图1A至图2A所示的芯片16的高度(当从顶侧安装时)。在实施例中，互连桥接20是无芯的。
互连桥接20包括电介质层20a和在电介质层20a的相对侧上的布线层20b。在实施例中，电介质层20a和/或电介质层20a和布线层20b的组合将是刚性基板，以用于经由基板12a、12b将相邻芯片16电互连。在进一步的实施例中，布线层20b在电介质层20a的每一侧上可以是10至20个层，并且更优选地是5至10个层。布线层20b是其中嵌入有导线15的电介质材料。布线层15允许经由连接件18在互连桥接20、基板12a、12b等与相应芯片16之间进行通信。在实施例中，互连桥接20的每个层20a、20b可以为大约10微米至约30微米；但是本文考虑了其他尺寸。
图7A-图7D示出了根据本公开的各方面的针对分隔基板、互连桥接组件和盖板的组装过程。在图7A中，芯片16通过例如回流工艺被连接到基板12a、12b。基板12a、12b被放置在系统卡26上，并通过BGA 18的回流而被接合到系统卡26。在实施例中，回流工艺可以在稍后的阶段(例如，在互连桥接20回流至基板12a、12b期间或TIM与盖板接合之后)执行。在图7B中，互连桥接20与基板12a、12b的布线对准。在对准之后，互连桥接20被放置在基板12a、12b上，并且回流工艺被执行来将互连桥接20机械地连接至基板12a、12b。在图7C中，分配器28被用于将TIM施加到互连桥接20、基板12a、12b和芯片16。粘合剂也可以被施加到盖板22和/或基板12a、12b。此后，如图7D所示，盖板22与基板12a、12b对准并被粘附到基板12a、12b。
在备选实施例中，使用图5A和图5B中所示的盖板组件，例如，芯片16和盖板22a可以首先被连接到基板12a、12b，然后，通过使用盖板22a中的开口22b，互连桥接20可以与基板12a、12b对准并被接合到基板12a、12b。盖板22a然后可以经由机械系统27而被锁定在一起。在对准、接合和锁定之后，TIM 24可以借助开口22b分配，以将芯片16和互连桥接20封装在盖板22a下方。
如上所述的(多个)方法被用于集成电路芯片的制造中。制造商可以以原始晶片形式(即，具有多个未封装芯片的单个晶片)，裸芯片或封装形式来分布所得的集成电路芯片。在后一种情况下，芯片被安装在单芯片封装(例如，具有引线的塑料载体，引线被固定到母板或其他更高级的载体)中，也可以被安装在多芯片封装(例如，具有表面互连或掩埋互连的其中一个或两者的陶瓷载体)中。在任何情况下，芯片然后都与其他芯片、分立电路元件和/或其他信号处理设备集成在一起，作为(a)中间产品(例如，母板)或(b)最终产品的一部分。最终产品可以是包含集成电路芯片的任何产品，范围从玩具和其他低端应用到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
已出于例示的目的给出了对本公开的各种实施例的描述，但是这些描述并不旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变型对于本领域普通技术人员将是显而易见的。选择本文中使用的术语是为了最好地解释实施例的原理、对市场上存在的技术的实际应用或技术改进，或者使得本领域的其他普通技术人员能够理解本文所公开的实施例。

Claims (20)

1.一种结构，包括：
多个基板；
至少一个芯片，所述至少一个芯片被接合且电连接到所述多个基板中的每个基板；以及
互连桥接，所述互连桥接物理地连接所述多个基板，并且将与所述多个基板中的每个基板的接合的所述多个芯片中的每个芯片电连接。
2.根据权利要求1所述的结构，其中所述互连桥接包括具有布线层的刚性基板，所述布线层用于将被安装到所述多个基板的相邻芯片电互连。
3.根据权利要求1所述的结构，其中所述多个基板的大小均为75mm或在75mm以下。
4.根据权利要求1所述的结构，其中所述多个基板的大小均为60mm。
5.根据权利要求1所述的结构，其中所述多个基板是两个基板。
6.根据权利要求1所述的结构，其中所述多个基板是多于两个的基板。
7.根据权利要求1所述的结构，其中所述互连桥接包括互连机构，所述互连机构物理地连接到所述多个基板，并且电连接到与所述多个基板中的每个基板接合的所述多个芯片中的每个芯片。
8.根据权利要求7所述的结构，还包括盖板，所述盖板被粘附到所述多个基板中的所选择的基板，从而覆盖所述互连桥接、所述至少一个芯片和所述多个基板。
9.根据权利要求8所述的结构，其中所述盖板具有开口，所述开口容纳所述互连桥接到所述多个基板上的放置。
10.根据权利要求1所述的结构，其中所述互连桥接从下侧物理地连接所述多个基板。
11.根据权利要求1所述的结构，其中所述互连桥接从顶侧物理地连接所述多个基板。
12.一种结构，包括：
具有布线层的多个基板；
芯片，所述芯片通过所述布线层被电连接到所述多个基板中的每个基板；
互连桥接，所述互连桥接将所述多个芯片彼此电连接并且将所述多个基板彼此物理地电连接；以及
盖板，所述盖板覆盖所述多个基板中的每个基板上的所述芯片。
13.根据权利要求12所述的结构，其中所述互连桥接包括刚性基板和布线层，所述布线层用于将被安装到所述多个基板的相邻芯片电互连。
14.根据权利要求12所述的结构，其中所述多个基板的大小均为75mm或在75mm以下。
15.根据权利要求12所述的结构，其中所述多个基板是两个或更多个基板。
16.根据权利要求12所述的结构，其中所述盖板被粘附到所述多个基板，从而覆盖所述互连桥接、所述芯片和所述多个基板。
17.根据权利要求12所述的结构，其中所述盖板具有开口，所述开口容纳所述互连桥接到所述多个基板上的放置。
18.根据权利要求12所述的结构，还包括热界面材料，所述热界面材料在所述盖板的下侧与所述多个基板上的所述互连桥接和所述芯片上方之间。
19.根据权利要求12所述的结构，其中所述多个基板中的第一基板上的所述芯片具有不同于所述多个基板中的另一基板上的所述芯片的大小。
20.一种结构，包括：
系统卡；
具有布线层的多个基板，所述多个基板被附接到所述系统卡；
芯片，所述芯片通过所述布线层中的至少一个布线层被电连接到所述多个基板中的每个基板；
互连桥接，所述互连桥接将所述多个基板中的每个基板的所述芯片彼此电连接，并且从底侧或顶侧将所述多个基板彼此物理地连接；
热界面材料，所述热界面材料覆盖所述互连桥接和所述多个基板中的每个基板的所述芯片；以及
盖板，所述盖板被粘附到所述多个基板中的所选择的基板，并覆盖所述多个基板的所述芯片和所述热界面材料。
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