CN109727946A - 形成芯片封装体的方法 - Google Patents

形成芯片封装体的方法 Download PDF

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Publication number
CN109727946A
CN109727946A CN201810306349.6A CN201810306349A CN109727946A CN 109727946 A CN109727946 A CN 109727946A CN 201810306349 A CN201810306349 A CN 201810306349A CN 109727946 A CN109727946 A CN 109727946A
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China
Prior art keywords
chip
substrate
layer
conductive
packing
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CN201810306349.6A
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CN109727946B (zh
Inventor
郑心圃
蔡柏豪
庄博尧
许峯诚
陈硕懋
翁得期
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供形成芯片封装体的方法。方法包括将芯片置于再布线结构上。再布线结构包括第一绝缘层与第一线路层，且第一线路层位于第一绝缘层中并电性连接至芯片。方法亦包括经由导电结构将中介基板接合至再布线结构。芯片位于中介基板与再布线结构之间。中介基板具有与再布线结构相邻的凹陷。芯片的第一部分位于凹陷中。中介基板包括基板与导电通孔结构，且导电通孔结构穿过基板并经由导电结构电性连接至第一线路层。

Description

形成芯片封装体的方法
技术领域
本发明实施例关于芯片封装体，更特别关于其中介基板。
背景技术
半导体装置已用于多种电子应用中，比如个人电脑、手机、数码相机、与其他电子设备中。半导体装置的制作方法通常为依序沉积绝缘层或介电层、导电层、与半导体于半导体基板上，并采用光刻工艺与蚀刻工艺图案化多种材料层，以形成电路构件与单元于其上。
在半导体晶圆上通常形成有许多集成电路。半导体晶圆可切割成晶粒。接着可封装晶粒，且多种已发展的技术可用于封装。
发明内容
本公开一实施例提供形成芯片封装体的方法，包括：将芯片置于再布线结构上，其中再布线结构包括第一绝缘层与第一线路层，且第一线路层位于第一绝缘层中并电性连接至芯片；以及经由导电结构将中介基板接合至再布线结构，其中芯片位于中介基板与再布线结构之间，中介基板具有与再布线结构相邻的凹陷，芯片的第一部分位于凹陷中，中介基板包括基板与导电通孔结构，且导电通孔结构穿过基板并经由导电结构电性连接至第一线路层。
附图说明
图1A至图1J是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。
图1D-1是一些实施例中，图1D的芯片封装体的俯视图。
图2是一些实施例中，芯片封装体的剖视图。
图3A至图3B是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。
图4是一些实施例中，芯片封装体的剖视图。
图5是一些实施例中，芯片封装体的剖视图。
图6是一些实施例中，芯片封装体的剖视图。
图7A至图7B是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。
图8A是一些实施例中，芯片封装体的剖视图。
图8B是一些实施例中，图8A的芯片封装体的中介基板的俯视图。
图9A是一些实施例中，芯片封装体的剖视图。
图9B是一些实施例中，图9A的芯片封装体的中介基板的俯视图。
图10A是一些实施例中，芯片封装体的剖视图。
图10B是一些实施例中，图10A的芯片封装体的中介基板的俯视图。
图11是一些实施例中，芯片封装体的剖视图。
图12是一些实施例中，芯片封装体的剖视图。
图13是一些实施例中，芯片封装体的剖视图。
图14A至图14D是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。
图15是一些实施例中，芯片封装体的剖视图。
附图标记说明：
A 粘着层
C1、C3、C4、C5、C6、C7、C8、C9、C10、C11、C12、C13、C14、C15、100、300 芯片封装体
D1 深度
R 凹陷
R1 边缘凹陷
T、T1、T2、T3、T4、T5、T6、T7 厚度
WR1、WR 线路结构
W1、W2、W4、W5、W6、W7、W120、W170 宽度
110、220 载板
120、310 再布线结构
121、123、125、127、175、176、178、312 绝缘层
121a、123a、125a、127a 穿孔
122、128a、128b、144、173a、173b、314、316、324、430、440 导电垫
124、126、201、318、410、420 线路层
129、214、362、364 部分
130 坝结构
132、176a、178a 开口
140、320 芯片
142、172、1310、322 基板
142a、142b、172a、172b、178e、322a 表面
150、230、240、330 导电凸块
160、710、340、360、710 底填层
170 中介基板
170c 中心区
170r 周边区
170s 侧壁
174、1210、1320 导电通孔结构
178c、212、1410 沟槽
178d 凸起部分
179、510 导电层
180 导电结构
190 离型膜
210、350 成型层
712 倾斜侧壁
1330 焊料层
具体实施方式
下述公开内容提供许多不同实施例或实例以实施本公开的不同结构。下述特定构件与排列的实施例是用以简化本公开而非局限本公开。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多个实例可采用重复标号及/或符号使说明简化及明确，但这些重复不代表多种实施例中相同标号的元件之间具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。应理解的是，在下述方法之前、之中、或之后可进行额外步骤，且下述方法的一些其他实施例可置换或省略一些步骤。
此外亦可包含其他结构与工艺。举例来说，可包含测试结构，其有助于三维封装体或三维集成电路装置的验证测试。举例来说，测试结构可包含形成于再布线层中或基板上的测试垫，其可用于三维封装体或三维集成电路的测试，探针及/或探针卡、或类似物。可在中间结构与最终结构上进行验证测试。此外，此处所述的结构与方法可与良品晶粒的中间验证整合的测试方法结合，以增加良率并降低成本。
图1A至图1J是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。如图1A所示的一些实施例，提供载板110。在一些实施例中，载板110设置以在后续工艺步骤中，提供暂时的机械与结构支撑。在一些实施例中，载板110包含玻璃、硅、氧化硅、氧化铝、金属、上述的组合、及/或类似物。在一些实施例中，载板110包含金属框。
如图1A所示的一些实施例，再布线结构120形成于载板110上。再布线结构120的形成方法包含形成绝缘层121于载板110上；形成导电垫122于绝缘层121上与绝缘层121的穿孔121a中；形成绝缘层123于绝缘层121与导电垫122上；形成线路层124于绝缘层123上与绝缘层123的穿孔123a中；形成绝缘层125于绝缘层123与线路层124上；形成线路层126于绝缘层125上与绝缘层125的穿孔125a中；形成绝缘层127于绝缘层125与线路层126上；以及形成导电垫128a与128b于绝缘层127上与绝缘层127的穿孔127a中。在一些实施例中，导电垫128a比导电垫128b宽。在一些实施例中，导电垫128a围绕导电垫128b。
在一些实施例中，导电垫122接触载板110。在一些其他实施例中(未图示)，导电垫122与载板110分隔一段距离。在一些实施例中，线路层124与126彼此电性相连。在一些实施例中，导电垫122、128a、与128b电性连接至线路层124与126。
在一些实施例中，绝缘层121、123、125、与127的组成为绝缘材料，比如聚合物材料(如聚苯并恶唑、聚酰亚胺、或光敏材料)、氮化物(如氮化硅)、氧化物(如氧化硅)、氮氧化硅、或类似物。在一些实施例中，线路层124与126以及导电垫122、128a、与128b的组成为导电材料，比如金属(如铜、铝、或钨)。
如图1B所示的一些实施例，坝结构130形成于再布线结构120上。为简化附图，图1B至图1E所示的实施例仅显示一个坝结构130。在一些实施例中，坝结构130具有开口132。在一些实施例中，坝结构130为环状结构。在一些实施例中，坝结构130连续地围绕导电垫128b。
在一些实施例中，坝结构130的组成为聚合物材料或金属材料。坝结构130的形成方法包含形成坝材料层于再布线结构120上，并在坝材料层上进行光刻工艺与蚀刻工艺。若坝结构130的组成为光敏材料，则坝结构130的形成方法包括形成坝材料层于再布线结构120上，并进行光刻工艺。在一些实施例中，并未形成坝结构130。
如图1C所示的一些实施例，经由导电凸块150将芯片140接合至再布线结构120。为简化附图，图1C至图1E所示的一些实施例仅显示一个芯片140。在一些实施例中，芯片140位于坝结构130的开口132之上或之中。
在一些实施例中，芯片140具有基板142与导电垫144。在一些实施例中，基板142具有表面142a，其面对再布线结构120。在一些实施例中，导电垫144位于表面142a上。
在一些实施例中，电子单元(未图示)形成于基板142之上或之中。电子单元包含主动单元(如晶体管、二极管、或类似物)及/或被动单元(如电阻、电容、电感、或类似物)。在一些实施例中，导电垫144电性连接至电子单元。
在一些实施例中，基板142的组成为至少一半导体元素材料，比如单晶、多晶、或非晶结构的硅或锗。在一些其他实施例中，基板142的组成为半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、或砷化铟；半导体合金如硅锗或磷砷化镓；或上述的组合。
基板142亦可包含多层的半导体、绝缘层上半导体(如绝缘层上硅或绝缘层上锗)、或上述的组合。在一些实施例中，导电垫144的组成为导电材料如金属(例如铜、铝、镍、或上述的组合)。
在一些实施例中，导电凸块150位于导电垫128b与144之间，使导电垫128b电性连接至导电垫144。在一些实施例中，导电凸块150位于开口132中。在一些实施例中，导电凸块150的组成为焊料材料，比如锡与银，或另一合适的导电材料如金。在一些实施例中，导电凸块150为焊料球。
图1D-1是一些实施例中，图1D的芯片封装体的俯视图。如图1D与图1D-1所示的一些实施例，底填层160形成于芯片140与再布线结构120之间。在一些实施例中，坝结构130连续地围绕整个底填层160，以避免底填层160延伸至导电垫128a上。在一些实施例中，底填层160的组成为绝缘材料如聚合物材料或成型化合物材料(由环氧材料或填充材料所组成)。
如图1E所示的一些实施例，中介基板170经由导电结构180接合至再布线结构120。为简化附图，图1E所示的实施例仅显示一个中介基板170。在一些实施例中，芯片140位于中介基板170与再布线结构120之间。在一些实施例中，中介基板170具有与再布线结构120相邻的凹陷R。在一些实施例中，凹陷R面对再布线结构120。在一些实施例中，芯片140的一部分位于凹陷R中。
在一些实施例中，中介基板170包含基板172、导电垫173a与173b、导电通孔结构174、绝缘层175、176、与178、以及线路层(未图示)。在一些实施例中，基板172具有两个相对的表面172a与172b。在一些实施例中，表面172a面对再布线结构120。
基板172的组成可为纤维材料、聚合物材料、半导体材料、玻璃材料、金属材料、或另一合适材料。举例来说，纤维材料包含玻璃纤维材料。举例来说，半导体材料包含硅或锗。
在一些实施例中，导电垫173a位于表面172a上。在一些实施例中，导电垫173b位于表面172b上。在一些实施例中，导电通孔结构174穿过基板172。在一些实施例中，导电通孔结构174位于导电垫173a与173b之间，并连接至导电垫173a与173b。
在一些实施例中，线路层(未图示)形成于表面172b上，且电性连接至导电垫173b与导电通孔结构174。在一些实施例中，线路层(未图示)亦形成于表面172a上，且电性连接至导电垫173a与导电通孔结构174。在一些实施例中，导电通孔结构174、导电垫173a与173b、以及线路层的组成为导电材料如铜、铝、或钨。
在一些实施例中，绝缘层175位于导电通孔结构174与基板172之间、位于导电垫173a与基板172之间、并位于导电垫173b与基板172之间。在一些实施例中，绝缘层175使基板172以及导电垫173a与173b与导电通孔结构174之间可具有电性绝缘。
在一些实施例中，绝缘层176形成于表面172a上。在一些实施例中，绝缘层176具有开口176a，其分别露出上方的导电垫173a。在一些实施例中，绝缘层178形成于表面172b上。
在一些实施例中，绝缘层178具有开口178a，其分别露出下方的导电垫173b。在一些实施例中，凹陷R穿过绝缘层176并延伸至基板172。在一些实施例中，绝缘层175、176、与178的组成为绝缘材料，比如氧化物(如氧化硅)。
中介基板170亦可包含导电层179。在一些实施例中，导电层179分别形成于导电垫173b上。在一些实施例中，导电层179的组成为表面处理材料(如镍、钯、及/或金)或焊料材料(如锡与银，或另一合适的导电材料)。
如图2所示的一些实施例中，基板172的组成为绝缘材料，且未形成绝缘层175。如图2所示的一些实施例，中介基板170亦包含线路层201形成于基板172中。
在一些实施例中，线路层201使导电垫173b(比如凹陷R上的导电垫173b)电性连接至导电通孔结构174。图1E的中介基板170可置换为图2的中介基板170。
如图1E所示的一些实施例，导电结构180形成于导电垫173a与128a之间。在一些实施例中，导电结构180使导电垫173a电性连接至导电垫128a。在一些实施例中，导电结构180为导电凸块或导电柱。在一些实施例中，导电结构180的组成为导电材料，比如金属材料(如铜)或焊料材料(如锡与银)。
如图1F所示的一些实施例，离型膜190形成于中间基板170上以覆盖导电层179与导电垫173b。在一些实施例中，离型膜190用于避免后续工艺中形成的成型层覆盖导电层179与导电垫173b。离型膜190的组成为聚合物材料或另一合适材料。
之后如图1F所示的一些实施例，成型层210形成于离型膜190、中介基板170、再布线结构120、与芯片140之间。在一些实施例中，在成型层210上进行热工艺，以硬化成型层210。在一些实施例中，成型层210围绕中介基板170、芯片140、导电凸块150、底填层160、导电结构180、与坝结构130。成型层210的组成可为聚合物材料或另一合适的绝缘材料。
如图1G所示的一些实施例，移除离型膜190。如图1G所示的一些实施例，形成沟槽212于成型层210中。在一些实施例中，沟槽212穿过中介基板170之间的成型层210。并穿过不同中介基板170下的导电结构180之间的成型层210。
在一些实施例中，沟槽212将成型层210分为多个部分214。在一些实施例中，部分214彼此分隔。在一些实施例中，每一部分214围绕中介基板170的一者与其下的芯片140。在一些实施例中，沟槽212的形成方法采用切割工艺。
如图1H所示的一些实施例，移除载板110。如图1H所示的一些实施例，上下翻转再布线结构120。如图1H所示的一些实施例，再布线结构120与中介基板170位于载板220上。
如图1H所示的一些实施例，移除绝缘层121。在一些其他实施例中(未图示)，部分地移除绝缘层121以露出导电垫122。如图1H所示的一些实施例，分别形成导电凸块230于导电垫122上。在一些实施例中，导电凸块230的组成为焊料材料如锡与银，或另一合适的导电材料。
如图1H与图1I所示的一些实施例，在中介基板170之间的再布线结构120上进行切割工艺，以切割穿过再布线结构120。在一些实施例中，将再布线结构120切割成彼此分开的部分129。
在一些实施例中，切割工艺之后移除载板220。在一些实施例中，切割工艺后实质上形成芯片封装体100。为简化附图，图1I所示的一些实施例仅显示一个芯片封装体100。
如图1I所示的一些实施例，芯片封装体100具有再布线结构120的部分129、芯片140、中介基板170、成型层210的部分214、以及导电凸块150与230。在一些实施例中，中介基板170的厚度T1介于约50微米至约300微米之间。在一些实施例中，凹陷R的深度D1介于约20微米至约270微米之间。
如图1J所示的一些实施例，芯片封装体300经由导电凸块240接合至中介基板170。在一些实施例中，导电凸块240位于芯片封装体300与中介基板170之间。在一些实施例中，导电层179熔接至导电凸块240中。
在一些实施例中，芯片封装体300经由导电凸块240、中介基板170、与导电结构180电性连接至再布线结构120的线路层124与126。芯片封装体300包含存储装置(如动态随机存取存储装置)、被动装置、逻辑装置、射频装置、或另一合适装置。
在一些实施例中，芯片封装体300包含再布线结构310、芯片320、导电凸块330、底填层340、与成型层350。在一些实施例中，再布线结构310包含绝缘层312、导电垫314与316、以及线路层318。绝缘层312可为多层结构或单层结构。
在一些实施例中，线路层318与导电垫314及316的部分位于绝缘层312中。在一些实施例中，线路层318电性连接至导电垫314与316。在一些实施例中，绝缘层312的组成为绝缘材料，比如聚合物材料(如苯并恶唑、聚酰亚胺、或光敏材料)、氮化物(如氮化硅)、氧化物(如氧化硅)、氮氧化硅、或类似物。在一些实施例中，线路层318以及导电垫314与316的组成为导电材料，比如金属(如铜、铝、或钨)。
在一些实施例中，芯片320经由导电凸块330接合至再布线结构310。在一些实施例中，芯片320具有基板322与导电垫324。在一些实施例中，基板322具有表面322a，其面对再布线结构310。在一些实施例中，导电垫324位于表面322a上。
在一些实施例中，电子单元(未图示)邢成于基板322之上或之中。电子单元包含主动单元(如晶体管、二极管、或类似物)及/或被动单元(如电阻、电容、电感、或类似物)。在一些实施例中，导电垫324电性连接至电子单元。
在一些实施例中，基板322的组成为至少一半导体元素材料，比如单晶、多晶、或非晶结构的硅或锗。在一些其他实施例中，基板322的组成为半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、或砷化铟；半导体合金如硅锗或磷砷化镓；或上述的组合。
基板322亦可包含多层的半导体、绝缘层上半导体(如绝缘层上硅或绝缘层上锗)、或上述的组合。在一些实施例中，导电垫324的组成为导电材料如金属(例如铜或铝)。
在一些实施例中，导电凸块330位于导电垫314与324之间，并电性连接至导电垫314与324。在一些实施例中，导电凸块330的组成为焊料材料如锡与银，或另一合适的导电材料。
在一些实施例中，底填层340形成于芯片320与再布线结构310之间。在一些实施例中，底填层340的组成为绝缘材料如聚合物材料。在一些实施例中，成型层350形成于再布线结构310上以覆盖芯片320与底填层340。成型层350的组成可为聚合物材料或另一合适的绝缘材料。
如图1J所示的一些实施例，底填层360形成于再布线结构310与中介基板170(或成型层210)之间。在一些实施例中，底填层360围绕导电凸块240。在一些实施例中，底填层360的组成为绝缘材料如聚合物材料。在一些实施例中，此步骤实质上形成芯片封装体C1。
在一些实施例中，芯片封装体C1包含芯片封装体100与300、导电凸块240、以及底填层360。在一些实施例中，芯片封装体C1中的芯片140部分地或完全地位于中介基板170中。如此一来，一些实施例可减少芯片封装体C1的总厚度T2。
在一些实施例中，中介基板170的刚性大于成型层210的刚性。如此一来，中介基板170可减少芯片封装体100的卷曲现象。如此一来，一些实施例可改善芯片封装体100与300的接合良率。在一些实施例中，中介基板170可增进芯片封装体100的刚性与弯曲强度。
在一些实施例中，中介基板170为刚性基板。如此一来，一些实施例的中介基板170(包含导电垫173b)实质上不受成型层210与芯片140之间的热膨胀不匹配造成的应力影响。如此一来，一些实施例可改善导电垫173b与导电凸块240之间的接合良率。
图3A至图3B是一些实施例中，形成芯片封装体的工艺其多种阶段的剖视图。如图3A所示的一些实施例，在进行图1D的步骤之后，形成粘着层A于芯片140的基板142的表面142b上。在一些实施例中，粘着层A可为膜、胶层、或膏层。
在一些实施例中，粘着层A的组成为聚合物材料或高导热材料。在一些实施例中，高导热材料的导热性(k)大于约1Wm-1K-1。在一些实施例中，高导热材料包含氧化铝及/或石墨烯。在一些实施例中，粘着层A的形成方法采用涂布工艺、压合工艺、或沉积工艺。
如图3B所示的一些实施例，进行图1E至图1J的步骤。如图3B所示的一些实施例，形成芯片封装体C3。在一些实施例中，芯片封装体C3与图1J的芯片封装体C1类似，差别在于芯片封装体C3还具有粘着层A。在一些实施例中，粘着层A直接接触中介基板170(或基板172)与芯片140。
在一些实施例中，粘着层A用于使中介基板170接合至芯片140。在一些实施例中，自芯片140产生并传导至中介基板170的热，可通过粘着层A散热。
图4是一些实施例中，芯片封装体C4的剖视图。如图4所示的一些实施例，芯片封装体C4与图1J的芯片封装体C1类似，差别在于芯片封装体C4的凹陷R未穿过绝缘层176。如此一来，一些实施例的凹陷R并未延伸至基板172中。
在一些实施例中，中介基板170具有线路层410与420以及导电垫430与440。在一些实施例中，线路层410位于绝缘层176中，并连接至导电垫430。在一些实施例中，绝缘层176覆盖导电垫430的部分。在一些实施例中，线路层410、导电垫430、与绝缘层176一起组成线路结构WR1。
在一些实施例中，凹陷R未穿过线路结构WR1。在一些实施例中，导电结构180连接至导电垫430。在一些实施例中，线路层420位于绝缘层178中，并连接至导电垫440。在一些实施例中，绝缘层178覆盖导电垫440的部分。在一些实施例中，线路层420、导电垫440、与绝缘层178一起组成线路结构WR2。
在一些实施例中，导电凸块240连接至导电垫440。在一些实施例中，导电垫440与线路层420经由导电通孔结构174电性连接至导电垫430与线路层410。图1E至图1J与图3B的中介基板170可包含线路结构WR1与WR2，端视需求而定。
图5是一些实施例中，芯片封装体C5的剖视图。如图5所示的一些实施例，芯片封装体C5与图4的芯片封装体C4类似，差别在于芯片封装体C5的凹陷R穿过线路结构WR1与基板172。在一些实施例中，线路结构WR2还具有导电层510于绝缘层178中。在一些实施例中，凹陷R露出导电层510。
在一些实施例中，导电层510位于芯片140上。在一些实施例中，导电层510的尺寸(如宽度W1或面积)大于芯片140的尺寸(如宽度W2或面积)。在一些实施例中，导电层510的厚度T3介于约5微米至约50微米之间。在一些实施例中，线路层420的厚度T4介于约5微米至约40微米之间。
在一些实施例中，芯片140产生的热可经由导电层510散热。在一些实施例中，成型层210直接接触导电层510与芯片140。在一些实施例中，导电层510、导电通孔结构174、线路层420、与导电垫440的组成为相同材料。在一些实施例中，导电层510的组成为导电材料，比如金属(如铜、铝、或钨)。
图6是一些实施例中，芯片封装体C6的剖视图。如图6所示的一些实施例，芯片封装体C6与图4的芯片封装体C4类似，差别在于芯片封装体C6的凹陷R未延伸至基板172中。在一些实施例中，凹陷R仅位于线路结构WR1中。
图7A至图7B是一些实施例中，形成芯片封装体的工艺的多种阶段的剖视图。如图7A所示的一些实施例，在进行图1E的步骤之后，形成底填层710于中介基板170与其下方的再布线结构120之间，以及中介基板170与其下方的芯片140之间。在一些实施例中，底填层710的组成为绝缘材料如聚合物材料或成型化合物材料(由环氧化合物、填充物、树脂、或上述的组合所组成)。在一些实施例中，未形成底填层160，且底填层710填入芯片140与再布线结构120之间的间隙。
如图7B所示的一些实施例，进行图1G至图1J的步骤。如图7B所示的一些实施例，实质上形成芯片封装体C7。为简化附图，图7B所示的一些实施例仅显示一个芯片封装体C7。在一些实施例中，底填层710围绕芯片140、底填层160、坝结构130、导电结构180、与中介基板170的下侧部分。
在一些实施例中，底填层710直接接触芯片140、底填层160、坝结构130、导电结构180、中介基板170、与再布线结构120。在一些实施例中，底填层710覆盖中介基板170的侧壁170s的部分。
在一些实施例中，中介基板170的宽度W170小于再布线结构120的宽度W120。在一些实施例中，底填层710具有倾斜侧壁712。在一些实施例中，倾斜侧壁712围绕中介基板170。
图8A是一些实施例中，芯片封装体C8的剖视图。图8B是一些实施例中，图8A的芯片封装体C8的中介基板170的俯视图。如图8A与图8B所示的一些实施例，芯片封装体C8与图7B的芯片封装体C7类似，差别在于中介基板170的绝缘层178露出中介基板170的基板172其表面172b的一部分。
在一些实施例中，中介基板170具有中心区170c与围绕中心区170c的周边区170r。在一些实施例中，表面172b的露出部分位于周边区170r中。在一些实施例中，表面172b的露出部分连续地围绕所有的绝缘层178。
在一些实施例中，中介基板170具有边缘凹陷R1。在一些实施例中，绝缘层178的侧壁178b与表面172b的露出部分围绕边缘凹陷R1。在一些实施例中，边缘凹陷R1具有宽度W3，其介于约20微米至约150微米之间。
在将芯片封装体300接合至中介基板170之前，若底填层710沿着中介基板170的侧壁170s延伸于基板172的表面172b上，则边缘凹陷R1可容纳表面172b上的底填层710，以避免底填层710延伸至导电垫173b上而阻碍导电垫173b与导电凸块240之间的接合。
在一些实施例中，芯片封装体300与中介基板170之间的底填层360填入边缘凹陷R1。在一些实施例中，底填层360的部分362延伸至中介基板170中。在一些实施例中，部分362为环形。在一些实施例中，部分362连续地围绕整个绝缘层178。在一些实施例中，未形成底填层360。
图9A是一些实施例中，芯片封装体C9的剖视图。图9B是一些实施例中，图9A的芯片封装体C9的中介基板170的俯视图。如图9A与图9B所示的一些实施例，芯片封装体C9与图7B的芯片封装体C7类似，差别在于中介基板170的绝缘层178具有沟槽178c。
在一些实施例中，沟槽178c露出周边区170r中的基板172的表面172b。在一些实施例中，沟槽178c围绕所有的导电垫173b。在一些实施例中，沟槽178c的宽度W4介于约20微米至约150微米之间。
沟槽178c用于容纳延伸至表面172b上的底填层710，以避免底填层710更延伸至导电垫173b上而阻碍导电垫173b与导电凸块240之间的接合。
在一些实施例中，芯片封装体300与中介基板170之间的底填层360填入沟槽178c。在一些实施例中，底填层360的部分364延伸至中介基板170中。在一些实施例中，部分364为环形。在一些实施例中，部分364连续地围绕所有的导电垫173b。
图10A是一些实施例中，芯片封装体C10的剖视图。图10B是一些实施例中，图10A的芯片封装体C10其中介基板170的俯视图。如图10A与图10B所示的一些实施例，芯片封装体C10与图7B的芯片封装体C7类似，差别在于中介基板170的绝缘层178具有凸起部分178d。在一些实施例中，凸起部分178d自绝缘层178的表面178e凸起。
在一些实施例中，凸起部分178d连续地围绕所有的导电垫173b。在一些实施例中，凸起部分178d为环形。在一些实施例中，凸起部分178d延伸至芯片封装体300与中介基板170之间的底填层360中。
在一些实施例中，凸起部分178d的宽度W5介于约20微米至约150微米之间。在一些实施例中，凸起部分178d的厚度T介于约10微米至约80微米之间。在一些实施例中，凸起部分178d用于避免底填层710延伸至导电垫173b上而阻碍导电垫173b与导电凸块240之间的接合。
图11是一些实施例中，芯片封装体C11的剖视图。如图11所示的一些实施例，芯片封装体C11与图7B的芯片封装体C7类似，差别在于中介基板170的宽度W6实质上等于或大于再布线结构120的宽度W7。
在一些实施例中，底填层710形成于中介基板170与再布线结构120之间。在一些实施例中，底填层710并未延伸至中介基板170的侧壁170s上。在一些实施例中，底填层710具有倾斜侧壁712。在一些实施例中，倾斜侧壁712位于中介基板170与再布线结构120之间。
图12是一些实施例中，芯片封装体C12的剖视图。如图12所示的一些实施例，芯片封装体C12与图1J的芯片封装体C1类似，差别在于芯片封装体C12的中介基板170还具有导电通孔结构1210。
在一些实施例中，导电通孔结构1210穿过绝缘层176。在一些实施例中，导电通孔结构1210连接至其上方的导电垫173a与其下方的导电结构180。在一些实施例中，导电通孔结构1210直接接触其下方的导电结构180。
在一些实施例中，基板172与绝缘层178的总厚度T5介于约20微米至约100微米之间。在一些实施例中，绝缘层176的厚度T6介于约30微米至约200微米之间。在一些实施例中，中介基板170的总厚度T7介于约50微米至约300微米之间。在一些实施例中，凹陷R的深度D1介于约30微米至约200微米之间。
在一些实施例中，绝缘层176与178的组成为不同材料。在一些实施例中，绝缘层176的组成为聚合物材料。在一些实施例中，绝缘层176包含Ajinomoto增层膜。在一些实施例中，绝缘层178的组成为聚合物材料，比如阻焊材料(如聚酰亚胺)。在一些实施例中，基板172的组成为绝缘材料如聚合物材料。
图13是一些实施例中，芯片封装体C13的剖视图。如图13所示的一些实施例，芯片封装体C13与图1J的芯片封装体C1类似，差别在于芯片封装体C13还包含基板1310、导电通孔结构1320、与焊料层1330。在一些实施例中，凹陷R穿过基板1310。基板1310的组成可为聚合物材料、纤维材料、半导体材料、玻璃材料、金属材料、或另一合适材料。
在一些实施例中，导电通孔结构1320穿过基板1310。在一些实施例中，导电通孔结构1320连接至其下方的导电结构180。在一些实施例中，基板1310与导电通孔结构1320围绕芯片140。在一些实施例中，导电通孔结构1320的组成为导电材料如铜、铝、或钨。
在一些实施例中，焊料层1330位于导电通孔结构1320与导电垫173a之间，并电性连接至导电通孔结构1320与导电垫173a。在一些实施例中，焊料层1330的组成为焊料材料如锡与银，或另一合适的导电材料。
图14A至图14D是一些实施例中，形成芯片封装体的工艺其多种阶段的剖视图。如图14A所示的一些实施例，在进行图1E所示的步骤后，形成沟槽1410于再布线结构120中。在一些实施例中，沟槽1410穿过中介基板170之间以及不同中介基板170下的导电结构180之间的再布线结构120。
在一些实施例中，沟槽1410将再布线结构120分为多个部分129。在一些实施例中，部分129彼此分隔。在一些实施例中，每一部分129位于中介基板170的一者下。在一些实施例中，沟槽1410的形成方法采用切割工艺。
如图14A所示的一些实施例，离型膜190形成于中介基板170上以覆盖导电层179与导电通孔结构174。如图14A所示的一些实施例，之后形成成型层210于离型膜190、中介基板170、部分129、与芯片140之间。在一些实施例中，成型层210围绕中介基板170、芯片140、导电凸块150、底填层160、坝结构130、与部分129。
如图14B所示的一些实施例，移除离型膜190。如图14B所示的一些实施例，沟槽212形成于成型层210中。在一些实施例中，沟槽212穿过中介基板170之间，以及不同中介基板170下的导电结构180之间的成型层210。
在一些实施例中，沟槽212将成型层210分成多个部分214。在一些实施例中，部分214彼此分隔。在一些实施例中，每一部分214围绕中介基板170的一者，以及中介基板170的一者下方的芯片140与部分129。在一些实施例中，沟槽212的形成方法采用切割工艺。
如图14C所示的一些实施例，移除载板110。如图14C所示的一些实施例，上下翻转中介基板170。如图14C所示的一些实施例，中介基板170位于载板220上。如图14C所示的一些实施例，移除部分129的绝缘层121。
在一些实施例中，在移除绝缘层121时，亦移除与绝缘层121相邻的成型层210其部分214。在一些其他实施例中(未图示)，在移除绝缘层121之后，仍保留与绝缘层121相邻的成型层210其部分214。如图14C所示的一些实施例，导电凸块230分别形成于导电垫122上。在一些实施例中，此步骤实质上形成芯片封装体100。
如图14D所示的一些实施例，移除载板220。如图14D所示的一些实施例，进行图1J所示的步骤以形成芯片封装体C14。为简化附图，图14D所示的一些实施例仅显示一个芯片封装体C14。在一些实施例中，芯片封装体C14中的成型层210围绕再布线结构120。
图15是一些施例中，芯片封装体C15的剖视图。如图15所示的一些实施例，芯片封装体C15与图1J的芯片封装体C1类似，差别在于芯片封装体C15的坝结构130其顶部延伸至中介基板170的凹陷R中。
图7A至图14D所示的中介基板170可具有图4、图5、或图6的线路结构WR1与WR2。图7A至图14D的中介基板170可取代为图2与图4至图6的中介基板170。
在一些实施例中，提供芯片封装体与其形成方法。形成芯片封装体的方法将中介基板接合至再布线结构，芯片位于中介基板与再布线结构之间，且芯片部分地位于中介基板中。中介基板可减少芯片封装体的卷曲，且芯片封装体包含中介基板、再布线结构、与芯片。如此一来，可改善芯片封装体与封装结构之间的接合良率。中介基板可增加芯片封装体的刚性与机械强度。中介基板的线路层与导电垫，实质上不受芯片封装体的芯片与成型层之间的热膨胀不匹配所产生的应力影响。由于芯片部分地位于中介基板中，可减少芯片封装体的总厚度。
在一些实施例中，提供形成芯片封装体的方法。方法包括将芯片置于再布线结构上。再布线结构包括第一绝缘层与第一线路层，且第一线路层位于第一绝缘层中并电性连接至芯片。方法亦包括经由导电结构将中介基板接合至再布线结构。芯片位于中介基板与再布线结构之间。中介基板具有与再布线结构相邻的凹陷。芯片的第一部分位于凹陷中。中介基板包括基板与导电通孔结构，且导电通孔结构穿过基板并经由导电结构电性连接至第一线路层。
在一些实施例中，上述方法还包括在将中介基板接合至再布线结构之后，形成底填层于中介基板与再布线结构之间，以及中介基板与芯片之间。
在一些实施例中，上述方法还包括在将中介基板接合至再布线结构之前，形成坝结构于再布线结构上，其中坝结构具有开口，且芯片位于开口之上或之中。
在一些实施例中，上述方法还包括在将中介基板接合至再布线结构之后，将封装结构接合至中介基板。
在一些实施例中，上述方法的中介基板还包括第一线路结构，基板具有面对再布线结构的第一表面，第一线路结构位于第一表面上，第一线路结构包括第二绝缘层与第二绝缘层中的第二线路层，且凹陷位于第一线路结构中。
在一些实施例中，上述方法的凹陷穿过第一线路结构。
在一些实施例中，上述方法的凹陷延伸至基板中。
在一些实施例中，上述方法的基板具有远离再布线结构的第二表面，中介基板还包括第二线路结构于第二表面与凹陷上，第二线路结构包括第三绝缘层与第三绝缘层中的导电层，且包陷更穿过基板并露出导电层。
在一些实施例中，上述方法的基板组成为纤维材料、聚合物材料、半导体材料、玻璃材料、或金属材料。
在一些实施例中，提供形成芯片封装体的方法。方法包括将芯片置于再布线结构上。再布线结构包括绝缘层与第一线路层，且第一线路层位于绝缘层中并电性连接至芯片。上述方法包括经由第一导电凸块将中介基板接合至再布线结构。芯片位于中介基板与再布线结构之间。中介基板具有与再布线结构相邻的凹陷，且芯片的一部分位于凹陷中。上述方法包括形成成型层，其围绕中介基板与第一导电凸块。成型层部分地位于中介基板与再布线结构之间，且部分地位于中介基板与芯片之间。
在一些实施例中，上述方法还包括在将芯片置于再布线结构上之前，形成再布线结构于载板上；以及在形成成型层之后，移除载板。
在一些实施例中，上述方法还包括在将芯片置于再布线结构上之前，形成坝结构于再布线结构上，其中坝结构具有开口。将芯片置于再布线结构上的步骤包括经由第二导电凸块接合芯片至再布线结构，且第二导电凸块在开口中。
在一些实施例中，上述方法的坝结构其顶部位于凹陷中。
在一些实施例中，上述方法的中介基板包括基板、导电通孔结构、与第二线路层，第二导电通孔结构穿过基板并经由第一导电凸块电性连接至第一线路层，第二线路层位于基板之中或之上，且第二线路层与成型层及芯片之间隔有基板。
在一些实施例中，上述方法还包括在将中介基板接合至再布线结构之前，形成粘着层于芯片的上表面上，其中粘着层位于芯片与中介基板之间。
在一些实施例中，提供芯片封装体。芯片封装体包括再布线结构，其包括绝缘层与线路层。线路层位于绝缘层中。芯片封装体包括芯片于再布线结构上，且芯片电性连接至线路层。芯片封装体包括中介基板于再布线结构与芯片上。芯片的一部分位于中介基板中。芯片封装体包括中介基板与再布线结构之间的导电结构，且导电结构电性连接至线路层。
在一些实施例中，上述芯片封装体还包括封装结构于中介基板上，其中封装结构经由中介基板电性连接至再布线结构的线路层。
在一些实施例中，上述芯片封装体还包括底填层于芯片封装体与中介基板之间，其中底填层的一部分为环形且延伸至中介基板中。
在一些实施例中，上述芯片封装体还包括底填层于芯片封装体与中介基板之间，其中中介基板的一部分为环形且延伸至底填层中。
在一些实施例中，上述芯片封装体还包括成型层于中介基板与再布线结构之间以及中介基板与芯片之间，且成型层围绕中介基板与导电结构。
上述实施例的特征有利于本领域技术人员理解本公开。本领域技术人员应理解可采用本公开作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本领域技术人员亦应理解，这些等效置换并未脱离本公开精神与范围，并可在未脱离本公开的权利要求的精神与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种形成芯片封装体的方法，包括：
将一芯片置于一再布线结构上，其中再布线结构包括一第一绝缘层与一第一线路层，且该第一线路层位于该第一绝缘层中并电性连接至该芯片；以及
经由一导电结构将一中介基板接合至该再布线结构，其中该芯片位于该中介基板与该再布线结构之间，该中介基板具有与该再布线结构相邻的一凹陷，该芯片的第一部分位于该凹陷中，该中介基板包括一基板与一导电通孔结构，且该导电通孔结构穿过该基板并经由该导电结构电性连接至该第一线路层。
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US20190131284A1 (en) 2019-05-02
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US20230260890A1 (en) 2023-08-17
US10515827B2 (en) 2019-12-24
US20200126812A1 (en) 2020-04-23
US10985100B2 (en) 2021-04-20
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TW201919165A (zh) 2019-05-16

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