TWI751334B - 晶片封裝體與其方法 - Google Patents

晶片封裝體與其方法 Download PDF

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TWI751334B
TWI751334B TW107116284A TW107116284A TWI751334B TW I751334 B TWI751334 B TW I751334B TW 107116284 A TW107116284 A TW 107116284A TW 107116284 A TW107116284 A TW 107116284A TW I751334 B TWI751334 B TW I751334B
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Taiwan
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conductive
chip
layer
interposer substrate
redistribution structure
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TW107116284A
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TW201919165A (zh
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鄭心圃
蔡柏豪
莊博堯
許峯誠
陳碩懋
翁得期
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台灣積體電路製造股份有限公司
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Abstract

提供形成晶片封裝體的方法。方法包括將晶片置於再佈線結構上。再佈線結構包括第一絕緣層與第一線路層，且第一線路層位於第一絕緣層中並電性連接至晶片。方法亦包括經由導電結構將中介基板接合至再佈線結構。晶片位於中介基板與再佈線結構之間。中介基板具有與再佈線結構相鄰的凹陷。晶片的第一部份位於凹陷中。中介基板包括基板與導電通孔結構，且導電通孔結構穿過基板並經由導電結構電性連接至第一線路層。

Description

晶片封裝體與其方法
本發明實施例關於晶片封裝體，更特別關於其中介基板。
半導體裝置已用於多種電子應用中，比如個人電腦、手機、數位相機、與其他電子設備中。半導體裝置的製作方法通常為依序沉積絕緣層或介電層、導電層、與半導體於半導體基板上，並採用光微影製程與蝕刻製程圖案化多種材料層，以形成電路構件與單元於其上。
在半導體晶圓上通常形成有許多積體電路。半導體晶圓可切割成晶粒。接著可封裝晶粒，且多種已發展的技術可用於封裝。
本發明一實施例提供形成晶片封裝體的方法，包括：將晶片置於再佈線結構上，其中再佈線結構包括第一絕緣層與第一線路層，且第一線路層位於第一絕緣層中並電性連接至晶片；以及經由導電結構將中介基板接合至再佈線結構，其中晶片位於中介基板與再佈線結構之間，中介基板具有與再佈線結構相鄰的凹陷，晶片的第一部份位於凹陷中，中介基板包括基板與導電通孔結構，且導電通孔結構穿過基板並經由導電 結構電性連接至第一線路層。
A:黏著層
C1、C3、C4、C5、C6、C7、C8、C9、C10、C11、C12、C13、C14、C15、100、300:晶片封裝體
D1:深度
R:凹陷
R1:邊緣凹陷
T、T1、T2、T3、T4、T5、T6、T7:厚度
WR1、WR:線路結構
W1、W2、W4、W5、W6、W7、W120、W170:寬度
110、220:載板
120、310:再佈線結構
121、123、125、127、175、176、178、312:絕緣層
121a、123a、125a、127a:穿孔
122、128a、128b、144、173a、173b、314、316、324、430、440:導電墊
124、126、201、318、410、420:線路層
129、214、362、364:部份
130:壩結構
132、176a、178a:開口
140、320:晶片
142、172、1310、322:基板
142a、142b、172a、172b、178e、322a:表面
150、230、240、330:導電凸塊
160、710、340、360、710:底填層
170:中介基板
170c:中心區
170r:周邊區
170s:側壁
174、1210、1320:導電通孔結構
178c、212、1410:溝槽
178d:凸起部份
179、510:導電層
180:導電結構
190:離型膜
210、350:成型層
712:傾斜側壁
1330:焊料層
第1A至1J圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。
第1D-1圖係一些實施例中，第1D圖的晶片封裝體其上視圖。
第2圖係一些實施例中，晶片封裝體的剖視圖。
第3A至3B圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。
第4圖係一些實施例中，晶片封裝體的剖視圖。
第5圖係一些實施例中，晶片封裝體的剖視圖。
第6圖係一些實施例中，晶片封裝體的剖視圖。
第7A至7B圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。
第8A圖係一些實施例中，晶片封裝體的剖視圖。
第8B圖係一些實施例中，第8A圖的晶片封裝體其中介基板的上視圖。
第9A圖係一些實施例中，晶片封裝體的剖視圖。
第9B圖係一些實施例中，第9A圖的晶片封裝體其中介基板的上視圖。
第10A圖係一些實施例中，晶片封裝體的剖視圖。
第10B圖係一些實施例中，第10A圖的晶片封裝體其中介基板的上視圖。
第11圖係一些實施例中，晶片封裝體的剖視圖。
第12圖係一些實施例中，晶片封裝體的剖視圖。
第13圖係一些實施例中，晶片封裝體的剖視圖。
第14A至14D圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。
第15圖係一些實施例中，晶片封裝體的剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明的多個實例可採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。應理解的是，在下述方法之前、之中、或之後可進行額外步驟，且下述方法的一些其他實施例可置換或省略一些步驟。
此外亦可包含其他結構與製程。舉例來說，可包含測試結構，其有助於三維封裝體或三維積體電路裝置的驗證 測試。舉例來說，測試結構可包含形成於再佈線層中或基板上的測試墊，其可用於三維封裝體或三維積體電路的測試，探針及/或探針卡、或類似物。可在中間結構與最終結構上進行驗證測試。此外，此處所述的結構與方法可與良品晶粒的中間驗證整合的測試方法結合，以增加良率並降低成本。
第1A至1J圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。如第1A圖所示的一些實施例，提供載板110。在一些實施例中，載板110設置以在後續製程步驟中，提供暫時的機械與結構支撐。在一些實施例中，載板110包含玻璃、矽、氧化矽、氧化鋁、金屬、上述之組合、及/或類似物。在一些實施例中，載板110包含金屬框。
如第1A圖所示的一些實施例，再佈線結構120形成於載板110上。再佈線結構120的形成方法包含形成絕緣層121於載板110上；形成導電墊122於絕緣層121上與絕緣層121的穿孔121a中；形成絕緣層123於絕緣層121與導電墊122上；形成線路層124於絕緣層123上與絕緣層123的穿孔123a中；形成絕緣層125於絕緣層123與線路層124上；形成線路層126於絕緣層125上與絕緣層125的穿孔125a中；形成絕緣層127於絕緣層125與線路層126上；以及形成導電墊128a與128b於絕緣層127上與絕緣層127的穿孔127a中。在一些實施例中，導電墊128a比導電墊128b寬。在一些實施例中，導電墊128a圍繞導電墊128b。
在一些實施例中，導電墊122接觸載板110。在一些其他實施例中(未圖示)，導電墊122與載板110分隔一段距離。在一些實施例中，線路層124與126彼此電性相連。在一些 實施例中，導電墊122、128a、與128b電性連接至線路層124與126。
在一些實施例中，絕緣層121、123、125、與127的組成為絕緣材料，比如聚合物材料(如聚苯并噁唑、聚醯亞胺、或光敏材料)、氮化物(如氮化矽)、氧化物(如氧化矽)、氮氧化矽、或類似物。在一些實施例中，線路層124與126以及導電墊122、128a、與128b的組成為導電材料，比如金屬(如銅、鋁、或鎢)。
如第1B圖所示的一些實施例，壩結構130形成於再佈線結構120上。為簡化圖式，第1B至1E圖所示的實施例僅顯示一個壩結構130。在一些實施例中，壩結構130具有開口132。在一些實施例中，壩結構130為環狀結構。在一些實施例中，壩結構130連續地圍繞導電墊128b。
在一些實施例中，壩結構130的組成為聚合物材料或金屬材料。壩結構130的形成方法包含形成壩材料層於再佈線結構120上，並在壩材料層上進行光微影製程與蝕刻製程。若壩結構130的組成為光敏材料，則壩結構130的形成方法包括形成壩材料層於再佈線結構120上，並進行光微影製程。在一些實施例中，並未形成壩結構130。
如第1C圖所示的一些實施例，經由導電凸塊150將晶片140接合至再佈線結構120。為簡化圖式，第1C至1E圖所示的一些實施例僅顯示一個晶片140。在一些實施例中，晶片140位於壩結構130的開口132之上或之中。
在一些實施例中，晶片140具有基板142與導電墊 144。在一些實施例中，基板142具有表面142a，其面對再佈線結構120。在一些實施例中，導電墊144位於表面142a上。
在一些實施例中，電子單元(未圖示)形成於基板142之上或之中。電子單元包含主動單元(如電晶體、二極體、或類似物)及/或被動單元(如電阻、電容、電感、或類似物)。在一些實施例中，導電墊144電性連接至電子單元。
在一些實施例中，基板142的組成為至少一半導體元素材料，比如單晶、多晶、或非晶結構的矽或鍺。在一些其他實施例中，基板142的組成為半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦；半導體合金如矽鍺或磷砷化鎵；或上述之組合。
基板142亦可包含多層的半導體、絕緣層上半導體(如絕緣層上矽或絕緣層上鍺)、或上述之組合。在一些實施例中，導電墊144的組成為導電材料如金屬(例如銅、鋁、鎳、或上述之組合)。
在一些實施例中，導電凸塊150位於導電墊128b與144之間，使導電墊128b電性連接至導電墊144。在一些實施例中，導電凸塊150位於開口132中。在一些實施例中，導電凸塊150的組成為焊料材料，比如錫與銀，或另一合適的導電材料如金。在一些實施例中，導電凸塊150為焊料球。
第1D-1圖係一些實施例中，第1D圖的晶片封裝體其上視圖。如第1D與1D-1圖所示的一些實施例，底填層160形成於晶片140與再佈線結構120之間。在一些實施例中，壩結構130連續地圍繞整個底填層160，以避免底填層160延伸至導電 墊128a上。在一些實施例中，底填層160的組成為絕緣材料如聚合物材料或成型化合物材料(由環氧材料或填充材料所組成)。
如第1E圖所示的一些實施例，中介基板170經由導電結構180接合至再佈線結構120。為簡化圖式，第1E圖所示的實施例僅顯示一個中介基板170。在一些實施例中，晶片140位於中介基板170與再佈線結構120之間。在一些實施例中，中介基板170具有與再佈線結構120相鄰的凹陷R。在一些實施例中，凹陷R面對再佈線結構120。在一些實施例中，晶片140的一部份位於凹陷R中。
在一些實施例中，中介基板170包含基板172、導電墊173a與173b、導電通孔結構174、絕緣層175、176、與178、以及線路層(未圖示)。在一些實施例中，基板172具有兩個相對的表面172a與172b。在一些實施例中，表面172a面對再佈線結構120。
基板172的組成可為纖維材料、聚合物材料、半導體材料、玻璃材料、金屬材料、或另一合適材料。舉例來說，纖維材料包含玻璃纖維材料。舉例來說，半導體材料包含矽或鍺。
在一些實施例中，導電墊173a位於表面172a上。在一些實施例中，導電墊173b位於表面172b上。在一些實施例中，導電通孔結構174穿過基板172。在一些實施例中，導電通孔結構174位於導電墊173a與173b之間，並連接至導電墊173a與173b。
在一些實施例中，線路層(未圖示)形成於表面172b上，且電性連接至導電墊173b與導電通孔結構174。在一些實施例中，線路層(未圖示)亦形成於表面172a上，且電性連接至導電墊173a與導電通孔結構174。在一些實施例中，導電通孔結構174、導電墊173a與173b、以及線路層的組成為導電材料如銅、鋁、或鎢。
在一些實施例中，絕緣層175位於導電通孔結構174與基板172之間、位於導電墊173a與基板172之間、並位於導電墊173b與基板172之間。在一些實施例中，絕緣層175使基板172以及導電墊173a與173b與導電通孔結構174之間可具有電性絕緣。
在一些實施例中，絕緣層176形成於表面172a上。在一些實施例中，絕緣層176具有開口176a，其分別露出上方的導電墊173a。在一些實施例中，絕緣層178形成於表面172b上。
在一些實施例中，絕緣層178具有開口178a，其分別露出下方的導電墊173b。在一些實施例中，凹陷R穿過絕緣層176並延伸至基板172。在一些實施例中，絕緣層175、176、與178的組成為絕緣材料，比如氧化物(如氧化矽)。
中介基板170亦可包含導電層179。在一些實施例中，導電層179分別形成於導電墊173b上。在一些實施例中，導電層179的組成為表面處理材料(如鎳、鈀、及/或金)或焊料材料(如錫與銀，或另一合適的導電材料)。
如第2圖所示的一些實施例中，基板172的組成為 絕緣材料，且未形成絕緣層175。如第2圖所示的一些實施例，中介基板170亦包含線路層201形成於基板172中。
在一些實施例中，線路層201使導電墊173b(比如凹陷R上的導電墊173b)電性連接至導電通孔結構174。第1E圖的中介基板170可置換為第2圖的中介基板170。
如第1E圖所示的一些實施例，導電結構180形成於導電墊173a與128a之間。在一些實施例中，導電結構180使導電墊173a電性連接至導電墊128a。在一些實施例中，導電結構180為導電凸塊或導電柱。在一些實施例中，導電結構180的組成為導電材料，比如金屬材料(如銅)或焊料材料(如錫與銀)。
如第1F圖所示的一些實施例，離型膜190形成於中間基板170上以覆蓋導電層179與導電墊173b。在一些實施例中，離型膜190用於避免後續製程中形成的成型層覆蓋導電層179與導電墊173b。離型膜190的組成為聚合物材料或另一合適材料。
之後如第1F圖所示的一些實施例，成型層210形成於離型膜190、中介基板170、再佈線結構120、與晶片140之間。在一些實施例中，在成型層210上進行熱製程，以硬化成型層210。在一些實施例中，成型層210圍繞中介基板170、晶片140、導電凸塊150、底填層160、導電結構180、與壩結構130。成型層210的組成可為聚合物材料或另一合適的絕緣材料。
如第1G圖所示的一些實施例，移除離型膜190。如第1G圖所示的一些實施例，形成溝槽212於成型層210中。在一些實施例中，溝槽212穿過中介基板170之間的成型層210。並 穿過不同中介基板170下的導電結構180之間的成型層210。
在一些實施例中，溝槽212將成型層210分為多個部份214。在一些實施例中，部份214彼此分隔。在一些實施例中，每一部份214圍繞中介基板170之一者與其下的晶片140。在一些實施例中，溝槽212的形成方法採用切割製程。
如第1H圖所示的一些實施例，移除載板110。如第1H圖所示的一些實施例，上下翻轉再佈線結構120。如第1H圖所示的一些實施例，再佈線結構120與中介基板170位於載板220上。
如第1H圖所示的一些實施例，移除絕緣層121。在一些其他實施例中(未圖示)，部份地移除絕緣層121以露出導電墊122。如第1H圖所示的一些實施例，分別形成導電凸塊230於導電墊122上。在一些實施例中，導電凸塊230的組成為焊料材料如錫與銀，或另一合適的導電材料。
如第1H與1I圖所示的一些實施例，在中介基板170之間的再佈線結構120上進行切割製程，以切割穿過再佈線結構120。在一些實施例中，將再佈線結構120切割成彼此分開的部份129。
在一些實施例中，切割製程之後移除載板220。在一些實施例中，切割製程後實質上形成晶片封裝體100。為簡化圖式，第1I圖所示的一些實施例僅顯示一個晶片封裝體100。
如第1I圖所示的一些實施例，晶片封裝體100具有再佈線結構120的部份129、晶片140、中介基板170、成型層210的部份214、以及導電凸塊150與230。在一些實施例中，中介 基板170的厚度T1介於約50微米至約300微米之間。在一些實施例中，凹陷R的深度D1介於約20微米至約270微米之間。
如第1J圖所示的一些實施例，晶片封裝體300經由導電凸塊240接合至中介基板170。在一些實施例中，導電凸塊240位於晶片封裝體300與中介基板170之間。在一些實施例中，導電層179熔接至導電凸塊240中。
在一些實施例中，晶片封裝體300經由導電凸塊240、中介基板170、與導電結構180電性連接至再佈線結構120的線路層124與126。晶片封裝體300包含記憶裝置(如動態隨機存取記憶裝置)、被動裝置、邏輯裝置、射頻裝置、或另一合適裝置。
在一些實施例中，晶片封裝體300包含再佈線結構310、晶片320、導電凸塊330、底填層340、與成型層350。在一些實施例中，再佈線結構310包含絕緣層312、導電墊314與316、以及線路層318。絕緣層312可為多層結構或單層結構。
在一些實施例中，線路層318與導電墊314及316的部份位於絕緣層312中。在一些實施例中，線路層318電性連接至導電墊314與316。在一些實施例中，絕緣層312的組成為絕緣材料，比如聚合物材料(如苯并噁唑、聚醯亞胺、或光敏材料)、氮化物(如氮化矽)、氧化物(如氧化矽)、氮氧化矽、或類似物。在一些實施例中，線路層318以及導電墊314與316的組成為導電材料，比如金屬(如銅、鋁、或鎢)。
在一些實施例中，晶片320經由導電凸塊330接合至再佈線結構310。在一些實施例中，晶片320具有基板322與 導電墊324。在一些實施例中，基板322具有表面322a，其面對再佈線結構310。在一些實施例中，導電墊324位於表面322a上。
在一些實施例中，電子單元(未圖示)邢成於基板322之上或之中。電子單元包含主動單元(如電晶體、二極體、或類似物)及/或被動單元(如電阻、電容、電感、或類似物)。在一些實施例中，導電墊324電性連接至電子單元。
在一些實施例中，基板322的組成為至少一半導體元素材料，比如單晶、多晶、或非晶結構的矽或鍺。在一些其他實施例中，基板322的組成為半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦；半導體合金如矽鍺或磷砷化鎵；或上述之組合。
基板322亦可包含多層的半導體、絕緣層上半導體(如絕緣層上矽或絕緣層上鍺)、或上述之組合。在一些實施例中，導電墊324的組成為導電材料如金屬(例如銅或鋁)。
在一些實施例中，導電凸塊330位於導電墊314與324之間，並電性連接至導電墊314與324。在一些實施例中，導電凸塊330的組成為焊料材料如錫與銀，或另一合適的導電材料。
在一些實施例中，底填層340形成於晶片320與再佈線結構310之間。在一些實施例中，底填層340的組成為絕緣材料如聚合物材料。在一些實施例中，成型層350形成於再佈線結構310上以覆蓋晶片320與底填層340。成型層350的組成可為聚合物材料或另一合適的絕緣材料。
如第1J圖所示的一些實施例，底填層360形成於再 佈線結構310與中介基板170(或成型層210)之間。在一些實施例中，底填層360圍繞導電凸塊240。在一些實施例中，底填層360的組成為絕緣材料如聚合物材料。在一些實施例中，此步驟實質上形成晶片封裝體C1。
在一些實施例中，晶片封裝體C1包含晶片封裝體100與300、導電凸塊240、以及底填層360。在一些實施例中，晶片封裝體C1中的晶片140部份地或完全地位於中介基板170中。如此一來，一些實施例可減少晶片封裝體C1的總厚度T2。
在一些實施例中，中介基板170的剛性大於成型層210的剛性。如此一來，中介基板170可減少晶片封裝體100的捲曲現象。如此一來，一些實施例可改善晶片封裝體100與300的接合良率。在一些實施例中，中介基板170可增進晶片封裝體100的剛性與彎曲強度。
在一些實施例中，中介基板170為剛性基板。如此一來，一些實施例的中介基板170(包含導電墊173b)實質上不受成型層210與晶片140之間的熱膨脹不匹配造成的應力影響。如此一來，一些實施例可改善導電墊173b與導電凸塊240之間的接合良率。
第3A至3B圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。如第3A圖所示的一些實施例，在進行第1D圖的步驟之後，形成黏著層A於晶片140的基板142其表面142b上。在一些實施例中，黏著層A可為膜、膠層、或膏層。
在一些實施例中，黏著層A的組成為聚合物材料或高導熱材料。在一些實施例中，高導熱材料的導熱性(k)大於約 1Wm-1K-1。在一些實施例中，高導熱材料包含氧化鋁及/或石墨烯。在一些實施例中，黏著層A的形成方法採用塗佈製程、壓合製程、或沉積製程。
如第3B圖所示的一些實施例，進行第1E至1J圖的步驟。如第3B圖所示的一些實施例，形成晶片封裝體C3。在一些實施例中，晶片封裝體C3與第1J圖的晶片封裝體C1類似，差別在於晶片封裝體C3更具有黏著層A。在一些實施例中，黏著層A直接接觸中介基板170(或基板172)與晶片140。
在一些實施例中，黏著層A用於使中介基板170接合至晶片140。在一些實施例中，自晶片140產生並傳導至中介基板170的熱，可藉由黏著層A散熱。
第4圖係一些實施例中，晶片封裝體C4的剖視圖。如第4圖所示的一些實施例，晶片封裝體C4與第1J圖的晶片封裝體C1類似，差別在於晶片封裝體C4的凹陷R未穿過絕緣層176。如此一來，一些實施例的凹陷R並未延伸至基板172中。
在一些實施例中，中介基板170具有線路層410與420以及導電墊430與440。在一些實施例中，線路層410位於絕緣層176中，並連接至導電墊430。在一些實施例中，絕緣層176覆蓋導電墊430的部份。在一些實施例中，線路層410、導電墊430、與絕緣層176一起組成線路結構WR1。
在一些實施例中，凹陷R未穿過線路結構WR1。在一些實施例中，導電結構180連接至導電墊430。在一些實施例中，線路層420位於絕緣層178中，並連接至導電墊440。在一些實施例中，絕緣層178覆蓋導電墊440的部份。在一些實施例 中，線路層420、導電墊440、與絕緣層178一起組成線路結構WR2。
在一些實施例中，導電凸塊240連接至導電墊440。在一些實施例中，導電墊440與線路層420經由導電通孔結構174電性連接至導電墊430與線路層410。第1E至1J圖與第3B圖的中介基板170可包含線路結構WR1與WR2，端視需求而定。
第5圖係一些實施例中，晶片封裝體C5的剖視圖。如第5圖所示的一些實施例，晶片封裝體C5與第4圖的晶片封裝體C4類似，差別在於晶片封裝體C5的凹陷R穿過線路結構WR1與基板172。在一些實施例中，線路結構WR2更具有導電層510於絕緣層178中。在一些實施例中，凹陷R露出導電層510。
在一些實施例中，導電層510位於晶片140上。在一些實施例中，導電層510的尺寸(如寬度W1或面積)大於晶片140的尺寸(如寬度W2或面積)。在一些實施例中，導電層510的厚度T3介於約5微米至約50微米之間。在一些實施例中，線路層420的厚度T4介於約5微米至約40微米之間。
在一些實施例中，晶片140產生的熱可經由導電層510散熱。在一些實施例中，成型層210直接接觸導電層510與晶片140。在一些實施例中，導電層510、導電通孔結構174、線路層420、與導電墊440的組成為相同材料。在一些實施例中，導電層510的組成為導電材料，比如金屬(如銅、鋁、或鎢)。
第6圖係一些實施例中，晶片封裝體C6的剖視圖。如第6圖所示的一些實施例，晶片封裝體C6與第4圖的晶片封裝 體C4類似，差別在於晶片封裝體C6的凹陷R未延伸至基板172中。在一些實施例中，凹陷R僅位於線路結構WR1中。
第7A至7B圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。如第7A圖所示的一些實施例，在進行第1E圖的步驟之後，形成底填層710於中介基板170與其下方的再佈線結構120之間，以及中介基板170與其下方的晶片140之間。在一些實施例中，底填層710的組成為絕緣材料如聚合物材料或成型化合物材料(由環氧化合物、填充物、樹脂、或上述之組合所組成)。在一些實施例中，未形成底填層160，且底填層710填入晶片140與再佈線結構120之間的間隙。
如第7B圖所示的一些實施例，進行第1G至1J圖的步驟。如第7B圖所示的一些實施例，實質上形成晶片封裝體C7。為簡化圖式，第7B圖所示的一些實施例僅顯示一個晶片封裝體C7。在一些實施例中，底填層710圍繞晶片140、底填層160、壩結構130、導電結構180、與中介基板170的下側部份。
在一些實施例中，底填層710直接接觸晶片140、底填層160、壩結構130、導電結構180、中介基板170、與再佈線結構120。在一些實施例中，底填層710覆蓋中介基板170之側壁170s的部份。
在一些實施例中，中介基板170的寬度W170小於再佈線結構120的寬度W120。在一些實施例中，底填層710具有傾斜側壁712。在一些實施例中，傾斜側壁712圍繞中介基板170。
第8A圖係一些實施例中，晶片封裝體C8的剖視 圖。第8B圖係一些實施例中，第8A圖的晶片封裝體C8其中介基板170的上視圖。如第8A與8B圖所示的一些實施例，晶片封裝體C8與第7B圖的晶片封裝體C7類似，差別在於中介基板170的絕緣層178露出中介基板170的基板172其表面172b的一部份。
在一些實施例中，中介基板170具有中心區170c與圍繞中心區170c的周邊區170r。在一些實施例中，表面172b的露出部份位於周邊區170r中。在一些實施例中，表面172b的露出部份連續地圍繞所有的絕緣層178。
在一些實施例中，中介基板170具有邊緣凹陷R1。在一些實施例中，絕緣層178的側壁178b與表面172b的露出部份圍繞邊緣凹陷R1。在一些實施例中，邊緣凹陷R1具有寬度W3，其介於約20微米至約150微米之間。
在將晶片封裝體300接合至中介基板170之前，若底填層710沿著中介基板170的側壁170s延伸於基板172的表面172b上，則邊緣凹陷R1可容納表面172b上的底填層710，以避免底填層710延伸至導電墊173b上而阻礙導電墊173b與導電凸塊240之間的接合。
在一些實施例中，晶片封裝體300與中介基板170之間的底填層360填入邊緣凹陷R1。在一些實施例中，底填層360的部份362延伸至中介基板170中。在一些實施例中，部份362為環形。在一些實施例中，部份362連續地圍繞整個絕緣層178。在一些實施例中，未形成底填層360。
第9A圖係一些實施例中，晶片封裝體C9的剖視 圖。第9B圖係一些實施例中，第9A圖的晶片封裝體C9其中介基板170的上視圖。如第9A與9B圖所示的一些實施例，晶片封裝體C9與第7B圖的晶片封裝體C7類似，差別在於中介基板170的絕緣層178具有溝槽178c。
在一些實施例中，溝槽178c露出周邊區170r中的基板172其表面172b。在一些實施例中，溝槽178c圍繞所有的導電墊173b。在一些實施例中，溝槽178c的寬度W4介於約20微米至約150微米之間。
溝槽178c用於容納延伸至表面172b上的底填層710，以避免底填層710更延伸至導電墊173b上而阻礙導電墊173b與導電凸塊240之間的接合。
在一些實施例中，晶片封裝體300與中介基板170之間的底填層360填入溝槽178c。在一些實施例中，底填層360的部份364延伸至中介基板170中。在一些實施例中，部份364為環形。在一些實施例中，部份364連續地圍繞所有的導電墊173b。
第10A圖係一些實施例中，晶片封裝體C10的剖視圖。第10B圖係一些實施例中，第10A圖的晶片封裝體C10其中介基板170的上視圖。如第10A與10B圖所示的一些實施例，晶片封裝體C10與第7B圖的晶片封裝體C7類似，差別在於中介基板170的絕緣層178具有凸起部份178d。在一些實施例中，凸起部份178d自絕緣層178的表面178e凸起。
在一些實施例中，凸起部份178d連續地圍繞所有的導電墊173b。在一些實施例中，凸起部份178d為環形。在一 些實施例中，凸起部份178d延伸至晶片封裝體300與中介基板170之間的底填層360中。
在一些實施例中，凸起部份178d的寬度W5介於約20微米至約150微米之間。在一些實施例中，凸起部份178d的厚度T介於約10微米至約80微米之間。在一些實施例中，凸起部份178d用於避免底填層710延伸至導電墊173b上而阻礙導電墊173b與導電凸塊240之間的接合。
第11圖係一些實施例中，晶片封裝體C11的剖視圖。如第11圖所示的一些實施例，晶片封裝體C11與第7B圖的晶片封裝體C7類似，差別在於中介基板170的寬度W6實質上等於或大於再佈線結構120的寬度W7。
在一些實施例中，底填層710形成於中介基板170與再佈線結構120之間。在一些實施例中，底填層710並未延伸至中介基板170的側壁170s上。在一些實施例中，底填層710具有傾斜側壁712。在一些實施例中，傾斜側壁712位於中介基板170與再佈線結構120之間。
第12圖係一些實施例中，晶片封裝體C12的剖視圖。如第12圖所示的一些實施例，晶片封裝體C12與第1J圖的晶片封裝體C1類似，差別在於晶片封裝體C12的中介基板170更具有導電通孔結構1210。
在一些實施例中，導電通孔結構1210穿過絕緣層176。在一些實施例中，導電通孔結構1210連接至其上方的導電墊173a與其下方的導電結構180。在一些實施例中，導電通孔結構1210直接接觸其下方的導電結構180。
在一些實施例中，基板172與絕緣層178的總厚度T5介於約20微米至約100微米之間。在一些實施例中，絕緣層176的厚度T6介於約30微米至約200微米之間。在一些實施例中，中介基板170的總厚度T7介於約50微米至約300微米之間。在一些實施例中，凹陷R的深度D1介於約30微米至約200微米之間。
在一些實施例中，絕緣層176與178的組成為不同材料。在一些實施例中，絕緣層176的組成為聚合物材料。在一些實施例中，絕緣層176包含Ajinomoto增層膜。在一些實施例中，絕緣層178的組成為聚合物材料，比如阻焊材料(如聚醯亞胺)。在一些實施例中，基板172的組成為絕緣材料如聚合物材料。
第13圖係一些實施例中，晶片封裝體C13的剖視圖。如第13圖所示的一些實施例，晶片封裝體C13與第1J圖的晶片封裝體C1類似，差別在於晶片封裝體C13更包含基板1310、導電通孔結構1320、與焊料層1330。在一些實施例中，凹陷R穿過基板1310。基板1310的組成可為聚合物材料、纖維材料、半導體材料、玻璃材料、金屬材料、或另一合適材料。
在一些實施例中，導電通孔結構1320穿過基板1310。在一些實施例中，導電通孔結構1320連接至其下方的導電結構180。在一些實施例中，基板1310與導電通孔結構1320圍繞晶片140。在一些實施例中，導電通孔結構1320的組成為導電材料如銅、鋁、或鎢。
在一些實施例中，焊料層1330位於導電通孔結構 1320與導電墊173a之間，並電性連接至導電通孔結構1320與導電墊173a。在一些實施例中，焊料層1330的組成為焊料材料如錫與銀，或另一合適的導電材料。
第14A至14D圖係一些實施例中，形成晶片封裝體的製程其多種階段的剖視圖。如第14A圖所示的一些實施例，在進行第1E圖所示的步驟後，形成溝槽1410於再佈線結構120中。在一些實施例中，溝槽1410穿過中介基板170之間以及不同中介基板170下的導電結構180之間的再佈線結構120。
在一些實施例中，溝槽1410將再佈線結構120分為多個部份129。在一些實施例中，部份129彼此分隔。在一些實施例中，每一部份129位於中介基板170之一者下。在一些實施例中，溝槽1410的形成方法採用切割製程。
如第14A圖所示的一些實施例，離型膜190形成於中介基板170上以覆蓋導電層179與導電通孔結構174。如第14A圖所示的一些實施例，之後形成成型層210於離型膜190、中介基板170、部份129、與晶片140之間。在一些實施例中，成型層210圍繞中介基板170、晶片140、導電凸塊150、底填層160、壩結構130、與部份129。
如第14B圖所示的一些實施例，移除離型膜190。如第14B圖所示的一些實施例，溝槽212形成於成型層210中。在一些實施例中，溝槽212穿過中介基板170之間，以及不同中介基板170下的導電結構180之間的成型層210。
在一些實施例中，溝槽212將成型層210分成多個部份214。在一些實施例中，部份214彼此分隔。在一些實施例 中，每一部份214圍繞中介基板170之一者，以及中介基板170之一者下方的晶片140與部份129。在一些實施例中，溝槽212的形成方法採用切割製程。
如第14C圖所示的一些實施例，移除載板110。如第14C圖所示的一些實施例，上下翻轉中介基板170。如第14C圖所示的一些實施例，中介基板170位於載板220上。如第14C圖所示的一些實施例，移除部份129的絕緣層121。
在一些實施例中，在移除絕緣層121時，亦移除與絕緣層121相鄰的成型層210其部份214。在一些其他實施例中(未圖示)，在移除絕緣層121之後，仍保留與絕緣層121相鄰的成型層210其部份214。如第14C圖所示的一些實施例，導電凸塊230分別形成於導電墊122上。在一些實施例中，此步驟實質上形成晶片封裝體100。
如第14D圖所示的一些實施例，移除載板220。如第14D圖所示的一些實施例，進行第1J圖所示的步驟以形成晶片封裝體C14。為簡化圖式，第14D圖所示的一些實施例僅顯示一個晶片封裝體C14。在一些實施例中，晶片封裝體C14中的成型層210圍繞再佈線結構120。
第15圖係一些施例中，晶片封裝體C15的剖視圖。如第15圖所示的一些實施例，晶片封裝體C15與第1J圖的晶片封裝體C1類似，差別在於晶片封裝體C15的壩結構130其頂部延伸至中介基板170的凹陷R中。
第7A至14D圖所示的中介基板170可具有第4、5、或6圖的線路結構WR1與WR2。第7A至14D圖的中介基板170可 取代為第2圖與第4至6圖的中介基板170。
在一些實施例中，提供晶片封裝體與其形成方法。形成晶片封裝體的方法將中介基板接合至再佈線結構，晶片位於中介基板與再佈線結構之間，且晶片部份地位於中介基板中。中介基板可減少晶片封裝體的捲曲，且晶片封裝體包含中介基板、再佈線結構、與晶片。如此一來，可改善晶片封裝體與封裝結構之間的接合良率。中介基板可增加晶片封裝體的剛性與機械強度。中介基板的線路層與導電墊，實質上不受晶片封裝體的晶片與成型層之間的熱膨脹不匹配所產生的應力影響。由於晶片部份地位於中介基板中，可減少晶片封裝體的總厚度。
在一些實施例中，提供形成晶片封裝體的方法。方法包括將晶片置於再佈線結構上。再佈線結構包括第一絕緣層與第一線路層，且第一線路層位於第一絕緣層中並電性連接至晶片。方法亦包括經由導電結構將中介基板接合至再佈線結構。晶片位於中介基板與再佈線結構之間。中介基板具有與再佈線結構相鄰的凹陷。晶片的第一部份位於凹陷中。中介基板包括基板與導電通孔結構，且導電通孔結構穿過基板並經由導電結構電性連接至第一線路層。
在一些實施例中，上述方法更包括在將中介基板接合至再佈線結構之後，形成底填層於中介基板與再佈線結構之間，以及中介基板與晶片之間。
在一些實施例中，上述方法更包括在將中介基板接合至再佈線結構之前，形成壩結構於再佈線結構上，其中壩 結構具有開口，且晶片位於開口之上或之中。
在一些實施例中，上述方法更包括在將中介基板接合至再佈線結構之後，將封裝結構接合至中介基板。
在一些實施例中，上述方法的中介基板更包括第一線路結構，基板具有面對再佈線結構的第一表面，第一線路結構位於第一表面上，第一線路結構包括第二絕緣層與第二絕緣層中的第二線路層，且凹陷位於第一線路結構中。
在一些實施例中，上述方法的凹陷穿過第一線路結構。
在一些實施例中，上述方法的凹陷延伸至基板中。
在一些實施例中，上述方法的基板具有遠離再佈線結構的第二表面，中介基板更包括第二線路結構於第二表面與凹陷上，第二線路結構包括第三絕緣層與第三絕緣層中的導電層，且凹陷更穿過基板並露出導電層。
在一些實施例中，上述方法的基板組成為纖維材料、聚合物材料、半導體材料、玻璃材料、或金屬材料。
在一些實施例中，提供形成晶片封裝體的方法。方法包括將晶片置於再佈線結構上。再佈線結構包括絕緣層與第一線路層，且第一線路層位於絕緣層中並電性連接至晶片。上述方法包括經由第一導電凸塊將中介基板接合至再佈線結構。晶片位於中介基板與再佈線結構之間。中介基板具有與再佈線結構相鄰的凹陷，且晶片的一部份位於凹陷中。上述方法包括形成成型層，其圍繞中介基板與第一導電凸塊。成型層部份地位於中介基板與再佈線結構之間，且部份地位於中介基板 與晶片之間。
在一些實施例中，上述方法更包括在將晶片置於再佈線結構上之前，形成再佈線結構於載板上；以及在形成成型層之後，移除載板。
在一些實施例中，上述方法更包括在將晶片置於再佈線結構上之前，形成壩結構於再佈線結構上，其中壩結構具有開口。將晶片置於再佈線結構上的步驟包括經由第二導電凸塊接合晶片至再佈線結構，且第二導電凸塊在開口中。
在一些實施例中，上述方法的壩結構其頂部位於凹陷中。
在一些實施例中，上述方法的中介基板包括基板、導電通孔結構、與第二線路層，第二導電通孔結構穿過基板並經由第一導電凸塊電性連接至第一線路層，第二線路層位於基板之中或之上，且第二線路層與成型層及晶片之間隔有基板。
在一些實施例中，上述方法更包括在將中介基板接合至再佈線結構之前，形成黏著層於晶片的上表面上，其中黏著層位於晶片與中介基板之間。
在一些實施例中，提供晶片封裝體。晶片封裝體包括再佈線結構，其包括絕緣層與線路層。線路層位於絕緣層中。晶片封裝體包括晶片於再佈線結構上，且晶片電性連接至線路層。晶片封裝體包括中介基板於再佈線結構與晶片上。晶片的一部份位於中介基板中。晶片封裝體包括中介基板與再佈線結構之間的導電結構，且導電結構電性連接至線路層。
在一些實施例中，上述晶片封裝體更包括封裝結構於中介基板上，其中封裝結構經由中介基板電性連接至再佈線結構的線路層。
在一些實施例中，上述晶片封裝體更包括底填層於晶片封裝體與中介基板之間，其中底填層的一部份為環形且延伸至中介基板中。
在一些實施例中，上述晶片封裝體更包括底填層於晶片封裝體與中介基板之間，其中中介基板的一部份為環形且延伸至底填層中。
在一些實施例中，上述晶片封裝體更包括成型層於中介基板與再佈線結構之間以及中介基板與晶片之間，且成型層圍繞中介基板與導電結構。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之申請專利範圍的精神與範疇的前提下進行改變、替換、或更動。
C1、100、300:晶片封裝體
T2:厚度
124、126、318:線路層
130:壩結構
140、320:晶片
160、340、360:底填層
170:中介基板
172、322:基板
173b、314、316、324:導電墊
180:導電結構
210、350:成型層
230、240、330:導電凸塊
310:再佈線結構
312:絕緣層
322a:表面

Claims (10)

  1. 一種形成晶片封裝體的方法，包括：將一晶片置於一再佈線結構上，其中該再佈線結構包括一第一絕緣層與一第一線路層，且該第一線路層位於該第一絕緣層中並電性連接至該晶片；以及在將該晶片置於該再佈線結構上之後，經由一導電結構將一中介基板接合至該再佈線結構，其中該晶片位於該中介基板與該再佈線結構之間，該中介基板具有與該再佈線結構相鄰的一凹陷，該晶片的第一部份位於該凹陷中，該中介基板包括一基板與一導電通孔結構，且該導電通孔結構穿過該基板並經由該導電結構電性連接至該第一線路層，該導電結構包括一導電凸塊或一導電柱，該中介基板更包括一第一線路結構，該基板具有面對該再佈線結構的一第一表面，該第一線路結構位於該第一表面上，該第一線路結構包括一第二絕緣層與該第二絕緣層中的一第二線路層，且該凹陷位於該第一線路結構中。
  2. 如請求項1之形成晶片封裝體的方法，更包括在將該中介基板接合至再佈線結構之後，形成一底填層於該中介基板與該再佈線結構之間，以及該中介基板與該晶片之間。
  3. 一種形成晶片封裝體的方法，包括：將一晶片置於一再佈線結構上，其中該再佈線結構包括一絕緣層與一第一線路層，且該第一線路層位於該絕緣層中並電性連接至該晶片； 經由一第一導電凸塊將一中介基板接合至該再佈線結構，其中該晶片位於該中介基板與該再佈線結構之間，該中介基板具有與該再佈線結構相鄰的一凹陷，且該晶片的一部份位於該凹陷中；以及形成一成型層，其圍繞該中介基板與該第一導電凸塊，其中該成型層部份地位於該中介基板與該再佈線結構之間，且部份地位於該中介基板與該晶片之間。
  4. 如請求項3之形成晶片封裝體的方法，更包括：在將該晶片置於該再佈線結構上之前，形成該再佈線結構於一載板上；以及在形成該成型層之後，移除該載板。
  5. 一種形成晶片封裝體的方法，包括：形成一壩結構於一再佈線結構上；經由一第一導電凸塊將一晶片接合至該再佈線結構，其中該壩結構連續圍繞該晶片與該第一導電凸塊；以及在經由該第一導電凸塊接合該晶片至該再佈線結構之後，經由一導電結構接合一中介基板至該再佈線結構，其中該晶片位於該中介基板與該再佈線結構之間，該晶片的一部份位於該中介基板中，該壩結構位於該第一導電凸塊與該導電結構之間以及該中間基板與該再佈線結構之間，且該導電結構包括一第二導電凸塊或一導電柱，在將該中介基板接合至該再佈線結構之後，形成一成型層以圍繞該中介基板、該導電結構、該晶片、與該第一導電凸塊，其中該成型層部份地位於該中介基板與該再佈線結 構之間，並部份地位於該中介基板與該晶片之間。
  6. 如請求項5之形成晶片封裝體的方法，其中該成型層部份地位於該中介基板與該壩結構之間。
  7. 一種晶片封裝體，包括：一再佈線結構，包括一絕緣層與一線路層。其中該線路層位於該絕緣層中；一晶片，位於該再佈線結構上且電性連接至該線路層；一中介基板，位於該再佈線結構與該晶片上，其中該晶片的一部份位於該中介基板中；一導電結構，位於該中介基板與該再佈線結構之間，並電性連接至該線路層，其中該導電結構包括一導電凸塊或一導電柱；一成型層，圍繞該中介基板與該導電結構，其中該成型層部份地位於該中介基板與該再佈線結構之間以及該中介基板與該晶片之間；以及一壩結構，位於該再佈線結構上並圍繞該晶片，其中該成型層位於該壩結構與該導電結構之間。
  8. 如請求項7之晶片封裝體，其中該成型層部份地位於該壩結構與該中介基板之間。
  9. 一種晶片封裝體，包括：一再佈線結構，包括一第一絕緣層與一第一線路層，其中該第一線路層位於該第一絕緣層中；一晶片，位於該再佈線結構上並電性連接至該第一線路層；一中介基板，位於該再佈線結構與該晶片上，其中該中介 基板包括一基板與一線路結構，該線路結構位於該基板與該再佈線結構之間，該線路結構包括一第二絕緣層與該第二絕緣層中的一第二線路層，該晶片的一部份位於該線路結構中，且該晶片與中介基板分開；以及一導電結構，位於該中介基板與該再佈線結構之間，並電性連接至該第一線路層，其中該導電結構包括一導電凸塊或一導電柱。
  10. 一種晶片封裝體，包括：一再佈線結構，包括一絕緣層與一線路層，其中該線路層位於該絕緣層中；一晶片，位於該再佈線結構上並電性連接至該線路層；一中介基板，位於該再佈線結構與該晶片上，其中該晶片的一部份位於該中介基板中，且該再佈線結構比該中介基板寬；一導電結構，位於該中介基板與該再佈線結構之間，並電性連接至該線路層，其中該導電結構包括一導電凸塊或一導電柱；以及一底填層，位於該中介基板與該再佈線結構之間，並圍繞該中介基板，該導電結構、與該晶片，其中該底填層覆蓋該中介基板的側壁之下側部份，並露出該中介基板的側壁之上側部份。
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