CN110739229A - 芯片封装体结构的制造方法 - Google Patents

芯片封装体结构的制造方法 Download PDF

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Publication number
CN110739229A
CN110739229A CN201910603971.8A CN201910603971A CN110739229A CN 110739229 A CN110739229 A CN 110739229A CN 201910603971 A CN201910603971 A CN 201910603971A CN 110739229 A CN110739229 A CN 110739229A
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layer
conductive
redistribution structure
chip
chip package
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CN201910603971.8A
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郑心圃
陈硕懋
许峯诚
林柏尧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种芯片封装体结构的制造方法，包括形成一第一重分布结构于一第一承载基底上。通过一第一导电凸块将一芯片结构接合至第一表面。形成一第一模塑层于第一重分布结构上。去除第一承载基底。形成一第二导电凸块于第二表面上。形成一第二重分布结构于一第二承载基底上。将第一重分布结构接合至第三表面。形成一第二模塑层于第二重分布结构上。去除第二承载基底。从第四表面去除第二重分布结构的一部分。形成一第三导电凸块于第四表面上。

Description

芯片封装体结构的制造方法
技术领域
本公开实施例涉及一种半导体技术，且特别涉及一种芯片封装体结构及其制造方法。
背景技术
半导体装置使用于各种电子应用，例如个人电脑，手机、数字数码相机以及其他电子设备。通常通过在半导体基底上按序沉积绝缘层或介电层、导电层以及半导体层，并使用光刻工艺及蚀刻工艺图案化各种材料层，以在其上形成电路部件及元件来制造半导体装置。
通常许多集成电路制造于半导体芯片上。半导体晶圆可单体分割成芯片。芯片可进行封装，并且已开发了各种用于封装的技术。
发明内容
一种芯片封装体结构的制造方法包括：形成一第一重分布结构于一第一承载基底上，其中第一重分布结构具有一第一表面及一第二表面；通过一第一导电凸块将一芯片结构接合至第一表面；形成一第一模塑层于第一重分布结构上，且围绕芯片结构；去除第一承载基底；形成一第二导电凸块于第二表面上；形成一第二重分布结构于一第二承载基底上，其中第二重分布结构具有一第三表面及相对于第三表面且面向第二承载基底的一第四表面；通过第二导电凸块将第一重分布结构接合至第三表面；形成一第二模塑层于第二重分布结构上，且围绕第一模塑层、第一重分布结构以及芯片结构；去除第二承载基底；从第四表面去除第二重分布结构的一部分；以及形成一第三导电凸块于第四表面上。
一种芯片封装体结构的制造方法包括：通过一第一导电凸块将一芯片结构接合至一中介基板，其中中介基板包括一核心层及穿过核心层并电性连接至芯片结构的一导电通孔结构；形成一第一模塑层于中介基板上并围绕芯片结构；形成一第二导电凸块于中介层基板上，其中中介基板位于第二导电凸块与芯片结构之间；形成一重分布结构于承载基底上，其中重分布结构具有一第一表面及一第二表面；通过第二导电凸块将中介基板接合至第一表面；形成一第二模塑层于重分布结构上并围绕第一模塑层、中介基板以及芯片结构；去除承载基底；从第二表面去除重分布结构的一部分；以及形成一第三导电凸块于第二表面上。
一种芯片封装体结构包括：一第一重分布结构，具有一第一表面及一第二表面，其中第一重分布结构包括一第一接垫及一第二接垫，第一接垫与第一表面相邻，且第二接垫与第二表面相邻；一芯片封装体，通过一第一凸块接合至第一接垫，其中第一接垫的第一宽度沿远离芯片封装体的一第一方向上减小，而第二接垫的一第二宽度沿第一方向上减小；以及一第二导电凸块位于第二接垫上。
附图说明
图1A至图1G是示出根据一些实施例的不同制造阶段的芯片封装体结构制造方法剖面示意图。
图2是示出根据一些实施例的芯片封装体结构剖面示意图。
图3是示出根据一些实施例的芯片封装体结构剖面示意图。
图4A至图4F是示出根据一些实施例的不同制造阶段的芯片封装体结构制造方法剖面示意图。
图5是示出根据一些实施例的芯片封装体结构剖面示意图。
图6是示出根据一些实施例的芯片封装体结构剖面示意图。
附图标记说明：
100 芯片封装体
200、300、300A、300B、400、500、600、600A、600B 芯片封装体结构
110、210、250 承载基底
120、220 重分布结构
121、123、125、127、221、223、225、227、D 介电层
121a、123a、125a、127a、221a、223a、225a、227a 通孔
122、128、222、228、263a、263b、269c、269d、419c、419d、P 导电接垫
122a、222a 侧壁
124、126、224、226、269a、269b、419a、419b 接线层
140 芯片结构
142 芯片
142a、260 基底
142b、144b 装置层
142c 内连接层
144 芯片封装体
144a 重分布结构/基底
144c、150、180、240、310 导电凸块
144d、170、230、290 模塑层
164 底胶层
172、232、292、A1、A2、S3、S4、S5 上表面
262、412 核心层
262a、262b、412a、412b、S1、S2、S6、S7、S8、S9 表面
262c、266a、268a、416a、418a 开口
264、414 导电通孔结构
265、266、268、415、416、418 绝缘层
270、320 环形结构
280、330 粘着层
341、342、343、345、346、347 被动装置
350 填充层
410 中介基底
B1 底表面
T1、T2、T3、T4 厚度
V1、V2 方向
W1、W2、W3、W4 宽度
W1’、W2’、W3’、W4’ 最大宽度
具体实施方式
以下的公开内容提供许多不同的实施例或范例，以实施本公开的不同特征部件。而以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化本公开内容。当然，这些仅为范例说明并非用以限定本公开。举例来说，若是以下的公开内容叙述了将一第一特征部件形成于一第二特征部件之上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外，本公开内容在各个不同范例中会重复标号及/或文字。重复是为了达到简化及明确目的，而非自行指定所探讨的各个不同实施例及/或配置之间的关系。
再者，在空间上的相关用语，例如＂下方＂、＂之下＂、＂下＂、＂上方＂、＂上＂等等在此处是用以容易表达出本说明书中所示出的附图中元件或特征部件与另外的元件或特征部件的关系。这些空间上的相关用语除了涵盖附图所示出的方位外，还涵盖装置于使用或操作中的不同方位。此装置可具有不同方位(旋转90度或其他方位)且此处所使用的空间上的相关符号同样有相应的解释。
也可包括其他特征部件及工艺。举例来说，可包括测试结构，以帮助3D封装或3DIC设备的验证测试。测试结构可包括，例如，形成于重分布层中或于基底上的测试接垫(其允许测试3D封装或3DIC)、探针及/或探针卡的使用等等。验证测试可在中间结构以及最终结构上进行。另外，本文公开的结构及方法可与测试方法(包括已知良好芯片的中间验证)结合使用，以增加良率并降低成本。
图1A至图1G是示出根据一些实施例的不同制造阶段的芯片封装体结构制造方法剖面示意图。如图1A所示，根据一些实施例，提供一承载基底110。根据一些实施例，承载基底110作为在后续工艺步骤期间提供暂时性的机械及结构性支撑。根据一些实施例，承载基底110包括玻璃、硅、氧化硅、氧化铝、金属、其组合及/或相似物。根据一些实施例，承载基底110包括一金属框架。
如图1A所示，根据一些实施例，形成一粘着层A1于承载基底110上。根据一些实施例，粘着层A1与承载基底110直接接触。根据一些实施例，粘着层A1顺应性地形成于承载基底110上。根据一些实施例，粘着层A1由绝缘材料制成，例如高分子材料。粘着层A1为使用涂覆工艺或其他合适的工艺形成。
如图1A所示，根据一些实施例，形成一重分布结构120于粘着层A1上。根据一些实施例，重分布结构120具有一表面S1及一表面S2。根据一些实施例，表面S1与表面S2相对。根据一些实施例，表面S2面向承载基底110。
重分布结构120的制作包括形成一介电层121于粘着层A1上；形成多个导电接垫122于介电层121上以及介电层121的多个通孔121a内；形成一介电层123于介电层121及导电接垫122上；形成一接线层124于介电层123上及介电层123的多个通孔123a内；形成一介电层125于介电层123及接线层124上；形成一接线层126于介电层125上及介电层125的多个通孔125a内；形成一介电层127于介电层125及接线层126上；形成多个导电接垫128于介电层127上及介电层127的多个通孔127a中。
根据一些实施例，介电层121与粘着层A1直接接触。根据一些实施例，介电层121顺应性地形成于粘着层A1上。在一些实施例中，介电层121内的导电接垫122的一宽度W1沿着从表面S1至表面S2的方向V1减小。
在一些实施例中，介电层127内的导电接垫128的宽度W2沿着方向V1减小。根据一些实施例，导电接垫122比导电接垫128宽。举例来说，根据一些实施例，导电接垫122的最大宽度W1’大于导电接垫128的最大宽度W2’。接线层124及接线层126彼此电连接。根据一些实施例，导电接垫122及导电接垫128电性连接至接线层124及接线层126。
根据一些实施例，介电层121、介电层123、介电层125以及介电层127由绝缘材料制成，例如高分子材料(例如，聚苯并恶唑，聚酰亚胺或光敏材料)、氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、氧氮化硅等。根据一些实施例，使用沉积工艺(例如，化学气相沉积工艺或物理气相沉积工艺)、光刻工艺及蚀刻工艺来形成介电层121、介电层123、介电层125以及介电层127中的每一个。根据一些实施例，接线层124及接线层126以及导电接垫122及导电接垫128由导电材料制成，例如金属(例如铜、铝或钨)。
如图1A所示，根据一些实施例，多个芯片结构140通过多个导电凸块150接合至重分布结构120。根据一些实施例，芯片结构140包括多个芯片142及/或多个芯片封装体144。为简化起见，图1A及图1B及图1D至图1G仅示出多个芯片142其中一者以及多个芯片封装体144其中一者。
芯片142包括片上系统级芯片(system-on-chip,SoC)、存储器芯片(例如，动态随机存取存储器芯片)或其他合适的芯片。芯片142和芯片封装体144可具有相同或不同的宽度。芯片142和芯片封装体144可具有相同或不同的高度。根据一些实施例，芯片142具有一基底142a、一装置层142b以及一内连接层142c。
在一些实施例中，基底142a由包括单晶、多晶或非晶结构的硅或锗的元素半导体材料制成。在一些其他实施例中，基底142a由化合物半导体制成(例如，碳化硅、砷化镓、磷化镓、磷化铟、砷化铟)、合金半导体(例如，SiGe、或GaAsP)、或其组合。
基底142a也可包括多层半导体，绝缘体上覆半导体(semiconductor oninsulator,SOI)(诸如，绝缘体上覆硅或绝缘体上覆锗)、或其组合。根据一些实施例，基底142a具有面向重分布结构120的一底表面B1。根据一些实施例，装置层142b位于底表面B1上方。根据一些实施例，装置层142b包括多个电子元件(未示出)、一介电层D及多个导电接垫P。
在一些实施例中，电子元件形成于基底142a上或基底142a内。根据一些实施例，电子元件包括主动元件(例如，晶体管，二极管等)及/或无源元件(例如，电阻器、电容器、电感器等)。根据一些实施例，介电层D形成于底表面B1上并覆盖电子元件。
根据一些实施例，导电接垫P埋入在介电层D内并且电性连接至电子元件。根据一些实施例，导电接垫P由导电材料制成，例如金属(例如，铜、铝、镍或其组合)。
根据一些实施例，内连接层142c形成于装置层142b上方。根据一些实施例，内连接层142c包括内连接结构(未示出)和介电层(未示出)。根据一些实施例，内连接结构在介电层内并且电性连接至导电接垫P。
在一些实施例中，根据一些实施例，每个芯片封装体144包括一重分布结构(或基底)144a、一芯片144b、多个导电凸块144c以及一模塑层144d。根据一些实施例，重分布结构144a包括一介电层(未示出)及多个接线层(未示出)。根据一些实施例，接线层位于介电层内。
根据一些实施例，芯片144b通过导电凸块144c接合至重分布结构144a。芯片144b包括动态随机存取存储器(dynamic random access memory,DRAM)芯片，高带宽存储存储器(high bandwidth memory,HBM)芯片或其他合适的芯片。根据一些实施例，导电凸块144c将芯片144b电性连接至重分布结构144a的接线层。
根据一些实施例，导电凸块144c由焊料材料制成，例如Sn及Ag或其他合适的导电材料(例如，金)。根据一些实施例，模塑层144d形成在重分布结构144a上方以围绕芯片144b和导电凸块144c。模塑层144d由高分子材料或其他合适的绝缘材料制成。
根据一些实施例，一些导电凸块150位于导电接垫128与内连接层142c之间，以通过内连接层142c的内连接结构将导电接垫128电性连接到导电接垫P。根据一些实施例，一些其他导电凸块150位于导电接垫128与重分布结构144a之间，以通过重分布结构144a及导电凸块144c的接线层将导电接垫128电性连接到芯片144b。
根据一些实施例，导电凸块150由焊料材料制成，例如Sn和Ag或其他合适的导电材料(例如，金)。根据一些实施例，导电凸块150是焊球。
如图1A所示，根据一些实施例，一底胶层162形成于芯片142与重分布结构120之间。根据一些实施例，底胶层162围绕芯片142下方的导电凸块150及导电接垫128。根据一些实施例，底胶层162由绝缘材料制成，例如高分子材料或由环氧树脂和填充材料组成的模塑成型材料(molding compound)。
如图1A所示，根据一些实施例，形成一底胶层164于芯片封装体144与重分布结构120之间。根据一些实施例，底胶层164围绕芯片封装体144下方的导电凸块150及导电接垫128。根据一些实施例，底胶层164由绝缘材料制成，例如高分子材料或由环氧树脂和填充材料组成的模塑材料。
在一些实施例中，形成一模塑材料层(未示出)于芯片结构140、底胶层162及164以及重分布结构120上方。根据在一些实施例，模塑材料层填充芯片结构140之间的间隙。根据一些实施例，间隙中的模塑材料层围绕芯片结构140。模塑材料层由高分子材料或其他合适的绝缘材料制成。在一些实施例中，对模塑材料层进行热工艺，以固化模塑材料层。
如图1A所示，根据一些实施例，去除模塑材料层的上部以形成一模塑层170。根据一些实施例，在进行去除工艺之后，模塑层170的上表面172实质上与基底142a的上表面S3、芯片144b的上表面S4及模塑层144d的上表面S5共平面或对齐。根据一些实施例，去除工艺包括化学机械研磨工艺。
如图1B所示，根据一些实施例，去除承载基底110及粘着层A1。如图1B所示，根据一些实施例，去除介电层121以露出导电接垫122的侧壁122a。如图1B所示，根据一些实施例，导电凸块180分别形成在导电接垫122上。根据一些实施例，导电凸块180由焊料材料制成，例如Sn和Ag或其他合适的导电材料。
如图1B所示，根据一些实施例，对模塑层170及重分布结构120上进行切割工艺，以切断模塑层170及重分布结构120而形成芯片封装体100。为简化起见，图1B仅示出根据一些实施例的多个芯片封装体100其中一者。
在一些实施例中，相邻导电接垫122之间的平均距离大于相邻导电接垫128之间的平均距离。因此，重分布结构120也称为扇出式中介层(interposer)。芯片封装体100也称为扇出式芯片封装体。
如图1C所示，根据一些实施例，提供一承载基底210。根据一些实施例，承载基底210作为在后续工艺步骤期间提供暂时性的机械及结构性支撑。根据一些实施例，承载基底210包括玻璃、硅、氧化硅、氧化铝、金属，其组合及/或相似物。根据一些实施例，承载基底210包括金属框架。
如图1C所示，根据一些实施例，形成一粘着层A2于承载基底210上。根据一些实施例，粘着层A2与承载基底210直接接触。根据一些实施例，粘着层A2顺应性地形成于承载基底210上。根据一些实施例，粘着层A2由绝缘材料制成，例如高分子材料。粘着层A2使用涂覆工艺或其他合适的工艺形成。
如图1C所示，根据一些实施例，形成一重分布结构220于粘着层A2上。根据一些实施例，重分布结构220具有表面S6及表面S7。根据一些实施例，表面S6与表面S7相对。根据一些实施例，表面S7面向承载基底210。
重分布结构220的制作包括形成一介电层221于粘着层A2上；形成多个导电接垫222于介电层221上及介电层221的通孔221a内；形成一介电层223于介电层221及导电接垫222上；形成一接线层224于介电层223上及介电层223的通孔223a内；形成一介电层225于介电层223及接线层224上；形成一接线层226于介电层225上及介电层225的通孔225a内；形成一介电层227于介电层225及接线层226上；形成多个导电接垫228于介电层227上及介电层227的通孔227a内。
根据一些实施例，介电层221与粘着层A2直接接触。根据一些实施例，介电层221顺应性地形成于粘着层A2上。在一些实施例中，介电层221内的导电接垫222的宽度W3沿着从表面S6至表面S7的方向V2减小。
在一些实施例中，介电层227中的导电接垫228的宽度W4沿着方向V2减小。根据一些实施例，导电接垫222比导电接垫228宽。举例来说，根据一些实施例，导电接垫222的最大宽度W3’大于导电接垫228的最大宽度W4’。接线层224与226彼此电性连接。根据一些实施例，导电接垫222及导电接垫228电性连接至接线层224及接线层226。
根据一些实施例，介电层221、介电层223、介电层225及介电层227由绝缘材料制成，例如高分子材料(例如，聚苯并恶唑、聚酰亚胺或光敏材料)、氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、氧氮化硅等。根据一些实施例，介电层221、介电层223、介电层225及介电层227由绝缘材料制成，上述绝缘材料不包含纤维材料(例如，玻璃纤维)。根据一些实施例，接线层224及接线层226以及导电接垫222及导电接垫228由导电材料制成，例如金属(例如，铜、铝或钨)。
如图1D所示，根据一些实施例，芯片封装体100通过多个导电凸块180接合至重分布结构220。根据一些实施例，导电凸块180位于导电接垫122与导电接垫228之间。根据一些实施例，导电凸块180将导电接垫122电性连接到导电接垫228。根据一些实施例，导电凸块180与导电接垫122及导电接垫228直接接触。
如图1D所示，根据一些实施例，形成一模塑层230于重分布结构220上方。根据一些实施例，模塑层230围绕芯片封装体100及导电凸块180。根据一些实施例，模塑层230与芯片封装体100及导电凸块180直接接触。根据一些实施例，模塑层230与模塑层170及重分布结构120直接接触。模塑层230由高分子材料或其他合适的绝缘材料制成。在一些实施例中，对模塑层230进行热工艺，以固化模塑层230。
模塑层230的制作包括：形成一模塑材料层(未示出)于重分布结构220和芯片封装体100上；通过进行例如化学机械研磨处理，去除芯片封装体100上的模塑材料层。根据一些实施例，模塑层230的上表面232与模塑层170的上表面172、基底142a的上表面S3、芯片144b的上表面S4以及芯片144b的上表面S5实质上共平面或对齐。
如图1D及图1E所示，根据一些实施例，去除承载基底210及粘着层A2。如图1D及图1E所示，根据一些实施例，去除介电层221以露出导电接垫222的侧壁222a。如图1E所示，根据一些实施例，多个导电凸块240分别形成在导电接垫222上。根据一些实施例，导电凸块240由焊料材料制成，例如Sn和Ag或其他合适的导电材料。
如图1E所示，根据一些实施例，对模塑层230及重分布结构220上进行切割工艺，以切断模塑层230及重分布结构220，而形成芯片封装结构200。为简化起见，图1E仅示出根据一些实施例的多个芯片封装结构200的其中一者。在一些实施例中，相邻导电接垫222之间的平均距离大于相邻导电接垫228之间的平均距离。因此，重分布结构220也称为扇出式中介层。
由于使用逐层沉积形成重分布结构220于承载基底210上(如图1D所示)，重分布结构220的平整度优于接线基底(包括一核心层及绝缘层形成于其上)。因此，改善了芯片封装体100和重分布结构220之间的接合工艺的良率。
再者，重分布结构220的特征部件尺寸(例如，线宽或相邻导电凸块180或导电凸块240之间的平均距离)小于接线基底的特征部件尺寸。因此，重分布结构220的接线密度及导电凸块密度大于接线基底的接线密度及导电凸块密度。如此一来，重分布结构220的信号传输及电源连接效率优于接线基底的信号传输及电源连接效率。
根据一些实施例，重分布结构220的线宽约在1.5μm至约15μm的范围内。根据一些实施例，相邻导电凸块180之间的平均距离约在22μm至200μm的范围内。根据一些实施例，相邻导电凸块240之间的平均距离在约在70μm至250μm的范围内。
在一些实施例中，导电接垫222的宽度W3沿着远离芯片封装体100的方向V2减小。在一些实施例中，介电层227中的导电接垫228的宽度W4沿着方向V2减小。
如图1F所示，根据一些实施例，提供一承载基底250。根据一些实施例，承载基底250作为在后续工艺步骤期间提供暂时性的机械及结构性支撑。根据一些实施例，承载基底250包括玻璃、硅、氧化硅、氧化铝、金属，其组合及/或相似物。根据一些实施例，承载基底250包括金属框架。
如图1F所示，根据一些实施例，一基底260设置于承载基底250上方。根据一些实施例，基底260包括一核心层262、多个导电接垫263a、263b、269c及269d、多个导电通孔结构264、多个绝缘层265、266及268以及多个接线层269a及269b。根据一些实施例，核心层262具有两相对的表面262a与表面262b。根据一些实施例，表面262a面向承载基底250。
核心层262由纤维材料、高分子材料、半导体材料、玻璃材料、金属材料或其他合适的材料制成。举例来说，纤维材料包括玻璃纤维材料。举例来说，半导体材料包括硅或锗。
根据一些实施例，多个导电接垫263a位于表面262a上方。根据一些实施例，多个导电接垫263b位于表面262b上方。根据一些实施例，多个导电通孔结构264穿过核心层262。根据一些实施例，导电通孔结构264位于导电接垫263a与导电接垫263b之间，且连接至导电接垫263a及导电接垫263b。
根据一些实施例，绝缘层265位于导电通孔结构264与核心层262之间、位于导电接垫263a与核心层262之间，以及位于导电接垫263b与核心层262之间。根据一些实施例，导电接垫263a及导电接垫263b以及导电通孔结构264通过绝缘层265与核心层262电性绝缘。
根据一些实施例，绝缘层266形成于表面262a上方。根据一些实施例，接线层269a形成于绝缘层266内，且电性连接至导电接垫263a及导电通孔结构264。根据一些实施例，导电接垫269c形成在绝缘层266内，且电性连接至接线层269a。根据一些实施例，绝缘层266具有分别露出导电接垫269c的开口266a。
根据一些实施例，绝缘层268形成于表面262b上方。根据一些实施例，接线层269b形成于绝缘层268内，且电性连接至导电接垫263b及导电通孔结构264。根据一些实施例，导电接垫269d形成于绝缘层268内，且电性连接至接线层269b。
根据一些实施例，绝缘层268具有分别露其下的导电接垫269d的开口268a。根据一些实施例，导电通孔结构264、导电接垫263a、263b、269c及269d以及接线层269a及269b由导电材料制成，例如铜、铝或钨。根据一些实施例，绝缘层265、266及268由氧化物(例如，氧化硅)的绝缘材料制成。
如图1F所示，根据一些实施例，芯片封装结构200通过导电凸块240接合至基底260。根据一些实施例，导电凸块240将导电接垫222电性连接至导电接垫269d。根据一些实施例，导电凸块240比导电凸块180宽。根据一些实施例，导电凸块180比导电凸块150宽。
之后，如图1F所示，根据一些实施例，一环形结构270通过粘着层280接合至基底260。根据一些实施例，环形结构270连续地围绕整个芯片封装结构200。根据一些实施例，环形结构270作为抗翘曲结构，以在后续工艺期间减少基底260的翘曲。
在一些实施例中，环形结构270的厚度T1大于重分布结构120的厚度T2与重分布结构220的厚度T3的总和。环形结构270由金属(例如，铜)，或其他合适的材料制成。根据一些实施例，粘着层280由高分子材料或其他合适的绝缘材料制成。
如图1F所示，根据一些实施例，形成一模塑层290于承载基底250、基底260及环形结构270上方。根据一些实施例，模塑层290围绕基底260、环形结构270、导电凸块240及芯片封装结构200。
在一些实施例中，模塑层290的上表面292与模塑层230的上表面232、模塑层170的上表面172、基底142a的上表面S3、芯片144b的上表面S4以及模塑层144d的上表面S5实质上共平面或对齐。
根据一些实施例，由于基底142a的上表面S3与芯片144b的上表面S4露出于模塑层144d、模塑层170、模塑层230及模塑层290，因此芯片142及芯片144b的散热效率获得改善。模塑层290由高分子材料或其他合适的绝缘材料制成。在一些实施例中，对模塑层290进行热工艺，以固化模塑层290。
如图1F及图1G所示，根据一些实施例，去除承载基底250。如图1G所示，根据一些实施例，多个导电凸块310分别形成于导电接垫269c上。根据一些实施例，导电凸块310由焊料材料制成，例如Sn及Ag或其他合适的导电材料。
如图1G所示，根据一些实施例，对模塑层290进行切割工艺，以切断模塑层290，而形成芯片封装结构300。为简化起见，图1G仅示出根据一些实施例的多个芯片封装结构300的其中一者。
图2是示出根据一些实施例的芯片封装体结构300A的剖面示意图。如图2所示，根据一些实施例，芯片封装结构300A相似于图1G中的芯片封装结构300，除了芯片封装结构300A还包括一环形结构320。根据一些实施例，环形结构320通过粘着层330接合至重分布结构220。
根据一些实施例，环形结构320及粘着层330连续地围绕整个芯片封装体100。根据一些实施例，环形结构320作为抗翘曲结构，以在后续工艺期间减少重分布结构220的翘曲。在一些实施例中，环形结构320的厚度T4大于重分布结构120的厚度T2。在一些实施例中，环形结构320的厚度T4大于重分布结构220的厚度T3。在一些实施例中，环形结构320的厚度T4小于环形结构270的厚度T1。
根据一些实施例，环形结构320由金属(例如，铜)或其他合适的材料制成。根据一些实施例，粘着层330由高分子材料或其他合适的绝缘材料制成。根据一些实施例，模塑层230覆盖并围绕环形结构320及粘着层330。根据一些实施例，模塑层230与环形结构320及粘着层330直接接触。
环形结构320的制作包括：在将芯片封装体100(图1B)接合至重分布结构220(图1C)之后，且在形成模塑层230于重分布结构220上之前(如图1D所示)，通过粘着层330将环形结构320接合至重分布结构220。
图3是示出根据一些实施例的芯片封装体结构300B的剖面示意图。如图3所示，根据一些实施例，芯片封装结构300B相似于图2中的芯片封装结构300A，不同之处在于芯片封装结构300B还包括多个被动装置341、342、343、344、345、346及347。
根据一些实施例，被动装置341设置于重分布结构120的表面S1上方。根据一些实施例，被动装置342设置于重分布结构120的表面S2上。根据一些实施例，被动装置343设置于重分布结构220的表面S6上。根据一些实施例，被动装置344设置于重分布结构220的表面S7上。
根据一些实施例，被动装置345设置在核心层262的表面262b上。根据一些实施例，被动装置346设置在核心层262的表面262a上。根据一些实施例，核心层262具有开口262c。根据一些实施例，被动装置347位于开口262c内。根据一些实施例，被动装置341、342、343、344、345、346及347包括电容器、电感器、电阻器或其他合适的装置。在一些实施例中，一填充层350填充于开口262c内。根据一些实施例，填充层350由绝缘材料制成。
图4A至图4F是示出根据一些实施例的不同制造阶段的芯片封装体结构制造方法剖面示意图。如图4A所示，根据一些实施例，提供一芯片封装结构400。在一些实施例中，芯片封装结构400相似于图1B的芯片封装体100，除了芯片封装结构400还包括一中介基底410，且不包括图1B的芯片封装体100的重分布结构120。
根据一些实施例，中介基底410包括一核心层412、多个导电接垫419c及419d、多个导电通孔结构414、绝缘层415、416及418，以及多个接线层419a及419b。根据一些实施例，核心层412具有两相对的表面412a及表面412b。
核心层412由半导体材料、玻璃材料、金属材料、纤维材料、高分子材料或其他合适的材料制成。例如，半导体材料包括硅或锗。例如，纤维材料包括玻璃纤维材料。
根据一些实施例，导电通孔结构414穿过核心层412。根据一些实施例，绝缘层415位于导电通孔结构414与核心层412之间。根据一些实施例，导电通孔结构414通过绝缘层415与核心层412电性绝缘。
根据一些实施例，绝缘层416形成于表面412a上方。根据一些实施例，接线层419a形成于绝缘层416内，且电性连接至导电通孔结构414。根据一些实施例，导电接垫419c形成于绝缘层416内，且电性连接至接线层419a。根据一些实施例，绝缘层416具有分别露出导电接垫419c的开口416a。
根据一些实施例，绝缘层418形成于表面412b上方。根据一些实施例，接线层419b形成于绝缘层418内，且电性连接至导电通孔结构414。根据一些实施例，导电接垫419d形成于绝缘层418内，且电性连接至接线层419b。
根据一些实施例，绝缘层418具有分别露出其下的导电接垫419d的开口418a。根据一些实施例，导电通孔结构414电性连接至导电接垫419c及导电接垫419d。根据一些实施例，导电通孔结构414、导电接垫419c及419d以及接线层419a和419b由导电材料制成，例如铜、铝或钨。根据一些实施例，绝缘层415、416及418由氧化物(例如，氧化硅)的绝缘材料制成。
根据一些实施例，芯片结构140通过导电凸块150接合到中介基底410。根据一些实施例，一些导电凸块150位于导电接垫419d与内连接层142c之间，以通过内连接层142c的内连接结构(未示出)将导电接垫419d电性连接至导电接垫P。根据一些实施例，一些其他导电凸块150位于导电接垫419d与重分布结构144a之间，以通过重分布结构144a与导电凸块144c的接线层(未示出)将导电接垫419d电性连接至芯片144b。
如图4A所示，根据一些实施例，多个导电凸块180分别形成在导电接垫419c上。根据一些实施例，导电凸块180由焊料材料制成，例如Sn及Ag或其他合适的导电材料。
如图4B所示，根据一些实施例，提供一承载基底210。如图4B所示，根据一些实施例，形成一粘着层A2于承载基底210上。如图4B所示，根据一些实施例，形成一重分布结构220于粘着层A2上。
根据一些实施例，承载基底210、粘着层A2以及重分布结构220的形成方法、结构以及材料与图1C的承载基底210、粘着层A2以及重分布结构220的形成方法、结构以及材料相同(或相似)。
根据一些实施例，介电层221与粘着层A2直接接触。根据一些实施例，介电层221顺应性地形成于粘着层A2上。在一些实施例中，介电层221内的导电接垫222的宽度W3沿着从表面S6至表面S7的方向V2减小。
在一些实施例中，介电层227内的导电接垫228的宽度W4沿着方向V2减小。根据一些实施例，导电接垫222比导电接垫228宽。例如，根据一些实施例，导电接垫222的最大宽度W3’大于导电接垫228的最大宽度W4’。接线层224与接线层226彼此电连接。根据一些实施例，导电接垫222及导电接垫228电性连接至接线层224及接线层226。
如图4C所示，根据一些实施例，芯片封装结构400通过导电凸块180接合至重分布结构220。根据一些实施例，导电凸块180位于导电接垫419c与导电接垫228之间。根据一些实施例，导电凸块180将导电接垫419c电性连接至导电接垫228。根据一些实施例，导电凸块180与导电接垫419c及导电接垫228直接接触。
如图4C所示，根据一些实施例，形成一模塑层230于重分布结构220上方。根据一些实施例，模塑层230围绕芯片封装结构400及导电凸块180。根据一些实施例，模塑层230与芯片封装结构400及导电凸块180直接接触。
根据一些实施例，模塑层230与模塑层170及中介基底410直接接触。模塑层230由高分子材料或其他合适的绝缘材料制成。在一些实施例中，对模塑层230进行热工艺，以固化模塑层230。
如图4C及图4D所示，根据一些实施例，去除承载基底210及粘着层A2。如图4C及图4D所示，根据一些实施例，去除介电层221，以露出导电接垫222的侧壁222a。如图4D所示，根据一些实施例，多个导电凸块240分别形成在导电接垫222上。根据一些实施例，导电凸块240由焊料材料制成，例如Sn及Ag或其他合适的导电材料。
如图4D所示，根据一些实施例，对模塑层230及重分布结构220上进行切割工艺，以切断模塑层230及重分布结构220，而形成多个芯片封装结构500。为简化起见，图4D仅示出根据一些实施例的多个芯片封装结构500的其中一者。
如图4E所示，根据一些实施例，提供一承载基底250。如图4E所示，根据一些实施例，一基底260设置于承载基底250上方。根据一些实施例，承载基底250及基底260的形成方法、结构以及材料与图1F的承载基底250及基底260的形成方法、结构以及材料相同(或相似)。
如图4E所示，根据一些实施例，芯片封装结构500通过导电凸块240接合至基底260。根据一些实施例，导电凸块240将导电接垫222电性连接至导电接垫269d。根据一些实施例，导电凸块240比导电凸块180宽。根据一些实施例，导电凸块180比导电凸块150宽。
如图4E所示，根据一些实施例，一环形结构270通过一粘着层280接合至基底260。根据一些实施例，环形结构270连续地围绕整个芯片封装结构500。根据一些实施例，环形结构270及粘着层280的形成方法、结构以及材料与图1F的环形结构270及粘着层280的形成方法、结构以及材料相同(或相似)。
如图4E所示，根据一些实施例，形成一模塑层290于承载基底250、基底260、环形结构270以及导电凸块240上方。根据一些实施例，模塑层290围绕基底260、环形结构270、导电凸块240以及芯片封装结构500。模塑层290由高分子材料或其他合适的绝缘材料制成。在一些实施例中，对模塑层290进行热工艺，以固化模塑层290。
如图4E及图4F所示，根据一些实施例，去除承载基底250。如图4F所示，根据一些实施例，多个导电凸块310分别形成在导电接垫269c上。根据一些实施例，导电凸块310由焊料材料制成，例如Sn及Ag或其他合适的导电材料。
如图4F所示，根据一些实施例，对模塑层290进行切割工艺，以切断模塑层290，而形成多个芯片封装结构600。为简化起见，图4F仅示出根据一些实施例的多个芯片封装结构600的其中一者。
图5是示出根据一些实施例的芯片封装体结构600A的剖面示意图。如图5所示，根据一些实施例，芯片封装结构600A相似于图4F中的芯片封装结构600，除了芯片封装结构600A还包括一环形结构320。根据一些实施例，环形结构320通过粘着层330接合至重分布结构220。
根据一些实施例，环形结构320及粘着层330连续地围绕整个芯片封装结构400。根据一些实施例，环形结构320及粘着层330的形成方法、结构以及材料与图2的环形结构320及粘着层330的形成方法、结构以及材料相同(或相似)。
根据一些实施例，模塑层230覆盖并围绕环形结构320及粘着层330。根据一些实施例，模塑层230与环形结构320及粘着层330直接接触。
图6是示出根据一些实施例的芯片封装体结构600B的剖面示意图。如图6所示，根据一些实施例，芯片封装结构600B相似于图5中的芯片封装结构600A，不同之处在于芯片封装结构600B包括被动装置341、被动装置342、被动装置343、被动装置344、被动装置345、被动装置346以及被动装置347。
根据一些实施例，被动装置341设置于中介基底410的表面S8上。根据一些实施例，被动装置342设置于中介基底410的表面S9上。根据一些实施例，被动装置343设置于重分布结构220的表面S6上。根据一些实施例，被动装置344设置于重分布结构220的表面S7上。
根据一些实施例，被动装置345设置于核心层262的表面262b上。根据一些实施例，被动装置346设置于核心层262的表面262a上。根据一些实施例，核心层262具有一开口262c。根据一些实施例，被动装置347位于开口262c内。根据一些实施例，被动装置341、被动装置342、被动装置343、被动装置344、被动装置345、被动装置346以及被动装置347包括电容器、电感器、电阻器或其他合适的装置。在一些实施例中，一填充层350填充于开口262c内。根据一些实施例，填充层350由绝缘材料制成。
根据一些实施例，提供芯片封装体结构的制造方法。上述方法(用于形成芯片封装体结构)将芯片封装体结构接合至重分布结构。由于使用逐层沉积于承载基底上形成重分布结构，因此改善了重分布结构的平整度。因此，改善了芯片封装体结构与重分布结构之间的接合工艺的良率。
根据一些实施例，提供一种芯片封装体结构的制造方法。上述方法包括形成一第一重分布结构于一第一承载基底上。第一重分布结构具有一第一表面及一第二表面。上述方法包括通过一第一导电凸块将一芯片结构接合至第一表面。上述方法包括形成一第一模塑层于第一重分布结构上，且围绕芯片结构。上述方法包括去除第一承载基底。上述方法包括形成一第二导电凸块于第二表面上。上述方法包括形成一第二重分布结构于一第二承载基底上。第二重分布结构具有一第三表面及相对于第三表面且面向第二承载基底的一第四表面。上述方法包括通过第二导电凸块将第一重分布结构接合至第三表面。上述方法包括形成一第二模塑层于第二重分布结构上，且围绕第一模塑层、第一重分布结构以及芯片结构。上述方法包括去除第二承载基底。上述方法包括从第四表面去除第二重分布结构的一部分。上述方法包括形成一第三导电凸块于第四表面上。
在一些实施例中，第二导电凸块位于第一重分布结构与第二重分布结构之间，且与第一重分布结构及第二重分布结构直接接触。在一些实施例中，第二模塑层围绕第二导电凸块，且与第二导电凸块直接接触。在一些实施例中，上述方法还包括在形成第二导电凸块于第二表面上之后，切断第一重分布结构及第一模塑层。在上述方法的一些实施例中，上述方法还包括在形成第三导电凸块于第四表面上之后，切断第二重分布结构及第二模塑层。在一些实施例中，第一重分布结构包括：一第一介电层、一第一布线层以及一第一导电接垫，第一介电层覆盖第一导电接垫，第一接线层位于第一介电层上方并穿过第一介电层而连接第一导电接垫，且上述方法还包括：在形成第二导电凸块于第二表面上之前，从第一重分布结构的第二表面局部去除第一介电层，以露出第一导电接垫的一第一侧壁，其中第二导电凸块形成于第一导电接垫上。在上述方法一些实施例中，第二重分布结构包括一第二介电层、一第二接线层以及一第二导电接垫，第二介电层覆盖第二导电接垫，第二接线层位于第二介电层上方并穿过第二介电层而连接第二导电接垫，且从第四表面局部去除第二重分布结构包括：在形成第三导电凸块于第四表面之前，从第二重分布结构的第四表面局部去除第二介电层，以露出第二导电接垫的一第二侧壁，其中第三导电凸块形成于第二导电接垫上方。在上述方法一些实施例中，第一导电接垫的一第一宽度沿着从第一表面到第二表面的方向减小，第二导电接垫的一第二宽度沿着上述方向减小。在一些实施例中，上述方法还包括通过第三导电凸块将第二重分布结构接合至一基底。在一些实施例中，芯片结构的一第一上表面、第一模塑层的一第二上表面以及第二模塑层的一第三上表面为共平面的。
根据一些实施例，提供一种芯片封装体结构的制造方法。上述方法包括通过一第一导电凸块将一芯片结构接合至一中介基板。中介基板包括一核心层及穿过核心层并电性连接至芯片结构的一导电通孔结构。上述方法包括形成一第一模塑层于中介基板上并围绕芯片结构。上述方法包括形成一第二导电凸块于中介层基板上。中介基板位于第二导电凸块与芯片结构之间。上述方法包括形成一重分布结构于承载基底上。重分布结构具有一第一表面及一第二表面。上述方法包括通过第二导电凸块将中介基板接合至第一表面。上述方法包括形成一第二模塑层于重分布结构上并围绕第一模塑层、中介基板以及芯片结构。上述方法包括去除承载基底。上述方法包括从第二表面去除重分布结构的一部分。上述方法包括形成一第三导电凸块于第二表面上。
在一些实施例中，第二导电凸块位于中介基板与重分布结构之间并与中介基板及重分布结构直接接触。在一些实施例中，第二模塑层围绕第二导电凸块，第二模塑层与第二导电凸块、中介基板、第一模塑层以及重分布结构直接接触。在一些实施例中，上述方法还包括在形成第三导电凸块于第二表面上之后，切断重分布结构及第二模塑层。在一些实施例中，第三导电凸块比第二导电凸块宽，且第二导电凸块比第一导电凸块宽。
根据一些实施例，提供一种芯片封装体结构。上述芯片封装体结构包括一第一重分布结构，具有一第一表面及一第二表面。第一重分布结构包括一第一接垫及一第二接垫，第一接垫与第一表面相邻，且第二接垫与第二表面相邻。上述芯片封装体结构包括一芯片封装体，通过一第一凸块接合至第一接垫，其中第一接垫的第一宽度沿远离芯片封装体的一第一方向上减小，而第二接垫的一第二宽度沿第一方向上减小。上述芯片封装体结构包括一第二导电凸块位于第二接垫上。
在一些实施例中，第二接垫比第一接垫宽。在一些实施例中，第二凸块比第一凸块宽。在一些实施例中，上述芯片封装体结构还包括一模塑层位于第一重分布结构上，并围绕芯片封装体及第一凸块。在一些实施例中，芯片封装体包括一第二重分布结构，第二重分布结构具有一第三表面及一第四表面，第二重分布结构包括一第三接垫及一第四接垫，第三接垫与第三表面相邻，第四接垫与第四表面相邻，第三接垫的一第三宽度沿朝向第一重分布结构的一第二方向减小，以及第四接垫的一第四宽度沿第二方向减小。
以上概略说明了本公开数个实施例的特征，使所属技术领域中技术人员对于本公开的形态可更为容易理解。任何所属技术领域中技术人员应了解到可轻易利用本公开作为其它工艺或结构的变更或设计基础，以进行相同于此处所述实施例的目的及/或获得相同的优点。任何所属技术领域中技术人员也可理解与上述等同的结构并未脱离本公开的构思和保护范围内，且可在不脱离本公开的构思和范围内，当可作变动、替代与润饰。

Claims (1)

1.一种芯片封装体结构的制造方法，包括：
形成一第一重分布结构于一第一承载基底上，其中该第一重分布结构具有一第一表面及一第二表面；
通过一第一导电凸块将一芯片结构接合至该第一表面；
形成一第一模塑层于该第一重分布结构上，且围绕该芯片结构；
去除该第一承载基底；
形成一第二导电凸块于该第二表面上；
形成一第二重分布结构于一第二承载基底上，其中该第二重分布结构具有一第三表面及相对于该第三表面且面向该第二承载基底的一第四表面；
通过该第二导电凸块将该第一重分布结构接合至该第三表面；
形成一第二模塑层于该第二重分布结构上，且围绕该第一模塑层、该第一重分布结构以及该芯片结构；
去除该第二承载基底；
从该第四表面去除该第二重分布结构的一部分；以及
形成一第三导电凸块于该第四表面上。
CN201910603971.8A 2018-07-19 2019-07-05 芯片封装体结构的制造方法 Pending CN110739229A (zh)

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