CN111863630A - 形成芯片封装结构的方法 - Google Patents

形成芯片封装结构的方法 Download PDF

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Publication number
CN111863630A
CN111863630A CN202010277983.9A CN202010277983A CN111863630A CN 111863630 A CN111863630 A CN 111863630A CN 202010277983 A CN202010277983 A CN 202010277983A CN 111863630 A CN111863630 A CN 111863630A
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chip
layer
chip structure
strip
chip package
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陈俊廷
施应庆
卢思维
吴志伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN111863630A publication Critical patent/CN111863630A/zh
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Abstract

本公开提供一种形成芯片封装结构的方法，包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开。第一芯片结构与第二芯片结构之间具有第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽，此沟槽部分地位在第一芯片结构以及第二芯片结构之中，且部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条在第一芯片结构、第二芯片结构、以及第一间距上方。

Description

形成芯片封装结构的方法
技术领域
本公开实施例涉及一种芯片封装结构以及其形成方法。
背景技术
在各种电子应用，例如个人电脑、手机、数码相机和其他电子装置中使用了半导体装置。通常是通过在半导体基板上依序沉积绝缘层或介电层、导电层和半导体层，并使用微影制程和蚀刻制程图案化各种材料层，以在材料层上形成电路部件和元件来制造半导体装置。
通常许多集成电路会被制造在半导体晶圆上。可以在晶圆级上晶圆级处理和封装晶粒，并且已经开发了用于晶圆级封装的各种技术。由于芯片封装结构可能会需要具有不同功能的不同芯片，因此要形成具有不同芯片的可靠芯片封装结构是一种挑战。
发明内容
根据一些实施例，本公开提供一种形成芯片封装结构的方法，包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开。第一芯片结构与第二芯片结构之间具有第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽，此沟槽部分地位在第一芯片结构以及第二芯片结构之中，且部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条在第一芯片结构、第二芯片结构、以及第一间距上方。
根据一些实施例，本公开提供一种形成芯片封装结构的方法。此方法包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽，沟槽部分地位在第一芯片结构中，部分地位在第二芯片结构中或上方，以及部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条延伸跨过第一间距。
根据一些实施例，本公开提供一种芯片封装结构。芯片封装结构包括基板。芯片封装结构包括第一芯片结构以及第二芯片结构，位在基板上方。第一芯片结构与该第二芯片结构隔开。芯片封装结构包括抗翘曲条，位在第一芯片结构中，以及位在第二芯片结构中或上方。抗翘曲条连续地从第二芯片结构延伸到第一芯片结构中。
附图说明
以下将配合附图详述本公开的实施例。应注意的是，依据在业界的标准做法，多种特征并未按照比例示出且仅用以说明例示。事实上，可能任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1A至图1I是形成芯片封装结构的过程的各个阶段的剖面图。
图1A-1是根据一些实施例的图1A的芯片封装结构的俯视图。
图1B-1是根据一些实施例的图1B的芯片封装结构的俯视图。
图1C-1是根据一些实施例的图1C的芯片封装结构的俯视图。
图1I-1是根据一些实施例的图1I的芯片封装结构的俯视图。
图2A是根据一些实施例的芯片封装结构的剖面图。
图2B是根据一些实施例的图2A的芯片封装结构的俯视图。
图3是根据一些实施例的芯片封装结构的俯视图。
图4A是根据一些实施例的芯片封装结构的俯视图。
根据一些实施例，图4B是沿着图4A中的剖面线I-I’示出的芯片封装结构的剖面图。
图5是根据一些实施例的芯片封装结构的俯视图。
图6是根据一些实施例的芯片封装结构的剖面图。
图7是根据一些实施例的芯片封装结构的剖面图。
图8A是根据一些实施例的芯片封装结构的俯视图。
根据一些实施例，图8B是沿着图8A中的剖面线I-I’示出的芯片封装结构的剖面图。
其中，附图标记说明如下：
10：晶种层
100，200，300，400，500，600，700，800：芯片封装结构110：基板
111：半导体结构
111a，111b：表面
112：导孔
113：绝缘层
114，117：重分布结构
114a，117a：介电层
114b，117b：线路层
114c，117c：导孔
115：导电垫
116：绝缘层
118：导电垫
119：缓冲环
120，130：晶圆结构
124，139，162，172：顶表面
131，132，133，134：半导体晶粒
132a，133a，134a，158a，158b：侧壁
135，170：成型层
135a，156：下表面
136：导电接合结构
137，150：底部填充层
138：导孔
140，192：导电凸点
152，154，174，176：部分
160：抗翘曲条
164a，164b：端部
180：遮罩层
182：开口
212：焊接层
212a：焊球
610：基板
A：粘着层
B：底表面
C：内壁
G1，G2，G3，G4：间距
I-I’：剖面线
L1，L2，L3：长度
R：沟槽
SC：切割道
T1，T2，T3，T4，T5：厚度
W1，W2，W3，W4，W5，W6：宽度
具体实施方式
以下公开许多不同的实施方法或是范例来实行所提供的标的的不同特征，以下描述具体的元件及其排列的实施例以阐述本公开。当然这些实施例仅用以例示，且不该以此限定本公开的范围。举例来说，在说明书中提到第一特征部件形成于第二特征部件之上，其包括第一特征部件与第二特征部件是直接接触的实施例，另外也包括于第一特征部件与第二特征部件之间另外有其他特征的实施例，亦即，第一特征部件与第二特征部件并非直接接触。此外，在不同实施例中可能使用重复的标号或标示，这些重复仅为了简单清楚地叙述本公开，不代表所讨论的不同实施例及/或结构之间有特定的关系。
此外，其中可能用到与空间相关用词，例如“在…之间”、“下方”、＂下＂、＂上方＂、＂上＂及类似的用词，这些空间相关用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系，这些空间相关用词旨在涵盖包括特征的装置的不同方向。当设备被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相关形容词也将依转向后的方位来解释。应理解的是，可以在上述方法前、中、后提供额外的操作，并且对于上述方法的其他实施例来说，可以取代或去除所描述的一些操作。
以下对本公开的一些实施例进行描述。可以在所述实施例中描述的阶段之前、之中及/或之后提供额外的操作。对于不同的实施例，可以更换或去除所述的某些阶段。可以在半导体装置结构中增加额外的特征。对于不同的实施例，可以更换或去除以下描述的某些功能。尽管通过使用特定顺序来执行的操作以讨论一些实施例，但是可以通过其他的逻辑顺序来执行所述操作。
本公开亦可包括其他特征和制程。举例来说可以包括测试结构，以辅助3D包装或3DIC装置的验证测试。测试结构可以包括例如形成在重分布层中或基板上的测试垫，以允许测试3D封装或3DIC、使用探针及/或探针卡等。可以在中间结构以及最后的结构上执行验证测试。此外，本公开所公开的结构和方法可以与已知良好晶粒的中间验证的测试方法一起使用，以增加良率并降低成本。
图1A至图1I是形成芯片封装结构的制程的各个阶段的剖面图。图1A-1是根据一些实施例的图1A的芯片封装结构的俯视图。根据一些实施例，图1A是沿着图1A-1中的剖面线I-I’示出的芯片封装结构的剖面图。
根据一些实施例，如图1A和图1A-1所示，提供了基板110。在一些实施例中，基板110是晶圆。根据一些实施例，基板110包括半导体结构111、导孔112、绝缘层113、重分布结构114和导电垫115。
根据一些实施例，半导体结构111具有表面111a和111b。在一些实施例中，半导体结构111由包括单晶(single crystal)、多晶(polycrystal)或无定形(amorphous)结构的硅或锗的元素半导体材料所形成。
在一些其他实施例中，半导体结构111由化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟或砷化铟)、合金半导体(例如SiGe或GaAsP)、或其组合所形成。半导体结构111还可包括多层半导体(multi-layer semiconductors)、绝缘体上半导体(semiconductor oninsulator，SOI)(例如绝缘体上硅或绝缘体上锗)、或其组合。
在一些实施例中，基板110是中置晶圆(interposer wafer)。根据一些实施例，导孔112形成在半导体结构111中。导孔112可以从表面111a延伸到半导体结构111中。根据一些实施例，绝缘层113形成在半导体结构111之上。根据一些实施例，绝缘层113位在导孔112和半导体结构111之间。
根据一些实施例，绝缘层113配置成使导孔112与半导体结构111电性绝缘。根据一些实施例，绝缘层113由含氧化物的材料形成，例如氧化硅。绝缘层113是使用氧化制程、沉积制程或其他合适的制程所形成。
在其他的一些实施例中，基板110是包括各种装置元件的装置晶圆。在一些实施例中，各种装置元件形成在基板110中及/或上方。为了简单和清楚起见，并未在图中绘示出装置元件。各种装置元件的范例包括主动装置、被动装置、其他合适的元件、或其组合。主动装置可以包括形成在表面111a的晶体管或二极管(未示出)。被动装置包括电阻、电容、或其他合适的被动装置。
举例来说，晶体管可为金属氧化物半导体场效晶体管(metal oxidesemiconductor field effect transistors，MOSFET)、互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)晶体管、双极性接面型晶体管(bipolar junction transistors，BJT)、高压晶体管(high-voltage transistors)、高频晶体管(high-frequency transistors)、p通道及/或n通道场效晶体管(p-channel and/orn-channel field effect transistor，PFETs/NFETs)等。执行各种制程以形成各种装置元件，例如前端生产线(front-end-of-line，FEOL)半导体制程。前端生产线半导体制造制程可包括沉积、蚀刻、布植、微影、退火、平坦化、一或多种其他合适的制程、或其组合。
在一些实施例中，在基板110中形成隔离特征(未示出)。隔离特征用于定义主动区域，并且电性隔离形成在主动区域中的基板110中及/或上方的各种装置元件。在一些实施例中，隔离特征包括浅沟槽隔离(shallow trench isolation，STI)特征、局部氧化硅(local oxidation of silicon，LOCOS)特征、其他合适的隔离特征、或其组合。
根据一些实施例，重分布结构114形成在半导体结构111上方。根据一些实施例，导电垫115形成在重分布结构114上方。根据一些实施例，重分布结构114包括介电层114a、线路层114b、和导孔114c。根据一些实施例，介电层114a形成在表面111a上。根据一些实施例，线路层114b形成在介电层114a中。
如图1A所示，根据一些实施例，导孔114c在不同的线路层114b之间、以及在线路层114b和导电垫115之间进行电性连接。根据一些实施例，为了简单起见，图1A仅示出一层线路层114b。根据一些实施例，导孔112通过线路层114b和导孔114c与导电垫115电性连接。
根据一些实施例，如图1A所示，芯片结构120和130通过在芯片结构120和基板110之间以及在芯片结构130和基板110之间的导电凸点140接合至基板110。根据一些实施例，芯片结构120和130与基板110彼此间隔开。根据一些实施例，在晶圆结构120与基板110之间，以及在晶圆结构130与基板110之间具有间距G1。根据一些实施例，导电凸点140位在间距G1中。
根据一些实施例，晶圆结构120和130彼此间隔开一间距G2。根据一些实施例，芯片结构120包括芯片，例如芯片上系统(system on chip，SoC)。在一些其他实施例中，芯片结构120包括芯片封装结构。
在一些实施例中，芯片结构130包括多个半导体晶粒。根据一些实施例，如图1A所示，芯片结构130包括半导体晶粒131、132、133和134。在一些实施例中，芯片结构130包括成型层135，用以封装和保护半导体晶粒132、133和134。成型层135可以包括在其中分散有填料的环氧基树脂(epoxy-based resin)。所述填料可包括绝缘纤维、绝缘颗粒、其他合适的元件、或其组合。
在一些实施例中，半导体晶粒132、133和134是存储器晶粒。存储器晶粒可以包括存储器装置，例如静态随机存取存储器(static random access memory，SRAM)装置、动态随机存取存储器(dynamic random access memo，DRAM)装置、其他合适的装置、或其组合等。在一些实施例中，半导体晶粒131是控制晶粒，电性连接到堆叠在半导体晶粒131上的存储晶粒(例如半导体晶粒132、133和134)。芯片结构130可以作为高带宽存储器(highbandwidth memory，HBM)。
可以对本公开的实施例进行各种变化及/或修改。在一些实施例中，芯片结构130包括单个半导体芯片。半导体芯片可为芯片上系统。如图1A所示，在一些实施例中，在半导体晶粒131、132、133和134之间形成导电接合结构136，以将半导体晶粒131、132、133和134结合在一起。在一些实施例中，每个导电接合结构136包括金属柱及/或焊接凸块(solderbumps)。
在一些实施例中，底部填充层137形成在半导体晶体131、132、133和134之间，以包围并保护导电接合结构136。在一些实施例中，底部填充层137包括有填料分散在其中的环氧基树脂。所述填料可包括绝缘纤维、绝缘颗粒、其他合适的元件或其组合。
在一些实施例中，如图1A所示，在半导体晶粒131、132和133中形成多个导孔138。每个导孔138穿过半导体晶粒131、132和133之一者，并且在导孔138下方及/或上方电性连接至导电接合结构136。可以通过导孔138，在垂直堆叠的半导体晶粒131、132、133和134之间传输电信号。
根据一些实施例，如图1A和图1A-1所示，底部填充层150形成在基板110与每个芯片结构120和130之间的间隔G1中。根据一些实施例，如图1A和图1A-1所示，芯片结构120和130之间的间隔G2填充有底部填充层150的一部分152。根据一些实施例，如第1A-1图所示，在芯片结构130之间的间隔G3填充有底部填充层150的一部分154。
根据一些实施例，底部填充层150围绕芯片结构120和130。根据一些实施例，底部填充层150称为保护层。根据一些实施例，底部填充层150包括聚合物材料。
根据一些实施例，图1B-1是图1B的芯片封装结构的俯视图。根据一些实施例，图1B是沿着图1B-1中的剖面线I-I’示出的芯片封装结构的剖面图。根据一些实施例，如图1B和图1B-1所示，去除了晶圆结构120和130以及底部填充层150的一部分。所述去除制程部分地去除了芯片结构130的成型层135以及底部填充层150的部分152和154。
根据一些实施例，在去除制程之后，在每个芯片结构130中剩余的成型层135覆盖半导体晶粒132、133和134的整个侧壁132a、133a和134a。根据一些实施例，在去除制程之后，在每个芯片结构130中剩余的成型层135和半导体晶粒132覆盖半导体晶体131的整个顶表面131a。
根据一些实施例，所述去除制程部分地在晶圆结构120和130和底部填充层150中形成沟槽R。根据一些实施例，沟槽R不穿过芯片结构120和130以及底部填充层150。根据一些实施例，沟槽R部分地位于间距G2和G3的上方。即，根据一些实施例，沟槽R与间隔G2和G3部分重叠。
根据一些实施例，如图1B所示，芯片结构120的下表面122、芯片结构130的下表面135a和底部填充层150的下表面156一起形成沟槽R的底表面B。根据一些实施例，下表面122、135a和156实质上共平面。本公开中的用语“实质上共平面”可以包括与共平面几何形状之间的小偏差。所述偏差可能是由于制造制程所引起的。
根据一些实施例，图1C-1是图1C的芯片封装结构的俯视图。根据一些实施例，图1C是沿着图1C-1中的剖面线I-I’示出的芯片封装结构的剖面图。如图1C和图1C-1所示，抗翘曲条160分别形成在沟槽R中。
根据一些实施例，抗翘曲条160位在芯片结构120和130以及底部填充层150的部分152和154之上。根据一些实施例，抗翘曲条160位在底表面B上方。根据一些实施例，抗翘曲条160延伸跨过间隔G2和G3。根据一些实施例，抗翘曲条160从芯片结构120连续地延伸到芯片结构130中。
根据一些实施例，抗翘曲条160与晶圆结构120和130以及底部填充层150间隔开。在一些实施例中，抗翘曲条160的宽度W1小于沟槽R的宽度W2。根据一些实施例，宽度W2为约1μm至约10mm。
根据一些实施例，抗翘曲条160与沟槽R的内壁C隔开一间隔G4。根据一些实施例，抗翘曲条160的宽度W1小于抗翘曲条160的长度L1。根据一些实施例，长度L1小于等于沟槽R的长度L2。根据一些实施例，长度L2小于等于芯片结构120的长度L3。
根据一些实施例，间距G2具有宽度W3。根据一些实施例，沟槽R的宽度W2大于宽度W3。根据一些实施例，芯片结构120上方的抗翘曲条160具有宽度W4。
根据一些实施例，晶圆结构130上方的抗翘曲条160具有宽度W5。根据一些实施例，宽度W4大于宽度W3。在一些实施例中，宽度W4与宽度W3的比值在约2至约50的范围内。根据一些实施例，宽度W3在约0.5μm至约200μm的范围内。
根据一些实施例，宽度W4在约100μm至约2000μm的范围内。根据一些实施例，宽度W5大于宽度W3。根据一些实施例，宽度W5在约100μm至约2000μm的范围内。在一些实施例中，宽度W4大于宽度W5。
根据一些实施例，抗翘曲条160比底部填充层150硬。即，根据一些实施例，抗翘曲条160由比底部填充层150的材料硬的材料所制成。举例来说，抗翘曲条160由金属材料或半导体材料所制成。
根据一些实施例，所述金属材料包括铜、金、银、铝、其合金、其组合或其他合适的材料。根据一些实施例，如果抗翘曲条160由金属材料制成，则抗翘曲条160提高了芯片结构120和130的散热效率。
半导体材料包括元素半导体材料，所述元素半导体材料包括单晶、多晶或非晶结构的硅或锗。在其他一些实施例中，抗翘曲条160由化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、或砷化铟)、合金半导体(例如SiGe或GaAsP)、或其组合所制成。抗翘曲条160还可以包括多层半导体、绝缘体上半导体(SOI)(例如绝缘体上硅或绝缘体上锗)、或其组合。
根据一些实施例，如图1C所示，每个抗翘曲条160通过下方的粘着层A接合到晶圆结构120和130以及底部填充层150。根据一些实施例，粘着层A位在抗翘曲条160与芯片结构120之间、抗翘曲条160与芯片结构130之间、以及抗翘曲条160与底部填充层150之间。在一些实施例中，抗翘曲条160的厚度T1大于粘着层A的厚度T2。在一些实施例中，晶圆结构120的厚度T3大于厚度T1和T2。
根据一些实施例，粘着层A直接接触上方的抗翘曲条160、下方的晶圆结构120和130、以及下方的底部填充层150。根据一些实施例，粘着层A由绝缘材料、聚合物材料或金属制成。
根据一些实施例，如图1D所示，在基板110、芯片结构120和130、导电凸点140、底部填充层150、抗翘曲条160和粘着层A上方形成成型层170。根据一些实施例，成型层170填充在间距G4中。根据一些实施例，抗翘曲条160比成型层170硬。根据一些实施例，成型层170包括聚合物材料。
根据一些实施例，如图1E所示，薄化成型层170，直到露出芯片结构120和130的顶表面124和139。根据一些实施例，薄化制程包括化学机械研磨(chemical mechanicalpolishing，CMP)制程。根据一些实施例，在薄化制程之后，芯片结构120和130的顶表面124、139和172与成型层170实质上共平面。
根据一些实施例，在薄化制程之后，成型层170的一部分174残留在沟槽R中。根据一些实施例，在沟槽R中，部分174围绕(或环绕)抗翘曲条160和粘着层A。根据一些实施例，在沟槽R中，部分174覆盖整个抗翘曲条160和整个粘着层A。根据一些实施例，在薄化制程之后，成型层170的一部分176保留在基板110上方和在沟槽R的外部。
根据一些实施例，部分176围绕芯片结构120和130、导电凸点140、底部填充层150、抗翘曲条160、和粘着层A。根据一些实施例，部分174和176彼此隔开。
根据一些实施例，如图1F所示，去除半导体结构111的下部。根据一些实施例，去除制程包括化学机械研磨(CMP)制程。根据一些实施例，在去除制程之后露出导孔112和绝缘层113。
根据一些实施例，导孔112和绝缘层113穿过半导体结构111。根据一些实施例，当半导体结构111是硅基板时，导孔112也被称为基板通孔或硅通孔。
根据一些实施例，如图1G所示，上下翻转半导体结构111。根据一些实施例，如图1G所示，在表面111b上方形成绝缘层116。根据一些实施例，绝缘层116配置为使随后形成在绝缘层116上方的线路层与半导体结构111电性绝缘。根据一些实施例，绝缘层116由含氧化物的材料制成，例如氧化硅。利用氧化制程、沉积制程或其他合适的制程形成绝缘层116。
在一些实施例中，在半导体结构111的表面111b上形成重分布结构117。在一些实施例中，重分布结构117包括介电层117a、线路层117b、和导孔117c。在一些实施例中，线路层117b形成在介电层117a中。
根据一些实施例，如图1G所示，在重分布结构117上形成导电垫118。根据一些实施例，导孔117c在不同的线路层117b之间以及线路层117b和导电垫118之间进行电性连接。根据一些实施例，为了简洁起见，图1G仅示出线路层117b之一者。根据一些实施例，导孔112通过线路层117b和导孔117c与导电垫118电性连接。
根据一些实施例，如图1G所示，在导电垫118上方形成缓冲环119。根据一些实施例，缓冲环119具有开口119a，以露出下方的导电垫118。根据一些实施例，缓冲环119配置成用来缓冲随后形成在缓冲环119上方的凸块和基板110之间的应力。
根据一些实施例，缓冲环119由如聚合材料(例如聚酰亚胺，polyimide)的弹性材料所制成。在一些其他实施例中(未示出)，将缓冲环119替换为具有开口的缓冲层，以露出导电垫118。
根据一些实施例，如图1G所示，在重分布结构117、缓冲环119和导电垫118上形成晶种层10。晶种层10的材料可以包括铜或铜合金。晶种层10的材料可包括其他金属，例如银、金、铝、及其组合。
根据一些实施例，如图1G所示，在晶种层10上方形成遮罩层180。根据一些实施例，遮罩层180具有开口182，开口182露出在导电垫118和缓冲环119上方并邻接导电垫118的晶种层10。根据一些实施例，遮罩层180由如光阻材料的聚合物材料所制成。
根据一些实施例，如图1H所示，在开口182中和导电垫118上方形成导电凸点192。在一些实施例中，导电凸点192通过基板110电性连接到晶圆结构120及/或130。根据一些实施例，导电凸点192由如铜(Cu)、铝(Al)、钨(W)、钴(Co)、或镍(Ni)的导电材料制成。根据一些实施例，导电凸点192使用如电镀(electroplating)制程的类的镀层(plating)制程形成。
根据一些实施例，如图1H所示，焊接层212形成在导电凸点192上方。根据一些实施例，焊接层212由锡(Sn)或熔点低于导电凸点192的熔点的其他合适的导电材料制成。根据一些实施例，使用如电镀制程的镀层制程来形成焊接层212。
如图1I所示，根据一些实施例，去除遮罩层180。根据一些实施例，如图1I所示，去除了原先被遮罩层180覆盖的晶种层10。根据一些实施例，使用蚀刻制程去除晶种层10。根据一些实施例，如图1I所示，在焊接层212上执行回流(reflow)制程以将焊接层212转换成焊球212a。
根据一些实施例，图1I-1是图1I的芯片封装结构的俯视图。根据一些实施例，图1I是沿着图1I-1中的剖面线I-I’示出的芯片封装结构的剖面图。根据一些实施例，如第1H图、图1I和图1I-1所示，执行切割制程以沿着预定的切割道SC来切割基板110和成型层170，从而形成芯片封装100。根据一些实施例，为了简洁起见，图1I仅示出芯片封装100之一者。
根据一些实施例，如图1I所示，上下翻转芯片封装100。根据一些实施例，如图1I-1所示，通过底部填充层150的部分152和154以及芯片结构120和130，将成型层170的部分174与成型层170的部分176分隔开。
由于在晶圆结构120和130之间的底部填充层150的部分152被比底部填充层150硬的抗翘曲条160部分取代，因此抗翘曲条160降低了由于芯片结构120和130之间的热膨胀系数(thermal expansion，CTE)不匹配所导致的芯片封装100的翘曲。
根据一些实施例，图2A是芯片封装结构200的剖面图。根据一些实施例，图2B是图2A的芯片封装结构200的俯视图。根据一些实施例，图2A是沿着图2B中的剖面线I-I’的芯片封装结构200示出的剖面图。
根据一些实施例，如图2A和图2B所示，芯片封装结构200的结构和形成方法与图1I的芯片封装结构100的结构和形成方法相似，而不同之处在于芯片封装结构200的成型层170的形成方式。
芯片封装结构200的成型层170的形成方式包括：在基板110、芯片结构120和130、导电凸点140、底部填充层150、抗翘曲条160、和粘着层A上方形成成型层170(如图1D所示)。然后薄化成型层170，直到露出芯片结构120和130的顶表面124、139和162以及抗翘曲条160(如图2A和图2B所示)。
根据一些实施例，薄化制程包括化学机械研磨(CMP)制程。根据一些实施例，在薄化制程之后，残留在沟槽R中的成型层170围绕(或环绕)抗翘曲条160和粘着层A。根据一些实施例，在薄化制程之后，芯片结构120和130的顶表面124、139、162和172、抗翘曲条160、和成型层170实质上是共平面的。
根据一些实施例，图3是芯片封装结构300的俯视图。根据一些实施例，如图3所示，芯片封装结构300与图2A和图2B的芯片封装结构200相似，不同之处在于沟槽R的长度L2实质上等于晶圆结构120的长度L3。因此，根据一些实施例，在沟槽R中的成型层170的部分174连接到在沟槽R外的成型层170的部分176。根据一些实施例，抗翘曲条160具有条状的形状。根据一些实施例，抗翘曲条160具有均匀的宽度。
根据一些实施例，图4A是芯片封装结构400的俯视图。根据一些实施例，图4B是沿着图4A中的剖面线I-I’示出的芯片封装结构400的剖面图。
根据一些实施例，如图4A和图4B所示，芯片封装结构400与图3的芯片封装结构300相似，不同之处在于抗翘曲条160的长度L1大于芯片结构120的长度L3。根据一些实施例，抗翘曲条160的端部164a和164b分别从底部填充层150的侧壁158a和158b突出。
根据一些实施例，图5是芯片封装结构500的俯视图。根据一些实施例，如图5所示，芯片封装结构500与图3的芯片封装结构300相似，不同之处在于芯片封装结构500的抗翘曲条160具有与芯片封装结构300的抗翘曲条160的结构不同的I字形的形状。根据一些实施例，图3的芯片封装结构300的抗翘曲条160具有条形的形状。
根据一些实施例，图6是芯片封装结构600的剖面图。根据一些实施例，如图6所示，图2A的晶圆封装结构200接合到基板610。在将芯片封装结构200接合到基板610之后，芯片封装结构200可以沿着芯片结构120和130之间的间隔G2稍微弯曲。
根据一些实施例，抗翘曲条160和基板110可以稍微弯曲。根据一些实施例，在芯片结构120的正下方的焊球212a的厚度T4大于在芯片结构130的正下方的焊球212a的厚度T5。
基板610可为布线基板或中置基板。在一些其他实施例中，芯片封装结构200被图1I的芯片封装结构100、图3的芯片封装结构300、图4A的芯片封装结构400、图5的芯片封装结构500、或图7的芯片封装结构700所取代。
根据一些实施例，图7是根据一些实施例的芯片封装结构700的剖面图。根据一些实施例，如第7图所示，芯片封装结构700类似于图2A的芯片封装结构200，不同之处在于芯片封装结构700不具有底部填充层150。根据一些实施例，成型层170与基板110、芯片结构120和130、导电凸点140、抗翘曲条160和粘着层A直接接触。
根据一些实施例，图8A是芯片封装结构800的俯视图。根据一些实施例，图8B是沿着图8A中的剖面线I-I’示出的芯片封装结构800的剖面图。
根据一些实施例，如图8A和图8B所示，芯片封装结构800与图4A的芯片封装结构400类似，不同之处在于抗翘曲条160的宽度W1大于芯片结构120的宽度W6。根据一些实施例，抗翘曲条160延伸跨过芯片结构120。
用于形成芯片封装结构200、300、400、500、700和800的制程和材料可以与用于形成上述芯片封装结构100的制程或材料相似或相同。
根据一些实施例，本公开提供了一种芯片封装结构及其形成方法。所述(用于形成所述芯片封装结构的)方法在第一晶圆结构和第二晶圆结构中形成延伸跨过所述第一晶圆结构和所述第二晶圆结构之间的间隙的抗翘曲条。抗翘曲条减少了由第一晶圆结构和第二晶圆结构之间的热膨胀系数不匹配引起的芯片封装结构的翘曲。
根据一些实施例，本公开提供一种形成芯片封装结构的方法，包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开。第一芯片结构与第二芯片结构之间具有第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽，此沟槽部分地位在第一芯片结构以及第二芯片结构之中，且部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条在第一芯片结构、第二芯片结构、以及第一间距上方。
在一些实施例中，形成芯片封装结构的方法还包括在将第一芯片结构以及第二芯片结构接合到基板的表面之后，且在去除第一芯片结构的第一部分以及第二芯片结构的第二部分之前，在第一间距中以及第二间距中形成底部填充层，第二间距位在第一芯片结构以及表面之间和位在第二芯片结构以及表面之间，其中去除第一芯片结构的第一部分以及第二芯片结构的第二部分的操作还包括去除第一间距中的底部填充层的第三部分。在一些实施例中，抗翘曲条位在第一间距中的底部填充层上方。在一些实施例中，抗翘曲条比该底部填充层硬。在一些实施例中，形成芯片封装结构的方法，还包括在沟槽中形成抗翘曲条后，在表面上方以及沟槽中形成成型层，其中在表面上方的成型层围绕第一芯片结构以及第二芯片结构，且沟槽中的成型层围绕抗翘曲条。在一些实施例中，抗翘曲条的第一宽度小于沟槽的第二宽度。在一些实施例中，抗翘曲条与沟槽的内壁隔开第二间距，且成型层填充第二间距。在一些实施例中，抗翘曲条比成型层硬。在一些实施例中，抗翘曲条通过粘着层接合到第一芯片结构以及第二芯片结构，粘着层位在抗翘曲条以及第一芯片结构之间，以及位在抗翘曲条和第二芯片结构之间。在一些实施例中，抗翘曲条的宽度小于抗翘曲条的长度。
根据一些实施例，本公开提供一种形成芯片封装结构的方法。此方法包括将第一芯片结构以及第二芯片结构接合到基板的表面。第一芯片结构与第二芯片结构隔开第一间距。此方法包括去除第一芯片结构的第一部分以及第二芯片结构的第二部分以形成沟槽，沟槽部分地位在第一芯片结构中，部分地位在第二芯片结构中或上方，以及部分地位在第一间距上方。此方法包括在沟槽中形成抗翘曲条。抗翘曲条延伸跨过第一间距。
在一些实施例中，形成芯片封装结构的方法还包括在将第一芯片结构以及第二芯片结构接合到基板的表面之后，且在去除第一芯片结构的第一部分以及第二芯片结构的第二部分之前，在第一间距中、以及位在第一芯片结构以及表面之间和位在第二芯片结构以及表面之间的第二间距中形成底部填充层，其中去除第一芯片结构的第一部分以及第二芯片结构的第二部分的操作还包括去除第一间距中的底部填充层的第三部分，以及第一芯片结构的第一下表面、第二芯片结构的第二下表面、以及底部填充层的第三下表面一起形成该沟槽的底表面，且抗翘曲条位在底表面上方。在一些实施例中，抗翘曲条通过粘着层接合到第一芯片结构、第二芯片结构、以及底部填充层，且粘着层直接接触抗翘曲条、第一芯片结构、第二芯片结构、以及底部填充层。在一些实施例中，抗翘曲条比底部填充层硬。在一些实施例中，抗翘曲条延伸跨过第二芯片结构。
根据一些实施例，本公开提供一种芯片封装结构。芯片封装结构包括基板。芯片封装结构包括第一芯片结构以及第二芯片结构，位在基板上方。第一芯片结构与该第二芯片结构隔开。芯片封装结构包括抗翘曲条，位在第一芯片结构中，以及位在第二芯片结构中或上方。抗翘曲条连续地从第二芯片结构延伸到第一芯片结构中。
在一些实施例中，芯片封装结构还包括底部填充层，位在第一芯片结构和第二芯片结构之间，位在第一芯片结构和基板之间，以及位在第二芯片结构和基板之间。在一些实施例中，抗翘曲条位在底部填充层上方，以及位在第一芯片结构和第二芯片结构之间。在一些实施例中，抗翘曲条与第一芯片结构以及第二芯片结构隔开。在一些实施例中，芯片封装结构还包括粘着层，位在抗翘曲条和第一芯片结构之间，以及位在抗翘曲条和第二芯片结构之间。
上述内容概述许多实施例的特征，因此任何所属技术领域中技术人员，可更加理解本公开的各面向。任何所属技术领域中技术人员，可能无困难地以本公开为基础，设计或修改其他制程及结构，以达到与本公开实施例相同的目的及/或得到相同的优点。任何所属技术领域中技术人员也应了解，在不脱离本公开的精神和范围内做不同改变、代替及修改，如这些效的创造并没有超出本公开的精神及范围。

Claims (1)

1.一种形成芯片封装结构的方法，包括：
将一第一芯片结构以及一第二芯片结构接合到一基板的一表面，其中该第一芯片结构与该第二芯片结构隔开，且该第一芯片结构与该第二芯片结构之间具有一第一间距；
去除该第一芯片结构的一第一部分以及该第二芯片结构的一第二部分以形成一沟槽，该沟槽部分地位在该第一芯片结构以及该第二芯片结构之中，且部分地位在该第一间距上方；以及
在该沟槽中形成一抗翘曲条，其中该抗翘曲条在该第一芯片结构、该第二芯片结构、以及该第一间距上方。
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