TWI818655B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

Info

Publication number
TWI818655B
TWI818655B TW111128961A TW111128961A TWI818655B TW I818655 B TWI818655 B TW I818655B TW 111128961 A TW111128961 A TW 111128961A TW 111128961 A TW111128961 A TW 111128961A TW I818655 B TWI818655 B TW I818655B
Authority
TW
Taiwan
Prior art keywords
resin film
semiconductor
semiconductor wafer
mentioned
semiconductor device
Prior art date
Application number
TW111128961A
Other languages
English (en)
Other versions
TW202335211A (zh
Inventor
板倉悟
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202335211A publication Critical patent/TW202335211A/zh
Application granted granted Critical
Publication of TWI818655B publication Critical patent/TWI818655B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H01L2224/32054—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Noodles (AREA)
  • Bipolar Transistors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明提供一種能夠提高半導體裝置之良率之半導體裝置及半導體裝置之製造方法。  實施方式之半導體裝置具備：配線基板；第1半導體晶片，其設置於上述配線基板之面上；樹脂膜，其覆蓋上述第1半導體晶片；及第2半導體晶片，其晶片面積較上述第1半導體晶片大，貼附於上述樹脂膜之上表面而安裝於上述配線基板；於自上述第1及第2半導體晶片之積層方向觀察時，上述樹脂膜整體落於上述第2半導體晶片之底面之內側區域內。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施方式係關於一種半導體裝置及半導體裝置之製造方法。
於將複數個半導體晶片安裝於印刷配線基板等配線基板上之半導體裝置中，有時將複數個半導體晶片中尺寸較小之半導體晶片直接安裝於配線基板上，自該半導體晶片之上，利用具有黏接性之樹脂膜將尺寸較大之半導體晶片貼附並安裝於配線基板。
此時，有時樹脂膜自尺寸較大之半導體晶片之端部突出。藉此，由於突出之樹脂膜，而阻礙半導體膜上之半導體晶片與配線基板之電性連接，導致半導體裝置之良率降低。
1個實施方式之目的在於提供一種能夠提高半導體裝置之良率之半導體裝置及半導體裝置之製造方法。
實施方式之半導體裝置具備：配線基板；第1半導體晶片，其設置於上述配線基板之面上；樹脂膜，其覆蓋上述第1半導體晶片；及第2半導體晶片，其晶片面積較上述第1半導體晶片大，貼附於上述樹脂膜之上表面而安裝於上述配線基板；於自上述第1及第2半導體晶片之積層方向觀察時，上述樹脂膜整體落於上述第2半導體晶片之底面之內側區域內。
1,1a,1b,2:半導體裝置
10,910:印刷配線基板
21,22,121,122,921,922:半導體晶片
21c,121c,921c:控制電路
22n,122n,922n:非揮發性記憶體
22g:交界部分
30,130,230,330,430,930:樹脂膜
31,131x,131y,231x,231y,331,431,436:凹部
32,33,233x,233y:切口
40,940:接合線
122x,122y:緣部
922w:基板
335,435,935:凸部
DT1,DT2,DTx:切割保護膠帶
DS,DSx:切割機
LS,LS2:雷射光
圖1(a)、(b)係表示實施方式1之半導體裝置之構成之一例之圖。
圖2(a)~(d)係將實施方式1之半導體裝置之製造方法之順序之一部分依次例示之沿著X方向或Y方向之剖視圖。
圖3(a)~(c)係將實施方式1之半導體裝置之製造方法之順序之一部分依次例示之沿著X方向或Y方向之剖視圖。
圖4(a)~(c)係表示比較例之半導體裝置之製造方法例及構成例之圖。
圖5(a)~(c)係表示實施方式1之變化例1之半導體裝置之構成之一例之圖。
圖6(a)、(b)係將實施方式1之變化例2之半導體裝置之製造方法之順序之一部分依次例示之XY剖視圖。
圖7係表示實施方式1之變化例3之半導體裝置之構成之一例之XZ剖視圖。
圖8係表示實施方式2之半導體裝置之構成之一例之XZ剖視圖。
圖9(a)~(c)係將實施方式2之半導體裝置之製造方法之順序之一部分依次例示之沿著X方向或Y方向之剖視圖。
以下，參照圖式對本發明詳細地進行說明。再者，本發明並不受下述實施方式限定。又，下述實施方式中之構成要素中包含業者能夠容易地設想之內容或者實質上相同之內容。
[實施方式1]
以下，參照圖式對實施方式1詳細地進行說明。
(半導體裝置之構成例)
圖1係表示實施方式1之半導體裝置1之構成之一例之圖。圖1(a)係半導體裝置1之XZ剖視圖，圖1(b)係半導體裝置1所具備之半導體晶片21之圖1(a)所示之A-A線上之XY剖視圖。於圖1中，X方向、Y方向、及Z方向為相互正交之方向。
再者，於自沿著半導體晶片21、22之積層方向之Z方向觀察時，半導體裝置1所具備之半導體晶片21、22具有例如大致正方形之形狀，藉此半導體裝置1之YZ剖面可成為與圖1(a)之XZ剖面相同之形狀。
如圖1所示，半導體裝置1例如構成為將1個以上之半導體晶片密封而成之半導體封裝，且具備印刷配線基板10、半導體晶片21、22、樹脂膜30、及接合線40。
印刷配線基板(PCB：Printed Circuit Board)10例如構成為將未圖示之絕緣層與導電層交替地積層複數次而成之多層基板。於印刷配線基板10之兩面配置有未圖示之電極等。
絕緣層例如由含浸硬化前之環氧樹脂等熱硬化性樹脂之碳纖維、玻璃纖維、或芳香族聚醯胺纖維等構成。導電層及電極例如由銅等金屬構成。印刷配線基板10之一個面之電極與半導體晶片21、22電性連接。印刷配線基板10之另一個面之電極經由母板等而與主機等電性連接。
半導體晶片21、22為將矽基板等單片化而成之小片，於表面具有半導體元件。於半導體晶片22，例如搭載有NAND快閃記憶體等非揮發性記憶體22n作為半導體元件。半導體晶片21例如被單片化為較半導體晶片22小之尺寸，且搭載有記憶體控制器等控制電路21c作為半導體元 件。控制電路控制非揮發性記憶體之電動作。
如此，半導體裝置1亦可構成為包含非揮發性記憶體22n與控制電路21c之SSD(Solid State Drive，固態驅動器)等記憶體系統。
作為第1半導體晶片之半導體晶片21例如將設置有控制電路21c之面朝向印刷配線基板10側，直接配置於印刷配線基板10之一個面上。控制電路21c與印刷配線基板10之表面上之電極例如經由未圖示之球柵陣列(BGA：Ball Grid Array)等而電性連接。亦將半導體晶片21之此種安裝方式稱為覆晶方式。
但是，半導體晶片21之安裝方式亦可為引線接合方式等其他方式。於將半導體晶片21利用引線接合方式安裝於印刷配線基板10之情形時，半導體晶片21將控制電路21c側之面朝向上方而配置於印刷配線基板10，控制電路21c與印刷配線基板10之電極利用接合線等電性連接。於該情形時，接合線較佳為整體密封於以下所記載之樹脂膜30內。
樹脂膜30例如亦被稱為晶粒接合膜(DAF：Die Attach Film)或黏晶膜(DBF：Die Bonding Film)等，由成形為膜狀之熱硬化性之黏接劑等構成。樹脂膜30覆蓋半導體晶片21整體。
作為第2半導體晶片之半導體晶片22，將設置有非揮發性記憶體22n之面朝向與印刷配線基板10相反側，即朝向上方，而貼附於樹脂膜30上。
半導體晶片22例如利用引線接合方式安裝於印刷配線基板10，半導體晶片22之非揮發性記憶體22n利用接合線40而與印刷配線基板10上表面之電極電性連接。
如此，於包含複數個半導體晶片21、22之半導體裝置1 中，將一個半導體晶片22利用樹脂膜30貼附於印刷配線基板10上、將另一個半導體晶片21填埋於樹脂膜30內之安裝方式亦稱為FOD(Film Over Die，晶片包裹膜)安裝。
半導體晶片22具有較半導體晶片21大之晶片面積，於自半導體晶片21、22之積層方向觀察時，半導體晶片21及覆蓋半導體晶片21之樹脂膜30不自半導體晶片22之底面突出，整體落於半導體晶片22底面之內側區域內。
更詳細而言，於自半導體裝置1之剖面觀察時，樹脂膜30之厚度方向之側面例如具有朝向半導體晶片22底面下方之內側區域凹陷之凹部31。此時，凹部31之凹陷量例如於矩形狀之半導體晶片22之4個緣部各自之中央附近成為最大。
再者，圖1(b)之XY剖視圖表示了朝向遠離印刷配線基板10之方向觀察圖1(a)之A-A線上之剖面時之剖面。又，圖1(b)中，於分別沿著半導體晶片22之4個緣部之樹脂膜30側面，由虛線表示了凹陷量最大之部分之凹部31。換言之，於圖1(b)中由虛線所示之輪廓與於圖1(a)中於B-B線切斷之樹脂膜30之外形對應。
圖1(a)之B-B線剖面中之樹脂膜30具有凹部31，相對於此，如圖1(b)所示，樹脂膜30之與半導體晶片22底面之黏接面擴散於半導體晶片22之底面整體。即，樹脂膜30不自半導體晶片22突出，而覆蓋半導體晶片22之底面整體。
但是，樹脂膜30之與半導體晶片22底面之黏接面亦可為於不自半導體晶片22突出之範圍內，將樹脂膜30側面之具有凹部31之部分之XY剖面形狀放大之相似形。或者，樹脂膜30亦可自半導體晶片22之底 面一部分突出，一部分沿著半導體晶片22之側面攀爬。
藉由具有如以上所述之形狀，而使樹脂膜30之體積例如能夠由以下之式表示。
Vd1<Td×An...(1)
Vd1：樹脂膜30之體積
Td：樹脂膜30之厚度
An：半導體晶片22之底面之面積
換言之，樹脂膜30之體積例如能夠較將樹脂膜30之厚度與半導體晶片22之底面之面積相乘之值僅小樹脂膜30所具有之凹部31之凹陷量。
又，於自半導體晶片22之上方觀察時，樹脂膜30之與配線基板10之黏接面亦可全部落於半導體晶片22之內側。樹脂膜30之與印刷配線基板10之黏接面亦可為將樹脂膜30側面之具有凹部31之部分之XY剖面形狀放大之相似形。於自半導體晶片22之上方觀察時，樹脂膜30之與配線基板10之黏接面亦可自半導體晶片22一部分突出。
(半導體裝置之製造方法)
接下來，使用圖2及圖3，對實施方式1之半導體裝置1之製造方法進行說明。圖2及圖3係將實施方式1之半導體裝置1之製造方法之順序之一部分依次例示之沿著X方向或Y方向之剖視圖。
如圖2(a)所示，將形成有非揮發性記憶體22n且單片化之複數個半導體晶片22排列於X方向及Y方向上且貼附於切割保護膠帶DT1。
此時，將設置有非揮發性記憶體22n之面朝向切割保護膠帶DT1側，貼附半導體晶片22。又，於複數個半導體晶片22之相互之交界 部分22g中，鄰接之半導體晶片22於X方向或Y方向上空開特定間隔而排列。
如圖2(b)所示，於複數個半導體晶片22之上表面，即與非揮發性記憶體22n為相反側之面上，貼附樹脂膜30。樹脂膜30跨及複數個半導體晶片22且包含相互之交界部分22g於內，以覆蓋該等半導體晶片22整體之方式貼附。此時，樹脂膜30成為硬化前之具有黏接性之狀態，且為暫時固定於複數個半導體晶片22之狀態。
如圖2(c)所示，將較複數個半導體晶片22間之間隔寬幅之切割機DS自與切割保護膠帶DT1相反之一側壓抵於位於半導體晶片22之交界部分22g之樹脂膜30，將與半導體晶片22之交界部分22g重疊之位置之樹脂膜30分別利用切割機DS於X方向及Y方向上以特定深度切割。
藉此，於樹脂膜30，於與半導體晶片22之交界部分22g重疊之位置，形成沿著X方向及Y方向延伸之複數個切口32。
作為複數個第1切口之切口32分別具有較複數個半導體晶片22間之間隔寬之寬度及特定之深度，且不於厚度方向上貫通樹脂膜30。因此，為於切口32之底部殘留樹脂膜30之薄膜之狀態。
再者，樹脂膜30之複數個切口32亦可並非利用切割機DS形成，而是例如藉由照射雷射光等來形成。於該情形時，例如亦調整雷射光之焦點深度，以使樹脂膜30不完全切開。
如圖2(d)所示，將殘留於複數個切口32底部之樹脂膜30之薄膜例如利用雷射光LS等分別切斷。此時，使雷射光LS之照射寬度例如為與複數個半導體晶片22間之間隔大致相等之寬度。又，於將樹脂膜30切斷時，以不切至切割保護膠帶DT1之方式，例如調整雷射光LS之焦點 深度。或者，雷射光LS之照射寬度亦可較複數個半導體晶片22間之間隔稍微寬。
藉此，於樹脂膜30，於切口32之底部且與半導體晶片22之交界部分22g重疊之位置，形成沿著X方向及Y方向延伸之複數個切口33。
作為複數個第2切口之切口33分別具有與複數個半導體晶片22間之間隔大致相等之寬度，且貫通樹脂膜30。藉此，針對複數個半導體晶片22之每一個切斷樹脂膜30。
如圖3(a)所示，將如上所述被加工之樹脂膜30及半導體晶片22切換載置於另一切割保護膠帶DT2。
即，使貼附於切割保護膠帶DT1之樹脂膜30及半導體晶片22以將樹脂膜30側朝向切割保護膠帶DT2之狀態，與切割保護膠帶DT2對向。
如圖3(b)所示，使樹脂膜30與切割保護膠帶DT2貼合，將保持貼附於切割保護膠帶DT1之狀態之樹脂膜30及半導體晶片22貼附於切割保護膠帶DT2。此時，樹脂膜30與切割保護膠帶DT2之黏接亦為暫時固定之狀態。
如圖3(c)所示，將貼附於半導體晶片22之切割保護膠帶DT1剝離，將切換載置於切割保護膠帶DT2上之複數個半導體晶片22利用拾取器等拾取後安裝於印刷配線基板10。
將預先形成有控制電路21c且單片化之半導體晶片21，利用覆晶方式等安裝於印刷配線基板10。而且，於自半導體晶片21、22之積層方向觀察時，於印刷配線基板10之與半導體晶片21重疊之位置，將 半導體晶片22以樹脂膜30側朝向半導體晶片21之方式進行配置。此時，亦為樹脂膜30暫時固定於半導體晶片21之狀態。
然後，於印刷配線基板10之半導體晶片21上，以使樹脂膜30朝下且配置有半導體晶片21之狀態，將樹脂膜30加熱。如上所述，樹脂膜30例如使用熱硬化性之黏接劑。因此，樹脂膜30暫時利用熱軟化後牢固地貼附於半導體晶片21、22，且維持牢固之黏接狀態而硬化。
又，樹脂膜30暫時利用熱軟化後，不僅密接於半導體晶片21之上表面還密接於側面，成為半導體晶片21整體由樹脂膜30覆蓋之狀態。此時，樹脂膜30側面之切口32之原本為直線之剖面形狀因軟化而改變形狀，樹脂膜30例如成為上述圖1所示之側面具有凹部31之形狀。
此種凹部31形成於側面之原因例如係由於軟化之樹脂膜30之表面張力等。又，如上述圖1(b)所示，樹脂膜30側面之凹部31例如於半導體晶片22之4個緣部各自之中央附近成為最大之凹陷量之原因亦係由於軟化之樹脂膜30之表面張力等。
如此，利用樹脂膜30之表面張力等，凹部31會於樹脂膜30之厚度方向中央部、及沿著半導體晶片22之緣部之寬度方向中央部分，具有最大之凹陷量。另一方面，於與半導體晶片22之底面之黏接面中，殘留於切口32底部之樹脂膜30之薄膜直接殘留，例如維持覆蓋半導體晶片22之底面整體之狀態。
但是，例如殘留於切口32底部之樹脂膜30之薄膜部分亦有時會隨著於樹脂膜30側面形成凹部31，而向半導體晶片22之內側區域後退。
於該情形時，如上所述，於半導體晶片22之底面中，樹脂 膜30之黏接面之形狀亦可成為樹脂膜30側面之凹部31之形狀之相似形。即便於該情形時，於熱硬化前覆蓋半導體晶片22之底面整體之樹脂膜30之成分等某些痕跡亦可殘留於半導體晶片22底面。
然後，將半導體晶片22與印刷配線基板10之電極利用接合線40連接，將半導體晶片22安裝於印刷配線基板10。
根據以上內容，製造實施方式1之半導體裝置1。
(比較例)
接下來，使用圖4，對比較例之半導體裝置進行說明。圖4係表示比較例之半導體裝置之製造方法例及構成例之圖。
如圖4(a)所示，於比較例之半導體裝置之製造步驟中，例如於切割保護膠帶DTx貼附樹脂膜930，於樹脂膜930之上表面，貼附單片化前之矽基板等基板922w。
於基板922w之表面，例如已經形成非揮發性記憶體922n。基板922w使設置有非揮發性記憶體922n之一側之面朝向上方貼附於樹脂膜930。
又，將貼附於切割保護膠帶DTx之樹脂膜930及基板922利用特定寬度之切割機DSx切斷而單片化。
如圖4(b)所示，成為於利用切割機DSx之單片化後，於切割保護膠帶DTx上，配置有複數個半導體晶片922與針對該等半導體晶片922之每一個而切斷之樹脂膜930之狀態。
此時，於自半導體晶片922與樹脂膜930之積層方向觀察時，各個樹脂膜930具有與對應之半導體晶片922之晶片面積大致相等之面積。又，樹脂膜930於自半導體晶片922與樹脂膜930之積層方向觀察時 與半導體晶片922之緣部大致一致之位置，具有剖面形狀大致呈直線之側面。
然後，將如上所述加工之樹脂膜930及半導體晶片922配置於具有控制電路921c且已經安裝於印刷配線基板910之半導體晶片921上，將半導體晶片922安裝於印刷配線基板910。
如圖4(c)所示，有時經過上述製造步驟之半導體裝置具有自半導體晶片922之底面突出之樹脂膜930。樹脂膜930具有向半導體晶片922之外側鼓出之凸部935。於樹脂膜930之側面形成此種凸部935例如係因為於使樹脂膜930熱硬化時，軟化之樹脂膜30以半導體晶片921之體積量向外側擠出，並且對樹脂膜930作用表面張力。
於此種情形時，有時由於自半導體晶片922突出之樹脂膜930，而阻礙接合線940與半導體晶片922及印刷配線基板910之接合，導致比較例之半導體裝置之良率降低。
又，於如上所述之情形時，將半導體晶片922與印刷配線基板910連接之接合線940避開具有凸部935之樹脂膜930，而於更遠離半導體晶片922之位置連接於印刷配線基板910。
藉此，有時導致印刷配線基板910中之半導體晶片921、922之安裝區域整體擴散。即，必須於印刷配線基板910上更廣泛地確保包含接合線940於內之實質性之安裝面積。又，藉由更遠離半導體晶片922地連接，而有時導致比較例之半導體裝置之特性惡化，如接合線940之全長延伸、非揮發性記憶體922n之動作速度降低等。
根據實施方式1之半導體裝置1，於自半導體晶片21、22之積層方向觀察時，樹脂膜30整體落於半導體晶片22之底面之內側區域 內。此種半導體裝置1例如藉由於位於複數個半導體晶片22各自之交界部分22g之樹脂膜30，形成具有較複數個半導體晶片22間之特定間隔更寬之寬度及特定之深度之切口32而獲得。
藉此，能夠抑制接合線40與半導體晶片22及印刷配線基板10之接合不良，能夠提高半導體裝置1之良率。
又，於將接合線40連接於印刷配線基板10，能夠更加連接於半導體晶片22之附近，能夠縮小印刷配線基板10中之半導體晶片21、22之實質性之安裝面積。因此，能夠提高印刷配線基板10中之半導體晶片21、22等之積體度。又，接合線40之全長縮短，能夠提高非揮發性記憶體22n之動作速度，提高半導體裝置1之特性。
根據實施方式1之半導體裝置1之製造方法，於樹脂膜30形成具有較複數個半導體晶片22間之特定間隔寬之寬度及特定之深度之切口32，於殘留於切口32底部之樹脂膜30，形成寬度與複數個半導體晶片22間之特定間隔實質上相等之切口33而將樹脂膜30於厚度方向上切斷。
如此，於形成切口32時並非一舉將樹脂膜30切斷，而是將樹脂膜30分2個階段切斷，故而於形成切口32時，能夠抑制半導體晶片22之損傷。
根據實施方式1之半導體裝置1之製造方法，於形成切口32時使用切割機DS。藉此，能夠迅速地形成跨及複數個半導體晶片22之複數個長切口32。
根據實施方式1之半導體裝置1之製造方法，於形成切口33時使用雷射光LS。藉此，例如能夠以較切割機DS等更高之精度來加工樹脂膜30，能夠將樹脂膜30切斷為不自各個半導體晶片22突出，而與半導 體晶片22之底面大致相等之尺寸。又，於將樹脂膜30切斷時，能夠抑制半導體晶片22之損傷。
根據實施方式1之半導體裝置1之製造方法，於與切割保護膠帶DT1不同之另一切割保護膠帶DT2，貼附具有切口32、33之樹脂膜30，使半導體晶片22自切割保護膠帶DT1切換載置於另一切割保護膠帶DT2。藉此，於將半導體晶片22安裝於印刷配線基板10時，能夠使用拾取器等，半導體晶片22之處理變得容易，又，能夠有效率地向印刷配線基板10進行安裝。
(變化例1)
接下來，使用圖5，對實施方式1之變化例1之半導體裝置1a進行說明。變化例1之半導體裝置1a於自沿著半導體晶片121、122之積層方向之Z方向觀察時半導體晶片121、122具有長方形之形狀這一方面與上述實施方式1不同。
圖5係表示實施方式1之變化例1之半導體裝置1a之構成之一例之圖。圖5(a)係半導體裝置1a之YZ剖視圖，圖5(b)係半導體裝置1a之XZ剖視圖，圖5(c)係半導體裝置1a之圖5(a)所示之A-A線上之XY剖視圖。再者，於圖5(c)中，模仿上述實施方式1之圖1，由虛線表示圖5(a)之B-B線剖面中之樹脂膜130之外徑。
又，有時對與上述實施方式1相同之構成標註相同之符號，而省略其說明。
如圖5所示，變化例1之半導體裝置1a具備半導體晶片121、122來代替實施方式1之半導體晶片21、22。實施方式1之半導體晶片21、22於自Z方向觀察時具有大致正方形之形狀，相對於此，變化例1 之半導體晶片121、122於自Z方向觀察時例如具有長方形之形狀。
作為第2半導體晶片之半導體晶片122例如於一個面具有非揮發性記憶體122n，且具有沿著Y方向之作為第1緣部之緣部122y、及沿著X方向且較沿著Y方向之緣部122y長之作為第2緣部之緣部122x。即，緣部122y相當於長方形之半導體晶片122之短邊，緣部122x相當於長邊。
作為第2半導體晶片之半導體晶片121例如於一個面具有控制電路121c，且具有沿著Y方向之緣部121y、及沿著X方向且較沿著Y方向之緣部121y長之緣部121x。即，緣部121y相當於長方形之半導體晶片121之短邊，緣部121x相當於長邊。
如此，若所安裝之半導體晶片121、122具有長方形，則覆蓋半導體晶片121且於上表面貼附著半導體晶片122之樹脂膜130之形狀有時與上述實施方式1之樹脂膜30不同。
具體而言，例如有時沿著作為半導體晶片122之長邊之緣部122x之樹脂膜130側面之作為第2凹部之凹部131x之凹陷量大於沿著作為半導體晶片122之短邊之緣部122y之樹脂膜130側面之作為第1凹部之凹部131y之凹陷量。
其原因在於，於沿著半導體晶片122之長邊且具有更大之表面積之樹脂膜130之側面所受到之表面張力之影響大於沿著半導體晶片122之短邊且具有相對較小之表面積之樹脂膜130側面所受到之表面張力之影響。
(變化例2)
接下來，使用圖6，對實施方式1之變化例2之半導體裝置進行說明。於變化例2之半導體裝置中，於其製造步驟中，使對於樹脂膜230之切口 量於X方向與Y方向變更這一方面與上述變化例1不同。
圖6係將實施方式1之變化例2之半導體裝置之製造方法之順序之一部分依次例示之XY剖視圖。再者，於圖6中，有時對與上述變化例1相同之構成標註相同之符號，而省略其說明。
圖6(a)係靠近經過相當於上述圖2之製造步驟之後之半導體晶片121之下表面之位置上之半導體晶片21、22間之XY剖視圖。
如圖6(a)所示，於樹脂膜230，形成有沿著半導體晶片122之長邊延伸之切口233x、及沿著半導體晶片122之短邊延伸之切口233y。該等切口233x、233y具有分別不同之寬度。
切口233x之沿著Y方向之方向之寬度較切口233y之沿著X方向之方向之寬度寬。關於此種切口233x、233y，例如於形成切口233x時使用較厚之切割機來形成，於形成切口233y時使用較薄之切割機來形成。
即，於位於在貼附於切割保護膠帶上之複數個半導體晶片122之短邊之緣部122y側相互鄰接之交界部分之樹脂膜230，形成具有較複數個半導體晶片122間之間隔寬之寬度之切口。該切口為於針對各個半導體晶片122之每一個切斷樹脂膜230之後，成為切口233y之部分。
又，於位於在貼附於切割保護膠帶上之複數個半導體晶片122之長邊之緣部122x側相互鄰接之交界部分之樹脂膜230，形成具有較半導體晶片122之短邊側之上述切口之寬度寬之寬度之切口。該切口為於針對各個半導體晶片122之每一個切斷樹脂膜230之後，成為切口233x之部分。
再者，於寬度分別不同之2種切口處，樹脂膜230之厚度方 向上之深度可大致相等。
圖6(b)係將如上所述被加工之樹脂膜230及半導體晶片122配置於印刷配線基板，且使樹脂膜230熱硬化之後之XY剖視圖。圖6(b)中由實線表示之剖面相當於上述變化例1之圖5(c)中由實線表示之剖面，圖6(b)中由虛線表示之剖面相當於上述變化例1之圖5(c)中由虛線表示之剖面。
如圖6(b)所示，藉由熱硬化，使樹脂膜230成為於側面具有凹部231x、231y之形狀。凹部231x形成於在沿著半導體晶片122之長邊之方向延伸之樹脂膜230之側面。凹部231y形成於在沿著半導體晶片122之短邊之方向延伸之樹脂膜230之側面。
又，凹部231x、231y於相當於半導體晶片122之長邊及短邊各自之緣部之中央附近具有最大之凹陷量。此時，最大之凹陷量於凹部231x與凹部231y大致相等。即，凹部231x之Y方向上之凹陷量與凹部231y之X方向上之凹陷量大致相等。其原因在於，於樹脂膜230形成寬度分別不同之切口233x、233y。
於使樹脂膜230熱硬化時，於軟化後之樹脂膜230中，沿著半導體晶片122之短邊，僅對表面積較小之樹脂膜230之側面作用較小之表面張力。
然而，藉由使切口233y之寬度變小，使自沿著半導體晶片122之短邊之樹脂膜230之側面到填埋於樹脂膜230之半導體晶片121之緣部為止之距離變長。藉此，能減小半導體晶片121將樹脂膜230之一部分向X方向外側擠出之影響。
因此，結果，凹部231y之凹陷量例如較上述變化例1之凹 部131y之凹陷量大。
於使樹脂膜230熱硬化時，於軟化後之樹脂膜230中，沿著半導體晶片122之長邊，較大之表面張力作用於表面積較大之樹脂膜230之側面。
然而，藉由使切口233x之寬度變大，使自沿著半導體晶片122之長邊之樹脂膜230之側面到填埋於樹脂膜230之半導體晶片121之緣部為止之距離變短。藉此，能增大半導體晶片121將樹脂膜230之一部分向Y方向外側擠出之影響。
因此，結果，凹部231x之凹陷量例如較上述變化例1之凹部131x之凹陷量小。
根據變化例2之半導體裝置之製造方法，於樹脂膜230，形成具有較複數個半導體晶片122間之特定間隔寬之寬度且之後成為切口233y之切口，形成具有較上述切口之寬度寬之寬度且之後成為切口233x之切口。
藉此，能夠減少熱硬化後之樹脂膜230所具有之凹部231x、231y之最大凹陷量之差。因此，能夠更確實地抑制樹脂膜230自半導體晶片122突出。
根據變化例2之半導體裝置之製造方法，另外發揮與上述實施方式1之半導體裝置1及其製造方法相同之效果。
再者，於上述變化例2中，半導體晶片121、122之任一者都具有長方形之形狀。然而，變化例2之構成亦能夠應用於半導體晶片之上述以外之組合。即，於樹脂膜上之半導體晶片、及填埋於樹脂膜中之半導體晶片之至少任一者具有長方形之形狀之情形時，能夠於X方向與Y方 向適當變更樹脂膜之切口量。
(變化例3)
即便於使用與上述實施方式1之半導體裝置1大致相同之構成材，藉由與上述實施方式1之半導體裝置1大致相同之製造方法來製造之情形時，半導體裝置所具有之樹脂膜之形狀亦可有各種不同。
樹脂膜之形狀有時因各自之半導體晶片之尺寸、印刷配線基板之表面性狀、樹脂膜之使用量、加熱溫度、及加熱時間、以及製造時之溫濕度等各種因素而變化。圖7表示與上述實施方式1不同之形狀之樹脂膜330之一例。
圖7係表示實施方式1之變化例3之半導體裝置1b之構成之一例之XZ剖視圖。於圖7中，有時對與上述實施方式1相同之構成標註相同之符號，而省略其說明。
再者，半導體晶片21、22於自沿著Z方向之Z方向觀察時例如具有大致正方形之形狀，藉此半導體裝置1b之YZ剖面可成為與圖7所示之XZ剖面相同之形狀。
如圖7所示，半導體裝置1b所具備之樹脂膜330之各個側面具有凹部331與凸部335。
樹脂膜330之凹部331例如位於半導體晶片22之底面正下方，於自半導體裝置1b之剖面觀察時，具有朝向半導體晶片22底面下方之內側區域凹陷之形狀。
樹脂膜330之凸部335位於凹部331下方之配置半導體晶片21之高度。凸部335於自半導體裝置1b之剖面觀察時，具有於不自半導體晶片22突出之範圍內朝向半導體晶片22之外側區域突出之形狀。
如上所述之樹脂膜330之形狀例如會於半導體晶片21對樹脂膜330之排斥量較多之情形時、半導體晶片21對樹脂膜330之排斥力較強之情形時等產生。
[實施方式2]
以下，參照圖式對實施方式2詳細地進行說明。於實施方式2之半導體裝置中，於樹脂膜之填埋半導體晶片之位置設置凹部這一方面與上述實施方式1不同。再者，以下，有時對與上述實施方式1相同之構成標註相同之符號，而省略其說明。
(半導體裝置之構成例)
圖8係表示實施方式2之半導體裝置2之構成之一例之XZ剖視圖。再者，半導體晶片21、22於自沿著Z方向之Z方向觀察時例如具有大致正方形之形狀，藉此半導體裝置2之YZ剖面可成為與圖8所示之XZ剖面相同之形狀。
如圖8所示，半導體裝置2所具備之樹脂膜430之各個側面具有凹部431與凸部435。
樹脂膜430之凹部431例如位於半導體晶片22之底面正下方，於自半導體裝置2之剖面觀察時，具有朝向半導體晶片22底面下方之內側區域凹陷之形狀。
樹脂膜430之凸部435位於凹部431下方之配置半導體晶片21之高度。凸部435於自半導體裝置2之剖面觀察時，具有於不自半導體晶片22突出之範圍內朝向半導體晶片22之外側區域突出之形狀。
但是，凸部435之突出量較上述實施方式1之變化例3之樹脂膜330中之凸部335所具有之突出量小。
或者，無論圖8之例子如何，半導體裝置2之樹脂膜430之側面都不存在凸部435，例如亦可具有如上述實施方式1之圖1所示之形狀。
於實施方式2之半導體裝置2中，如上述變化例3般，即便於半導體晶片21對樹脂膜330之排斥力更強地起作用之情形時，亦藉由使用下述製造方法來減少樹脂膜430之凸部435之突出量。
再者，半導體裝置2所具備之樹脂膜430之體積例如能夠由以下之式表示。
Vd2=Td×An-Vc±α...(2)
Vd2：樹脂膜430之體積
Td：樹脂膜430之厚度
An：半導體晶片22之底面之面積
Vc：半導體晶片21之體積
±α：相對於半導體晶片21之體積之誤差範圍
如此，樹脂膜430之體積例如於誤差範圍±α內，與由式[Td×An-Vc]求出之體積相等。
(半導體裝置之製造方法)
接下來，使用圖9，對實施方式2之半導體裝置2之製造方法進行說明。圖9係將實施方式2之半導體裝置2之製造方法之順序之一部分依次例示之沿著X方向或Y方向之剖視圖。
於實施方式2之半導體裝置2之製造方法中，例如亦與上述實施方式1相同，實施圖2所示之處理。圖9(a)表示經過上述圖2之處理之後之情況。
如圖9(a)所示，於樹脂膜430形成沿著X方向及Y方向延伸之複數個切口32、33，針對複數個半導體晶片22之每一個切斷樹脂膜430。
於如此被加工之各個樹脂膜430中，於自Z方向觀察時與半導體晶片22重疊之位置且於之後供半導體晶片21填埋之位置，例如照射雷射光LS2而形成凹部436。
較佳為，凹部436例如具有較半導體晶片21之晶片面積大出若干之面積，且具有較半導體晶片21之厚度淺上若干之深度，且整體具有與半導體晶片21之體積大致相等之容量。
為了使凹部436形成為所期望之深度，例如可調整雷射光LS2之焦點深度。又，作為雷射光LS2，例如較佳為使用相對性大口徑之雷射光。藉此，能夠迅速地進行凹部436之加工。
再者，凹部436與切口32、33亦可利用與上述不同之順序形成。例如，亦可於形成切口32之前形成凹部436。又，例如，亦可於形成切口32之後且形成切口33之前形成凹部436。
如圖9(b)所示，將半導體晶片22及樹脂膜430切換載置於另一切割保護膠帶DT2。
如圖9(c)所示，利用拾取器等拾取切換載置於切割保護膠帶DT2上之複數個半導體晶片22，並配置於安裝於印刷配線基板10之半導體晶片21上。此時，以貼附於半導體晶片22上之樹脂膜430之凹部436與印刷配線基板10上之半導體晶片21於Z方向上重疊之方式，配置半導體晶片22及樹脂膜430。
然後，以於印刷配線基板10之半導體晶片21覆蓋樹脂膜 430之凹部436之狀態，使樹脂膜430熱硬化。樹脂膜430暫時利用熱軟化且牢固地貼附於半導體晶片21、22，且維持牢固之黏接狀態而硬化。
此時，除了表面張力作用於軟化後之樹脂膜430以外，還利用半導體晶片21之排斥力，將樹脂膜430之一部分朝向外側擠出。然而，樹脂膜430例如具有容量與半導體晶片21之體積大致相等之凹部436。因此，此時之樹脂膜430之排斥量例如較上述實施方式1之變化例3之情形時少。
又，於形成容量與半導體晶片21之體積大致相等之凹部436時，如上所述，例如使凹部436之面積較半導體晶片21之晶片面積大。藉此，能夠更加減少包圍半導體晶片21之周圍之樹脂膜430之量，且使半導體晶片21對樹脂膜430之排斥量更加少。
再者，關於由使凹部436之面積變大所致之超出量之容積，如上所述藉由使凹部436之深度較半導體晶片21之厚度小來修正。
此處，有時於DAF或DBF等樹脂膜中添加玻璃珠等填料。於此種情形時，例如於上述實施方式1之變化例3之樹脂膜330、與實施方式2之樹脂膜430中，該等樹脂膜330、430中所包含之填料之分佈可能不同。其原因在於，認為於設有凹部436之情形時與未設凹部436之情形時，被半導體晶片21擠出時之樹脂膜330、430之流動狀態存在差異。
如上所述，藉由於樹脂膜430設置凹部436，而使熱硬化後之樹脂膜430中凸部435之突出量例如較上述實施方式1之變化例3之凸部335少。又，熱硬化後之樹脂膜430會具有由上述式(2)表示之體積。
再者，於上述式(2)中，誤差範圍±α可包含凹部436之加工公差、由樹脂膜430之熱硬化所致之收縮量或膨脹量等。
根據以上內容，製造實施方式2之半導體裝置2。
(概括)
根據實施方式2之半導體裝置2之製造方法，於貼附於半導體晶片22之樹脂膜430，形成具有特定之深度之凹部436，以於自半導體晶片21、22之積層方向觀察時，印刷配線基板10之面上之半導體晶片21與樹脂膜430之凹部436重疊之方式，於印刷配線基板10之半導體晶片21上貼附樹脂膜430。
藉此，例如能夠較上述實施方式1之變化例3之凸部335更加減少樹脂膜430之凸部435之突出量。因此，能夠更確實地抑制樹脂膜430自半導體晶片22突出。
根據實施方式2之半導體裝置2之製造方法，凹部436於自半導體晶片21、22之積層方向觀察時，具有較半導體晶片21之晶片面積大之面積。藉此，能夠減少包圍半導體晶片21之周圍之樹脂膜430之量，且減少半導體晶片21對樹脂膜430之排斥量。
根據實施方式2之半導體裝置2之製造方法，凹部436具有較半導體晶片21之厚度短之深度。藉此，能夠修正因凹部436之面積較半導體晶片21之晶片面積大所致之凹部436之超出量之容積，能夠使凹部436之容積與半導體晶片21之體積大致相等。
根據實施方式2之半導體裝置2之製造方法，凹部436具有於特定之誤差範圍內與半導體晶片21之體積相等之容積。藉此，能夠將半導體晶片21對樹脂膜430之排斥量抑制為大致為零，並且能夠充分確保樹脂膜430之量，自而更確實地覆蓋半導體晶片21。
根據實施方式2之半導體裝置2之製造方法，另外發揮與上 述實施方式1之半導體裝置1及其製造方法相同之效果。
再者，於上述實施方式1、2及變化例1~3中，半導體裝置具備分別搭載有非揮發性記憶體與控制電路之複數個半導體晶片。然而，半導體裝置所具備之半導體晶片之組合並不限定於此。
例如，半導體裝置亦可具備分別搭載有邏輯電路及附隨於邏輯電路之半導體電路等、且晶片面積分別不同之複數個半導體晶片。關於此種半導體裝置，亦能夠應用上述實施方式1、2及變化例1~3之構成。
又，半導體裝置無論為記憶體類的還是邏輯類的，貼附於樹脂膜上之半導體晶片與填埋於樹脂膜內之半導體晶片之個數之組合均任意為1對1或1對多等。
又，於上述實施方式1、2及變化例1~3中，半導體裝置具備印刷配線基板10。然而，供半導體晶片安裝之配線基板並不限定於印刷配線基板。半導體裝置之配線基板例如亦可為形成有配線之矽基板或玻璃基板、或者係具有再配線層之各種基板等。
已對本發明之幾個實施方式進行了說明，但該等實施方式係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施方式能夠以其他各種方式實施，於不脫離發明之主旨之範圍內，能夠進行各種省略、置換、變更。該等實施方式或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍中所記載之發明及與其等價之範圍內。
[相關申請案]
本申請案享有以日本專利申請案2022-024647號(申請日：2022年2月21日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案 而包含基礎申請案之所有內容。
1:半導體裝置 10:印刷配線基板 21,22:半導體晶片 21c:控制電路 22n:非揮發性記憶體 30:樹脂膜 31:凹部 40:接合線

Claims (9)

  1. 一種半導體裝置，其具備：配線基板；第1半導體晶片，其設置於上述配線基板之面上；樹脂膜，其覆蓋上述第1半導體晶片；及第2半導體晶片，其晶片面積較上述第1半導體晶片大，貼附於上述樹脂膜之上表面而安裝於上述配線基板；於自上述第1及第2半導體晶片之積層方向觀察時，上述樹脂膜整體落於上述第2半導體晶片之底面之內側區域內；於自與上述積層方向交叉之第1方向觀察時，上述樹脂膜於側面具有朝向上述內側區域凹陷之凹部。
  2. 如請求項1之半導體裝置，其中上述凹部之凹陷量於上述第2半導體晶片之緣部之中央附近最大。
  3. 如請求項1或2之半導體裝置，其中上述第2半導體晶片具有：第1緣部，其沿著上述第1方向；及第2緣部，其沿著與上述積層方向及上述第1方向交叉之第2方向，且較上述第1緣部長；上述樹脂膜，於沿著上述第1緣部之側面具有第1凹部， 於沿著上述第1緣部之側面，具有朝向上述內側區域較上述第1凹部更大地凹陷之第2凹部。
  4. 一種半導體裝置，其具備：配線基板；第1半導體晶片，其設置於上述配線基板之面上；樹脂膜，其覆蓋上述第1半導體晶片；及第2半導體晶片，其晶片面積較上述第1半導體晶片大，貼附於上述樹脂膜之上表面而安裝於上述配線基板；於自上述第1及第2半導體晶片之積層方向觀察時，上述樹脂膜整體落於上述第2半導體晶片之底面之內側區域內；上述樹脂膜之體積於將上述樹脂膜之厚度設為Td、將上述第2半導體晶片之上述底面之面積設為An之情形時，較由式[Td×An]求出之體積小。
  5. 如請求項4之半導體裝置，其中上述樹脂膜之體積於進而將上述第1半導體晶片之體積設為Vc之情形時，落於包含由式[Td×An-Vc]求出之體積之特定範圍內。
  6. 一種半導體裝置之製造方法，其於配線基板之面上設置第1半導體晶片；將具有半導體元件且以晶片面積較上述第1半導體晶片大之方式單片化之複數個第2半導體晶片以具有上述半導體元件之面朝下之方式以特定間隔貼附於切割保護膠帶； 於貼附於上述切割保護膠帶上之上述複數個第2半導體晶片之與上述面為相反側之面上貼附具有黏接性之樹脂膜；於位於上述複數個第2半導體晶片各自之交界部分之上述樹脂膜，形成具有較上述特定間隔寬之第1寬度及第1深度之第1切口；於殘留於上述第1切口底部之上述樹脂膜，將與上述特定間隔實質上相等或者較寬之第2切口形成於自上述第2半導體晶片及上述樹脂膜之積層方向觀察時與上述複數個第2半導體晶片之上述交界部分重疊之位置且將上述樹脂膜於厚度方向上切斷；將具有上述第1及第2切口之上述樹脂膜貼附於上述配線基板之上述第1半導體晶片，於自上述第1及第2半導體晶片之積層方向觀察時與上述配線基板之上述第1半導體晶片重疊之位置，設置上述第2半導體晶片。
  7. 如請求項6之半導體裝置之製造方法，其中進而包含以下步驟，即，於自上述第2半導體晶片及上述樹脂膜之積層方向觀察時與貼附於上述第2半導體晶片之上述樹脂膜之上述第2半導體晶片重疊之位置，形成具有第2深度之凹部，於將上述第2半導體晶片設置於上述配線基板時，以自上述第1及第2半導體晶片之積層方向觀察時上述配線基板之上述面上之上述第1半導體晶片與上述樹脂膜之上述凹部重疊之方式，於上述配線基板之上述第1半導體晶片貼附上述樹脂膜。
  8. 如請求項6之半導體裝置之製造方法，其中上述第2半導體晶片具有： 第1緣部，其沿著與上述積層方向交叉之第1方向；及第2緣部，其沿著與上述積層方向及上述第1方向交叉之第2方向，且較上述第1緣部長；於形成上述第1切口時，於位於上述複數個第2半導體晶片於上述第1緣部側相互鄰接之交界部分之上述樹脂膜，形成具有較上述特定間隔寬之第2寬度及上述第1深度之第3切口，於位於上述複數個第2半導體晶片於上述第2緣部側相互鄰接之交界部分之上述樹脂膜，形成具有較上述第2寬度寬之第3寬度及上述第1深度之第4切口。
  9. 如請求項6之半導體裝置之製造方法，其中於將上述第2半導體晶片安裝於上述配線基板時，使上述樹脂膜熱硬化，利用上述樹脂膜覆蓋上述第1半導體晶片。
TW111128961A 2022-02-21 2022-08-02 半導體裝置及半導體裝置之製造方法 TWI818655B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022024647A JP2023121355A (ja) 2022-02-21 2022-02-21 半導体装置および半導体装置の製造方法
JP2022-024647 2022-02-21

Publications (2)

Publication Number Publication Date
TW202335211A TW202335211A (zh) 2023-09-01
TWI818655B true TWI818655B (zh) 2023-10-11

Family

ID=87574562

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111128961A TWI818655B (zh) 2022-02-21 2022-08-02 半導體裝置及半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US20230268310A1 (zh)
JP (1) JP2023121355A (zh)
CN (1) CN116666368A (zh)
TW (1) TWI818655B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201907534A (zh) * 2017-07-04 2019-02-16 南韓商三星電機股份有限公司 半導體元件與其製造方法
TW201913933A (zh) * 2017-08-28 2019-04-01 日商東芝股份有限公司 半導體裝置、半導體裝置之製造方法及半導體封裝之製造方法
TW202008529A (zh) * 2018-08-03 2020-02-16 日商東芝記憶體股份有限公司 半導體裝置及其製造方法
TW202008538A (zh) * 2018-08-07 2020-02-16 日商東芝記憶體股份有限公司 半導體裝置及其製造方法
TW202125651A (zh) * 2019-09-06 2021-07-01 日商日立化成股份有限公司 半導體裝置的製造方法及夾頭

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201907534A (zh) * 2017-07-04 2019-02-16 南韓商三星電機股份有限公司 半導體元件與其製造方法
TW201913933A (zh) * 2017-08-28 2019-04-01 日商東芝股份有限公司 半導體裝置、半導體裝置之製造方法及半導體封裝之製造方法
TW202008529A (zh) * 2018-08-03 2020-02-16 日商東芝記憶體股份有限公司 半導體裝置及其製造方法
TW202008538A (zh) * 2018-08-07 2020-02-16 日商東芝記憶體股份有限公司 半導體裝置及其製造方法
TW202125651A (zh) * 2019-09-06 2021-07-01 日商日立化成股份有限公司 半導體裝置的製造方法及夾頭

Also Published As

Publication number Publication date
CN116666368A (zh) 2023-08-29
US20230268310A1 (en) 2023-08-24
JP2023121355A (ja) 2023-08-31
TW202335211A (zh) 2023-09-01

Similar Documents

Publication Publication Date Title
US6767767B2 (en) Method of manufacturing a semiconductor device in which a block molding package utilizes air vents in a substrate
US10204882B2 (en) Stacked package module having an exposed heat sink surface from the packaging
US20040043537A1 (en) Method of manufacturing a semiconductor device having a flexible wiring substrate
US20060065421A1 (en) Circuit device and manufacturing method thereof
US11049845B2 (en) Semiconductor device having wires connecting connection pads
US10537018B2 (en) Semiconductor device
US20120286411A1 (en) Semiconductor device and manufacturing method thereof, and semiconductor module using the same
US9443823B2 (en) Semiconductor device including filling material provided in space defined by three semiconductor chips
US20130137217A1 (en) Method of manufacturing semiconductor device
JP2004528729A (ja) 複数の半導体チップ、および配線ボードを有する樹脂パッケージ、ならびにこの樹脂パッケージを射出成形用金型によって製作する方法
CN112242358B (zh) 半导体装置及其制造方法
CN110797334B (zh) 半导体装置及其制造方法
TWI818655B (zh) 半導體裝置及半導體裝置之製造方法
TWI750439B (zh) 半導體裝置及其製造方法
US8198141B2 (en) Intermediate structure of semiconductor device and method of manufacturing the same
US20070013039A1 (en) Package substrate and semiconductor package using the same
CN112490223A (zh) 半导体装置
CN112310006A (zh) 具有承载件、层压体和位于两者间的构件的包封的封装体
US11011505B2 (en) Semiconductor memory and manufacturing method thereof
US20240136306A1 (en) Semiconductor device and method for manufacturing semiconductor device
US20230005823A1 (en) Semiconductor device and a method of manufacturing semiconductor device
US20150333041A1 (en) Semiconductor device and manufacturing method therefor
JP4453009B2 (ja) 半導体装置及びその製造方法
KR20100065787A (ko) 기판, 상기 기판을 사용하는 반도체 패키지 및 상기 기판의제조방법
JP2010109153A (ja) 半導体装置の製造方法