CN110797334A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110797334A
CN110797334A CN201811599371.0A CN201811599371A CN110797334A CN 110797334 A CN110797334 A CN 110797334A CN 201811599371 A CN201811599371 A CN 201811599371A CN 110797334 A CN110797334 A CN 110797334A
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semiconductor chip
region
semiconductor
substrate
chip
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CN110797334B (zh
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松浦永悟
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种能够在不使用间隔芯片的情况下将一半导体芯片配置在另一半导体芯片上方从而缩小封装尺寸的半导体装置及其制造方法。本实施方式的半导体装置具备形成着电极的基板、设置在基板的表面上的第1及第2半导体芯片、将第1半导体芯片与电极连接的导线、粘接层、及树脂层。第2半导体芯片在朝向基板侧的面即背面具有形成着突出部的第1区域及第1区域以外的第2区域，第2区域位于第1半导体芯片或导线的至少一部分的上方。粘接层设置在第1区域与基板之间及第2区域与基板之间。树脂层设置在基板上，且被覆第1及第2半导体芯片。

Description

半导体装置及其制造方法
[相关申请]
本申请享有以日本专利申请2018-146821号(申请日：2018年8月3日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置及其制造方法。
背景技术
存在如存储器芯片及其控制器芯片那样将多个半导体芯片密封在1个封装内的情况。在此情况下，例如存在利用间隔芯片将存储器芯片堆叠并重叠配置在控制器芯片上方的封装构造。此种封装构造能够比将多个半导体芯片单纯地横向并列配置而成的构造进一步缩小封装整体的尺寸。
然而，为了将存储器芯片堆叠而必需间隔芯片，因此成本增高。
另外，在使用厚DAF(Die Attachment Film，芯片粘接膜)代替间隔芯片的情况下，存储器芯片变得容易倾斜。或者也存在存储器芯片本身的形状容易变形的顾虑。如果存储器芯片倾斜或者变形，那么当在存储器芯片上进而积层其它存储器芯片时，所积层的存储器芯片变得容易剥落而难以将接合线连接。另外，存在当DAF被压扁时存储器芯片会与其下方的控制器芯片接触的顾虑。进而，也存在当DAF被压扁时，DAF从存储器芯片的下方向接合垫伸出，之后难以将金属导线与接合垫接合的情况。
发明内容
实施方式提供一种能够在不使用间隔芯片的情况下将一半导体芯片配置在另一半导体芯片上方从而缩小封装尺寸的半导体装置及其制造方法。
本实施方式的半导体装置具备形成着电极的基板、设置在基板的表面上的第1及第2半导体芯片、将第1半导体芯片与电极连接的导线、粘接层、及树脂层。第2半导体芯片在朝向基板侧的面即背面具有形成着突出部的第1区域及第1区域以外的第2区域，第2区域位于第1半导体芯片或导线的至少一部分的上方。粘接层设置在第1区域与基板之间及第2区域与基板之间。树脂层设置在基板上，且被覆第1及第2半导体芯片。
附图说明
图1(A)及(B)是表示第1实施方式的半导体装置的构成例的剖视图及俯视图。
图2(A)、图2(B)、图3(A)、图3(B)、图4(A)、图4(B)、图5(A)、图5(B)、图6(A)、图6(B)是表示第1实施方式的半导体装置的制造方法的一例的图。
图7是表示第1实施方式的变化例1的半导体装置的制造方法的图。
图8(A)、图8(B)、图9(A)、图9(B)是表示依据第1实施方式的变化例2的半导体装置的制造方法的剖视图。
图10是表示第2实施方式的半导体装置的构成例的剖视图。
图11是表示第3实施方式的半导体装置的构成例的剖视图。
图12是表示第4实施方式的半导体装置的构成例的剖视图。
图13(A)及(B)是表示第5实施方式的半导体装置的构成例的剖视图及俯视图。
图14(A)及(B)是表示第5实施方式的半导体装置的制造方法的剖视图。
图15是表示第6实施方式的半导体装置的构成例的剖视图。
图16是表示第7实施方式的半导体装置的构成例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。在以下的实施方式中，上下方向表示把将半导体芯片安装在基板的面设为上方的情况下的相对方向，存在与依据重力加速度的上下方向不同的情况。附图是示意图或概念图，各部分的比率等未必与实物相同。在说明书与附图中，对于关于已经出现过的附图而在上文中说明过的要素相同的要素标注相同的符号，并适当省略详细的说明。
(第1实施方式)
图1(A)及图1(B)是表示第1实施方式的半导体装置1的构成例的剖视图及俯视图。半导体装置1具备树脂基板10、控制器芯片20、存储器芯片30、粘接层40、50、金属导线60、70、及模具树脂80。本实施方式的半导体装置1是面安装型的半导体封装，例如可以是BGA(Ball Grid Array package，球栅阵列封装)、LGA(Land Grid Array Package，焊盘网格阵列封装)等。半导体装置1例如也可以是NAND(Not AND，与非)型闪速存储器等半导体存储装置。
作为基板的树脂基板10例如可以是将多个绝缘层与多个布线层(均未图示)积层并一体化而成的多层布线基板。绝缘层例如使用玻璃环氧树脂、有机高分子材料或陶瓷材料(例如氧化铝(Al2O3))等树脂材料。布线层设置在树脂基板10内，并电连接在接合垫。布线层例如使用铜等低电阻的导电性材料。树脂基板10的平面形状并无特别限定，如图1(B)所示，可以为大致长方形或者大致正方形。
在树脂基板10的表面上设置着接合垫12、14。金属导线60、70接合在接合垫12、14。金属导线60、70例如使用金。
作为第1半导体芯片的控制器芯片20通过粘接层(DAF(Die Attachment Film))40粘接并固定在树脂基板10的表面上。控制器芯片20是控制存储器芯片30的半导体芯片，且在半导体基板的表面设置着构成控制电路的半导体元件(例如晶体管等)。另外，控制器芯片20具有连接在内部的控制电路的接合垫22，接合垫22通过金属导线60与树脂基板10的接合垫12电连接。
作为第2半导体芯片的存储器芯片30通过粘接层(DAF)50粘接并固定在树脂基板10的表面上。存储器芯片30例如是具有NAND型闪速存储器的半导体芯片，在半导体基板的表面上设置着平面型或立体型的存储单元阵列。另外，存储器芯片30具有连接在内部电路的接合垫24，接合垫24通过金属导线70与树脂基板10的接合垫14电连接。由此，存储器芯片30经由金属导线60、70及树脂基板10的内部布线与控制器芯片20电连接，并能够接收控制器芯片20的控制来进行动作。
如图1(A)所示，存储器芯片30的背面具有在第1区域R1突出的突出部31。另外，存储器芯片30的背面具有在第1区域R1以外的背面的第2区域R2凹陷的凹部。在使突出部31粘接在树脂基板10的表面时，第2区域R2的凹部32是以重叠在将控制器芯片20与树脂基板10之间连接的金属导线60的至少一部分的上方的方式存在。此时，凹部32未与控制器芯片20及金属导线60接触。
粘接层50设置在第1区域R1与树脂基板10之间，将突出部31粘接在树脂基板10上。并且，粘接层50也设置在第2区域R2与树脂基板10之间，将凹部32粘接在树脂基板10。另外，位于第2区域R2与树脂基板10之间的粘接层50与金属导线60的一部分及接合垫12接触，并被覆它们。也就是说，从树脂基板10的表面上方观察时，存储器芯片30的第2区域R2与金属导线60的至少一部分重叠。
如此一来，通过在存储器芯片30的背面设置突出部31及凹部32，能够使存储器芯片30不与控制器芯片20及金属导线60接触而是使存储器芯片30的第2区域R2向控制器芯片20侧突出。由此，能够使存储器芯片30重叠在控制器芯片20或金属导线60的上方，从而能够缩小半导体装置1的整体尺寸。
第2区域R2与第1区域R1中的存储器芯片30的厚度差优选大于控制器芯片20的厚度使得即便使第2区域R2向控制器芯片20侧突出，存储器芯片30亦不会与控制器芯片20接触。另外，第2区域R2与第1区域R1中的存储器芯片30的厚度差优选大于金属导线60的高度使得即便使第2区域R2向控制器芯片20侧突出，金属导线60亦不会与控制器芯片20接触。
模具树脂80设置在树脂基板10上，且被覆控制器芯片20、存储器芯片30、金属导线60、70。模具树脂80保护控制器芯片20、存储器芯片30、金属导线60、70免受半导体装置1的外部的损害。
如图1(B)所示，第1区域R1位于第2区域R2的内侧而并未伸出至第2区域R2的外侧。另外，如图1(A)所示，在沿控制器芯片20及存储器芯片30的排列方向切断的截面中，第2区域R2向从存储器芯片30朝向控制器芯片20的第1方向D1及与第1方向D1相反的第2方向D2这两个方向延伸。在此情况下，当粘接层50从第1区域R1伸出时，第2区域R2接受所伸出的粘接层50，从而能够抑制粘接层50向横向扩展。也就是说，在第2区域R2从存储器芯片30的两侧向D1及D2方向延伸的情况下，粘接层50在端部E1的第2区域R2与树脂基板10之间、以及端部E2的第2区域R2与树脂基板10之间被接受。
虽必须在靠近控制器芯片20的端部E1设置第2区域R2，但未必在远离控制器芯片20的端部E2设置第2区域R2。也就是说，第2区域R2未必必须向第2方向D2延伸。在此情况下，也能够使存储器芯片30重叠在金属导线60的上方。另外，从第1区域R1的端部E1向D1方向伸出的粘接层50能够被第2区域R2接受而被覆金属导线60的一部分。
此外，金属导线60是在存储器芯片30的粘接前接合，因此粘接层50可以与接合垫12及金属导线60接触。不如使粘接层50被覆接合垫12及金属导线60，由此能够使粘接层50保护接合垫12及金属导线60。
另一方面，在未在端部E2设置第2区域R2的情况下，存在从第1区域R1的端部E2向D2方向伸出的粘接层50未被接受而向横向扩展的情况。金属导线70是在存储器芯片30的粘接后接合，因此如果在搭载存储器芯片30时粘接层50伸出至接合垫14，那么存在无法使金属导线70接合在接合垫14的顾虑。因此，第2区域R2优选也设置在端部E2。然而，即便粘接层50向横向扩展，但只要不对接合垫14及金属导线70造成影响，那么第2区域R2也可以不设置在端部E2。
另外，如图1(B)所示，在从树脂基板10的上方观察的俯视下，第2区域R2也可以以包围第1区域R1的方式设置在第1区域R1的整个外周。在此情况下，不仅是向D1、D2方向伸出的粘接层50，在背面F2面内向相对于D1、D2方向大致直行方向伸出的粘接层50也能够在第2区域R2与树脂基板10之间被接受。结果，能够抑制粘接层50过度扩展。
在本实施方式中，多个存储器芯片30分开设置在控制器芯片20的两侧。在此情况下，并未在控制器芯片20的正上方设置存储器芯片30，因此在多个存储器芯片30间设置着模具树脂80。由此，存储器芯片30、控制器芯片20及金属导线60、70由模具树脂80保护。金属导线60的一部分与接合垫12由粘接层50保护。
根据本实施方式，存储器芯片30在背面的第1区域R1具有突出部31。在使突出部31粘接在树脂基板10的表面时，存储器芯片30的第2区域R2在不与控制器芯片20接触的情况下配置在金属导线60的至少一部分的上方。在从树脂基板10的表面上方观察的俯视下，第2区域R2与金属导线60的至少一部分重叠。由此，相较于只是将控制器芯片20及存储器芯片30横向并列而成的封装构造，依据本实施方式的封装构造的尺寸减小。
进而，在存储器芯片30的端部E1侧的第2区域R2的下方设置着粘接层50。由此，粘接层50被覆金属导线60的一部分及接合垫12，从而能够保护它们。
另外，能够在端部E2侧的第2区域R2的下方接受粘接层50。由此，在搭载存储器芯片30时，粘接层50不会从存储器芯片30伸出至接合垫14，从而能够抑制接合垫14的污染等。
进而，通过将第2区域R2设置在第1区域R1的整个外周，能够进而有效地抑制粘接层50从存储器芯片30伸出。
接下来，对本实施方式的半导体装置1的制造方法进行说明。
图2(A)～图6(B)是表示第1实施方式的半导体装置1的制造方法的一例的图。此外，以下的半导体芯片的制造方法能够应用于控制器芯片20及存储器芯片30的任一个。
首先，如图2(A)及图2(B)所示，在半导体晶圆100的正面F1上形成半导体元件15。在各半导体芯片间设置切割线DL。此外，图2(B)是图2(A)的一部分的剖视图。
接下来，如图3(A)所示，将保护胶带110贴附在半导体晶圆100的正面F1，如图3(B)所示，通过CMP(Chemical Mechanical Polishing，化学机械研磨)法对半导体晶圆100的背面F2进行研磨。
接下来，如图4(A)所示，利用修剪刀片TB对半导体晶圆100的背面F2的第2区域R2进行切削。由此，形成在背面F2的第1区域R1突出的突出部31及在除此以外的背面F2的第2区域R2凹陷的凹部32。
接下来，如图4(B)所示，将背面F2朝向粘接层50而将半导体晶圆100搭载在具有粘接层50的切割保护胶带120上。进而，如图5(A)所示，通过将半导体晶圆100向切割保护胶带120加压，而使粘接层50嵌入半导体晶圆100的凹部32内。
接下来，如图5(B)所示，使用激光振荡器130对与半导体晶圆100的背面F2的切割线DL对应的部分照射激光。由此，在半导体晶圆100的内部形成改质层LM。
接下来，如图6(A)所示，通过上推部件140将切割保护胶带120从下方往上推，由此将切割保护胶带120拉伸(使之延伸)。由此，切割保护胶带120与半导体晶圆100一起被朝向外方拉伸。此时，如图6(B)所示，半导体晶圆100及粘接层50沿着改质层LM(也就是沿着切割线)被劈开，从而被单片化成多个半导体芯片。
之后，分别拾取半导体芯片(控制器芯片20及/或存储器芯片30)并安装在树脂基板10上。
例如，将控制器芯片20安装在树脂基板10上。此时，如图1所示，粘接层40将控制器芯片20粘接在树脂基板10上。此时，也可以对粘接层40进行加热而将控制器芯片20粘接在树脂基板10上。
接下来，通过金属导线60将控制器芯片20与树脂基板10的接合垫12接合。
接下来，将存储器芯片30安装在树脂基板10上。此时，如图1所示，粘接层50将存储器芯片30粘接在树脂基板10上。也可以对粘接层50进行加热而将存储器芯片30粘接在树脂基板10上。此时，利用粘接层50将存储器芯片30的突出部31粘接在树脂基板10的表面，并且将凹部32配置在金属导线60的上方。
存储器芯片30是以其端部E1突出至金属导线60的上方的方式配置，并与金属导线60的一部分重叠。由此，能够缩小半导体装置1的尺寸。并且，存储器芯片30的端部E1侧的粘接层50能够将金属导线60的一部分及接合垫12掩埋从而保护它们。
在本实施方式中，2个存储器芯片30配置在控制器芯片20的两侧，且在控制器芯片20的两侧，粘接层50保护金属导线60及接合垫12。
接下来，通过模具树脂80将控制器芯片20及存储器芯片30密封。由此，完成图1所示的半导体装置1的封装。
根据本实施方式，在使存储器芯片30的突出部31粘接在树脂基板10的表面时，能够将存储器芯片30的凹部32不与金属导线60接触而配置在其上方。由此，不使用间隔芯片等便能够使存储器芯片30的一部分重叠在控制器芯片20的上方，从而能够缩小封装构造的尺寸。
进而，在存储器芯片30的端部E1侧的第2区域R2的下方设置着粘接层50。由此，粘接层50被覆金属导线60的一部分及接合垫12，从而能够保护它们。
另外，能够在端部E2侧的第2区域R2的下方接受粘接层50。由此，在搭载存储器芯片30时，粘接层50不会伸出至接合垫14，从而能够抑制接合垫14的污染等。
(变化例1)
图7是表示第1实施方式的变化例1的半导体装置1的制造方法的图。在第1实施方式的制造方法中，如图5(A)所示，利用粘接层50填充凹部32后，通过激光切割及延伸来使半导体芯片单片化。
然而，在变化例1中，进行刀片切割代替激光切割及延伸。在刀片切割中，使用图7的切割刀片DB将切割线DL切断。
修剪刀片的宽度(相对于旋转面垂直的方向上的宽度)宽于切割刀片的宽度。因此，凹部32的宽度宽于切割线DL，且宽于利用切割刀片而切出的区域的宽度。由此，即便在单片化后，在存储器芯片30的背面F2也残留着突出部31及凹部32。
(变化例2)
图8(A)～图9(B)是表示依据第1实施方式的变化例2的半导体装置1的制造方法的剖视图。
在第1实施方式中，在进行修剪处理后进行半导体芯片的单片化。相对于此，在变化例2中，在进行半导体芯片的单片化后进行修剪处理。
首先，经过参照图2(A)及图2(B)所说明的步骤，如图8(A)所示，利用切割刀片DB沿着切割线DL切至半导体晶圆100的中途(半切)。
接下来，如图8(B)所示，将保护胶带110贴附在半导体晶圆100的正面F1，如图9(A)所示，通过CMP法对半导体晶圆100的背面F2进行研磨。通过该背面F2的研磨，而将半导体晶圆100单片化成半导体芯片。
之后，如图9(B)所示，利用修剪刀片TB对半导体晶圆100的背面F2的第2区域R2进行切削。由此，形成在背面F2的第1区域R1突出的突出部31及在除此以外的背面F2的第2区域R2凹陷的凹部32。进而，经过参照图4(B)～图5(A)所说明的步骤，形成半导体芯片。在变化例2中，无需图5(B)及图6(A)所示的激光切割及延伸的步骤。
之后，经过与第1实施方式相同的步骤，完成与第1实施方式相同的半导体装置1。即便在如上所述那样进行半导体芯片的单片化后进行修剪处理，也能够形成与第1实施方式相同的半导体装置1。
(第2实施方式)
图10是表示第2实施方式的半导体装置2的构成例的剖视图。在第2实施方式中，控制器芯片20是无需打线接合的倒装芯片。在控制器芯片20为倒装芯片的情况下，将具有半导体元件的表面朝向树脂基板10接合。另一方面，控制器芯片20的背面与存储器芯片30的凹部32对向。因此，即便粘接层50被覆控制器芯片20，粘接层50的应力也不易施加至控制器芯片20的半导体元件。
因此，在第2实施方式中，在存储器芯片30的端部E1侧向D1方向突出的第2区域R2大于第1实施方式的在存储器芯片30的端部E1侧向D1方向突出的第2区域R2。存储器芯片30的凹部32配置在控制器芯片20的上方。随之，粘接层50设置在控制器芯片20上。由此，粘接层50能够保护控制器芯片20的一部分。
第2实施方式的其它构成可以与第1实施方式的构成相同。另外，第2实施方式的制造方法也可以与第1实施方式的制造方法相同。因此，第2实施方式能够获得与第1实施方式相同的效果。
(第3实施方式)
图11是表示第3实施方式的半导体装置3的构成例的剖视图。在第3实施方式中，在存储器芯片30的端部E1、E2，在突出部31与凹部32之间，将级差部33设置在第3区域R3。也就是说，第3实施方式的存储器芯片30的背面F2具有突出部31、级差部33、及凹部32这3段。级差部33及凹部32配置在金属导线60及/或控制器芯片20的上方。
另外，在图11中，粘接层50设置到级差部33为止，也可以设置到凹部32为止。在粘接层50设置到级差部33为止的情况下，粘接层50被覆金属导线60。虽未图示，但在粘接层50设置到凹部32为止的情况下，粘接层50被覆金属导线60及控制器芯片20的一部分。在此情况下，粘接层50能够保护整个金属导线60、金属导线60与接合垫12的接合部、及金属导线60与控制器芯片20的接合部。
即便如第3实施方式那样设置级差部33，也不会失去本实施方式的效果。另外，通过设置级差部33，即便使凹部32向D1方向延长，也能够维持存储器芯片30的机械强度。此外，设置在突出部31与凹部32之间的级差部33的数量并无特别限定。因此，也可以将多个级差部33呈阶梯状设置在突出部31与凹部32之间。
(第4实施方式)
图12是表示第4实施方式的半导体装置4的构成例的剖视图。在第4实施方式中，在存储器芯片30上进而积层其它存储器芯片(第3半导体芯片)35。第4实施方式的其它构成可以与第1实施方式相同。
可以如上所述那样在存储器芯片30上积层存储器芯片35。但是，存储器芯片35的背面不具有突出部31及凹部32而是平坦。另外，积层在存储器芯片30上的存储器芯片35的数量并无特别限定。即便如第4实施方式那样在存储器芯片30上积层其它存储器芯片35，也不会失去本实施方式的效果。
(第5实施方式)
图13(A)及图13(B)是表示第5实施方式的半导体装置5的构成例的剖视图及俯视图。此外，在图13(B)的俯视图中，控制器芯片20仅示出其概略性的位置，并省略与金属导线60等相关的图示。
在第5实施方式中，存储器芯片30在其背面F2具有多个第1区域R1，且在各第1区域R1设置着突出部31。由此，如图1(A)所示，存储器芯片30的背面F2在相对于树脂基板10的表面垂直的截面中形成为大致U形状。存储器芯片30是以横跨控制器芯片20的上方的方式设置，且在控制器芯片20的两侧，突出部31通过粘接层50被粘接在树脂基板10。控制器芯片20配置在2个突出部31间，且在其上方配置着凹部32。凹部32被覆控制器芯片20的表面上方。如上所述，存储器芯片30也可以不左右分离而为一体型芯片。在存储器芯片30为一体型的情况下，存储器芯片30的机械强度及稳定性提高。因此，存储器芯片30的弯曲得到抑制，从而能够增大存储器芯片35的积层数。
半导体装置5只要变更半导体晶圆100的修剪处理的位置，便能够与第1实施方式的半导体装置1同样地形成。例如，在第1实施方式的图4(A)中，第2区域R2的凹部32只要形成在相邻的切割线DL间即可。此外，修剪刀片TB的宽度设为小于各存储器芯片30的宽度。由此，在半导体芯片的中心部形成凹部32，在凹部32的两侧形成2个突出部31。切割线DL与突出部31的中间位置对应。因此，切割后，各半导体芯片形成为在其中心部具有凹部32且在凹部32的两侧具有2个突出部31的大致U形状。关于所述变化例1，也同样地，只要变更半导体晶圆100的修剪处理的位置，便能够制造半导体装置5。
作为半导体装置5的制造方法，也存在以下那样的制造方法。
图14(A)及图14(B)是表示第5实施方式的半导体装置5的制造方法的剖视图。例如，在经过参照图2(A)～图3(A)所说明的步骤后，使用修剪刀片如图14(A)所示那样，在切割线DL间的半导体芯片的中心部形成凹部32。
接下来，使用CMP法对半导体晶圆100的背面F2进行研磨。此时，对背面F2进行研磨直至半导体晶圆100的背面F2的突出部31成为所需高度为止。由此，如图14(B)所示，在凹部32的两侧形成2个突出部31。
之后，经过参照图4(B)～图7所说明的步骤，对半导体晶圆100进行切割。由此，形成如图13(A)所示的存储器芯片30。可以如上所述那样形成凹部32后对背面F2进行研磨。
(第6实施方式)
图15是表示第6实施方式的半导体装置6的构成例的剖视图。在第6实施方式中，在存储器芯片30上进而积层其它存储器芯片(第3半导体芯片)35。第6实施方式的其它构成可以与第5实施方式相同。
可如上所述那样在存储器芯片30上积层其它存储器芯片35。但是，存储器芯片35的背面不具有突出部31及凹部32而是平坦。另外，积层在存储器芯片30上的存储器芯片35的数量并无特别限定。即便如第6实施方式那样在存储器芯片30上积层其它存储器芯片35，也不会失去本实施方式的效果。
(第7实施方式)
图16是表示第7实施方式的半导体装置7的构成例的剖视图。在第7实施方式中，在整个存储器芯片30的背面F2与树脂基板10之间设置着粘接层50。也就是说，粘接层50不仅设置在突出部31与树脂基板10之间，还设置在凹部32与控制器芯片20或树脂基板10之间。第7实施方式的其它构成可以与第5实施方式相同。
如果如上所述那样粘接层50填满存储器芯片30的下方，那么粘接层50被覆整个控制器芯片20，因此对控制器芯片20施加大致均匀的应力。因此，第7实施方式即便在控制器芯片20并非为倒装芯片型的情况下也能够应用。
第7实施方式也可以与第6实施方式进行组合。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出的，并无意图限定发明的范围。这些实施方式能够以其它各种方式加以实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，同样地包含在权利要求书所记载的发明与其均等的范围内。
[符号的说明]
1～7 半导体装置
10 树脂基板
20 控制器芯片
30 存储器芯片
31 突出部
32 凹部
40、50 粘接层
60、70 金属导线
80 模具树脂

Claims (15)

1.一种半导体装置，具备：
基板，形成着电极；
第1半导体芯片，设置在所述基板的表面上；
导线，将所述第1半导体芯片与所述电极连接；
第2半导体芯片，设置在所述基板的表面上，在朝向所述基板侧的面即背面具有形成着突出部的第1区域及所述第1区域以外的第2区域，所述第2区域位于所述第1半导体芯片或所述导线的至少一部分的上方；
粘接层，设置在所述第1区域与所述基板之间及所述第2区域与所述基板之间；以及
树脂层，设置在所述基板上，且被覆所述第1及第2半导体芯片。
2.根据权利要求1所述的半导体装置，其中所述粘接层与所述第1半导体芯片或所述导线的至少一部分接触。
3.根据权利要求1所述的半导体装置，其中在沿所述第1及第2半导体芯片的排列方向切断的截面中，所述第2区域向从所述第2半导体芯片朝向所述第1半导体芯片的第1方向及相对于该第1方向为相反侧的第2方向这两个方向延伸，
所述粘接层设置在从所述第2半导体芯片向所述第1方向延伸的所述第2区域与所述基板之间、以及从所述第2半导体芯片向所述第2方向延伸的所述第2区域与所述基板之间。
4.根据权利要求1所述的半导体装置，其中所述第2区域设置在所述第2半导体芯片的所述第1区域的整个外周。
5.根据权利要求1所述的半导体装置，其中多个所述第2半导体芯片分开设置在所述第1半导体芯片的两侧，且
在多个所述第2半导体芯片间设置着所述树脂层。
6.根据权利要求1所述的半导体装置，其中所述第2半导体芯片具有多个所述第1区域，且遍及所述第1半导体芯片的上方而设置，
所述第1半导体芯片配置在所述多个第1区域间。
7.一种半导体装置，具备：
基板，形成着电极；
第1半导体芯片，设置在所述基板的表面上；
导线，将所述第1半导体芯片与所述电极连接；
第2半导体芯片，设置在所述基板的表面上，在朝向所述基板侧的面即背面具有形成着突出部的第1区域及所述第1区域以外的第2区域，所述第2区域位于所述第1半导体芯片或所述导线的至少一部分的上方；
粘接层，设置在所述第1区域与所述基板之间及所述第2区域与所述基板之间，且与所述第1半导体芯片或所述导线的至少一部分接触；以及
树脂层，设置在所述基板上，且被覆所述第1及第2半导体芯片；且
在沿所述第1及第2半导体芯片的排列方向切断的截面中，所述第2区域向从所述第2半导体芯片朝向所述第1半导体芯片的第1方向及相对于该第1方向为相反侧的第2方向这两个方向延伸，
多个所述第2半导体芯片分开设置在所述第1半导体芯片的两侧。
8.一种半导体装置，具备：
基板，形成着电极；
第1半导体芯片，设置在所述基板的表面上；
导线，将所述第1半导体芯片与所述电极连接；
第2半导体芯片，设置在所述基板的表面上，在朝向所述基板侧的面即背面具有形成着突出部的第1区域及所述第1区域以外的第2区域，所述第2区域位于所述第1半导体芯片或所述导线的至少一部分的上方；
粘接层，设置在所述第1区域与所述基板之间及所述第2区域与所述基板之间，且与所述第1半导体芯片或所述导线的至少一部分接触；以及
树脂层，设置在所述基板上，且至少被覆所述第2半导体芯片；且
在沿所述第1及第2半导体芯片的排列方向切断的截面中，所述第2区域向从所述第2半导体芯片朝向所述第1半导体芯片的第1方向及相对于该第1方向为相反侧的第2方向这两个方向延伸，
所述第2半导体芯片具有多个所述第1区域，且遍及所述第1半导体芯片的上方而设置，
所述第1半导体芯片配置在所述多个第1区域之间。
9.根据权利要求1至8中任一项所述的半导体装置，其中所述第2区域与所述第1区域的厚度差大于所述第1半导体芯片的厚度。
10.根据权利要求7或8所述的半导体装置，其还具备积层在所述第2半导体芯片上的第3半导体芯片。
11.一种半导体装置的制造方法，包括如下步骤：
在形成着电极的基板设置第1半导体芯片；
利用导线将所述第1半导体芯片与所述电极连接；
半导体晶圆的设备对形成面的相反面即背面的一部分进行切削，形成在该背面的第1区域突出的突出部、及在所述第1区域以外的所述背面的第2区域凹陷的凹部；
以填埋所述半导体晶圆的凹部的方式在该背面设置粘接层；
将所述半导体晶圆切断，并单片化成第2半导体芯片；
利用所述粘接层将第2半导体芯片的所述突出部粘接在基板的表面，并且将所述第2半导体芯片的所述凹部配置在设置在该第2半导体芯片之下的第1半导体芯片或所述导线的上方；以及
利用树脂层被覆所述基板上的至少第2半导体芯片。
12.根据权利要求11所述的半导体装置的制造方法，其中在形成所述突出部与所述凹部的步骤中，所述凹部是包含将所述第2半导体芯片单片化的切断线的区域。
13.根据权利要求11所述的半导体装置的制造方法，其中形成所述突出部与所述凹部时所使用的修剪刀片比将所述半导体晶圆单片化成所述第2半导体芯片时所使用的切割刀片宽。
14.根据权利要求11所述的半导体装置的制造方法，其中在形成所述突出部与所述凹部后，对所述半导体晶圆进行切割而单片化成多个所述第2半导体芯片。
15.根据权利要求11所述的半导体装置的制造方法，其中在形成所述突出部与所述凹部之前，对所述半导体晶圆进行切割并对所述半导体晶圆的背面进行研磨，由此将所述半导体晶圆单片化成多个所述第2半导体芯片。
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