CN116779571A - 可翻转的半导体芯片 - Google Patents

可翻转的半导体芯片 Download PDF

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CN116779571A
CN116779571A CN202310767298.8A CN202310767298A CN116779571A CN 116779571 A CN116779571 A CN 116779571A CN 202310767298 A CN202310767298 A CN 202310767298A CN 116779571 A CN116779571 A CN 116779571A
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chip
bond
bond pads
top surface
die
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CN116779571B (zh
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杨顺迪
波姆皮奥·V·乌马里
林根伟
哈里·马蒂纳斯·马里亚·霍尔斯蒂克
斯文·瓦尔兹克
梁志豪
蒂埃里·简斯
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Nexperia BV
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Nexperia BV
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Abstract

本申请公开了一种半导体芯片和一种半导体器件，半导体芯片具有形成在多于两个内部层上的内部电路，以及布置在芯片顶表面上的芯片接合焊盘。接合焊盘连接到内部电路，以向内部电路提供输入和输出信号。一条或多条连接线电连接一对或多对芯片接合焊盘，从而限定接合焊盘布局。芯片接合焊盘被布置并且与连接线连接，使得接合焊盘布局是可翻转的，这允许芯片以不同的封装类型(例如，TSSOP或DFN)使用，又维持标准的引脚布置而不需要长的或交叉的接合导线。

Description

可翻转的半导体芯片
本申请是申请号为2017109314652、申请日为2017年10月9日、发明名称为“可翻转的半导体芯片”的专利申请的分案申请。
技术领域
本发明涉及半导体芯片，更具体地，涉及具有特定芯片焊盘布局的半导体芯片。
背景技术
半导体芯片由晶片切割而成并且附接至引线框架或衬底上，然后用塑料材料包封以防止芯片被物理地损坏。芯片通常在其“有效表面”上包括多个电极或芯片接合焊盘。这些电极连接至引线框架或衬底上的相应的连接点(例如，引线指)，以便将芯片电极连接至封装件引脚，这些封装件引脚是便于将芯片内部电路连接到外部电路的外部连接点。
可以以各种封装类型提供所封装的芯片，例如适应不同用户要求的薄收缩小外形封装(TSSOP)或双平面无引线(DFN)。图1A示出了5引脚的TSSOP 10，其包括封装主体12和从封装主体12向外延伸的引线或引脚14。图1B是TSSOP 10的截面图，其中半导体芯片16附接至引线框架的标志区并且用接合导线18电连接至内部引线14。图2A示出了具有封装主体22和外部连接点24的DFN封装件20，外部连接点24通常与封装主体22齐平。图2B是DFN封装件20的截面图，其中半导体芯片16附接至引线框架的标志区并且用接合导线26电连接至引线。
由于封装件中的芯片的各种封装类型和放置(例如在引线框架的上部或底部)，不同的芯片布局对于满足标准化引脚分配的要求是必要的。例如，图3A是TSSOP的底部截面图，其示出了从芯片接合焊盘延伸至内部引线14的接合导线18。在该情况下，导线18跨越最小的距离，并且不与任何其它导线18交叉。图3B是DFN封装件20的顶部截面图。然而，对于该封装类型，导线26必须跨越更长的距离，例如跨过芯片16的宽度，就像到达引脚2和引脚3的导线一样。此外，导线26中的一些也彼此交叉，例如到达引脚1和引脚6的导线和到达引脚3和引脚4的导线。具有更长的导线和交叉的导线可能会导致组装风险、产量降低并且会降低组装处理速度。然而，提供具有不同焊盘布局的同一芯片的不同版本以适应不同封装类型也是昂贵的。
因此，期望具有这样的半导体芯片，其芯片焊盘被布置成使得芯片可以适应不同的封装需求，又保持相同的引脚分配而不增加组装风险。
发明内容
在一个实施例中，本发明提供了一种半导体芯片，其具有形成在两层以上内部层上的内部电路以及布置在芯片的顶表面上的芯片接合焊盘。接合焊盘连接至内部电路以将输入和输出信号提供至内部电路。一条或多条连接线电连接一对或多对芯片接合焊盘，从而限定接合焊盘布局。芯片接合焊盘被布置并且与连接线连接使得接合焊盘布局是可翻转的(reversible)，这允许芯片以不同的封装类型(例如，TSSOP或DFN)使用，又保持标准的引脚布置，而不需要长的或交叉的接合导线。
在另外的实施例中，本发明提供了一种半导体器件，其包括衬底、半导体芯片、接合导线和包封材料。衬底包括标志区和多条引线。半导体芯片附接至标志区。芯片包括：内部电路；多个接合焊盘，其被设置在芯片的顶表面上并且电连接至内部电路以向内部电路提供输入和输出信号；以及一条或多条连接线，其电连接一对或多对芯片接合焊盘。接合焊盘和连接线的布置限定了接合焊盘布局。接合导线将预定的一些芯片接合焊盘与预定的一些引线电连接。包封材料覆盖芯片和接合导线，但是每条引线的至少一部分被暴露。芯片接合焊盘被布置并且与连接线连接使得接合焊盘布局是可翻转的。即，芯片可以附接至引线框架或衬底的顶侧或底侧，并且仍然允许芯片接合焊盘连接至引线使得保持标准的引脚布置，并且不需要长的交叉的接合导线。
附图说明
本发明以示例的方式示出，并且不受附图所示的实施例的限制，其中相同的附图标记表示相同的元件。附图中的元件为了简单和清楚而被示出，并且不一定按比例绘制。应注意，某些尺寸被夸大以便于更好地理解本发明，附图中：
图1A是传统的薄收缩小外形封装件(TSSOP)的等距视图，图1B是TSSOP的侧截面视图；
图2A是传统的DFN封装件的等距视图，图2B是DFN封装件的侧截面视图，以及
图3A是图1A的TSSOP的底截面视图，图3B是图2A的DFN封装件的顶截面视图；
图4A是根据本发明的实施例的具有8个接合焊盘的半导体芯片的俯视图，图4B是附接至第一引线框架的图4A的芯片的俯视图，图4C是附接至第二引线框架的图4A的芯片的俯视图；
图5A是根据本发明的实施例的具有10个接合焊盘的半导体芯片的俯视图，图5B是附接至第一引线框架的图5A的芯片的俯视图，并且图5C是附接至第二引线框架的图5A的芯片的俯视图；
图6A是根据本发明的实施例的具有6个接合焊盘的半导体芯片的俯视图，图6B是附接至第一引线框架的图6A的芯片的俯视图，图6C是附接至第二引线框架的图6A的芯片的俯视图；以及
图7是根据本发明的实施例的半导体芯片的截面侧视图。
具体实施方式
现在参考附图，其中相同的附图标记在几个附图中始终指代相同的部件，图4A示出了根据本发明的实施例的半导体芯片30的俯视图。芯片30具有顶表面或有效表面32以及形成在顶表面32下方的多个层上的内部电路。层数和内部电路可以是传统的，不需要对其进行详细描述来全面理解本发明。
多个芯片接合焊盘34被布置在芯片30的顶表面32上。在示出的实施例中，存在沿着顶表面32的周边布置的8个接合焊盘，并且为了方便，它们被编号为1至8。接合焊盘34连接至内部电路从而以传统方式向内部电路提供输入和输出信号(例如，利用过孔)。还存在一条或多条连接线36，其电连接一对或多对芯片接合焊盘34，从而限定接合焊盘布局。在示出的实施例中，存在3条连接线36。每条连接线36将2个接合焊盘34彼此电连接。更具体地，在本发明的优选实施例中，连接线36对角地延伸跨越芯片顶表面32并且连接顶表面32的相对侧上的接合焊盘。另外，连接线36大致彼此平行。在本发明的优选实施例中，连接线36包括越过顶表面32的金属迹线(metal trace)。然而，在另外的实施例中，使用芯片30的过孔和下金属层来形成连接线36，以连接预定的一些芯片接合焊盘34。
芯片接合焊盘34被布置并且与连接线36连接使得接合焊盘布局是可翻转的。即，如下面参考图4B和图4C更详细地说明的那样，芯片30可以附接至引线框架的顶部或底部，芯片接合焊盘34仍然可以使用接合线连接至引线框架的同一引线，而不需要长的接合导线或交叉的接合导线。
图4B是图4A的芯片30的俯视图，芯片30附接至用于组装与图1A、图1B和图3A中示出的TSSOP 10类似的TSSOP的第一引线框架40。引线框架40具有多个引线指42，在该实施例中，引线指42是包括标签1至5的5个引线指。引线指42-1至42-5也被称为引脚1至引脚5。因此，在示出的实施例中，引脚1用接合导线44连接至芯片接合焊盘34-4；引脚2连接至芯片接合焊盘34-2，引脚3连接至芯片接合焊盘34-3，引脚4连接至芯片接合焊盘34-8，并且引脚5连接至芯片接合焊盘34-6。芯片接合焊盘34-5和34-7不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线44都不必跨越芯片顶表面32，任何的接合导线44也不必与其他接合导线交叉。
图4C是附接至第二引线框架46的芯片30的俯视图，第二引线框架46具有被编号为1至6的6条引线或引线指48。引线框架46是用于DFN类型封装件的引线框架。因此，与在图2A、图2B和图3B中类似，芯片30附接至引线48的顶表面(通过引线框架标志的方式概括地显示)。
在该实施例中，引脚1连接至芯片接合焊盘34-7，芯片接合焊盘34-7通过连接线36连接至芯片接合焊盘34-4；引脚2连接至芯片接合焊盘34-5，芯片接合焊盘34-5通过一条连接线36连接至芯片接合焊盘34-2；引脚3连接至芯片接合焊盘34-3；引脚4连接至芯片接合焊盘34-1，从而还通过一条连接线36连接至芯片接合焊盘34-8；引脚5不连接；以及引脚6连接至芯片接合焊盘34-6。芯片接合焊盘34-2、34-4、34-8不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线44都不必跨越芯片顶表面32，任何的接合导线44也不必与其他接合导线交叉。而且，同一个芯片30既用于图4B的TSSOP又用于图4C的DFN，并仅仅通过使芯片旋转90°来维持相同的引脚分配。
现在参考图5A，图5A示出了根据本发明的另一实施例的半导体芯片50的俯视图。芯片50具有顶表面或有效表面52以及形成在顶表面52下方的多个层上的内部电路。如参考图4A所讨论的，层数和内部电路可以是传统的。
多个接合焊盘54被布置在芯片50的顶表面52上。在示出的实施例中，存在沿着顶表面52的周边布置的10个接合焊盘，并且为了方便，它们被编号为1至10。接合焊盘54连接至内部电路从而以传统方式向内部电路提供输入和输出信号(例如，利用到达下金属层的过孔)。通常，接合焊盘54沿着芯片顶表面52的周边布置。然而，当存在更多数量的接合焊盘时，例如，在这里，一个或多个接合焊盘54可以偏离其他对齐的接合焊盘。例如，在图5A中，显然，接合焊盘4与芯片50的左边缘上的其它接合焊盘(焊盘1、6和8)偏离，而在右侧，焊盘7偏离芯片边缘并且与焊盘3、5和10不完全对齐。
还存在一条或多条连接线56，其电连接一对或多对芯片接合焊盘54，从而限定接合焊盘布局。在示出的实施例中，存在4条连接线56，每条连接线56将2个接合焊盘54彼此电连接。连接线56对角地延伸跨越芯片顶表面52并且连接顶表面52的相对侧上的接合焊盘54。另外，连接线56大致彼此平行。在示出的实施例中，芯片接合焊盘2和4、3和6、5和8以及7和9分别利用对应的连接线56彼此连接。
芯片接合焊盘54被布置并且与连接线56连接使得接合焊盘布局是可翻转的。即，如将参考图5B和图5C更详细地说明的那样(并且与图4A至图4C示出的芯片30类似)，芯片50可附接至引线框架的顶部或底部，并且芯片接合焊盘54仍然可以使用接合导线连接至引线框架的同一引线，而不需要长的接合导线或交叉的接合导线。
图5B是图5A的芯片50的俯视图，芯片50附接至用于组装与TSSOP 10(图1A、图1B和图3A)和TSSOP 40(图4B)类似的TSSOP的第一引线框架60。引线框架60具有多个引线指62，在该实施例中，为六个引线指，其包括标签1至6。引线指62-1至62-6也被称为引脚1至引脚6。因此，在示出的实施例中，引脚1用接合导线64连接至芯片接合焊盘54-1；引脚2连接至芯片接合焊盘54-4；引脚3连接至芯片接合焊盘54-8，引脚4连接至芯片接合焊盘54-10，引脚5连接至芯片接合焊盘54-7，并且引脚6连接至芯片接合焊盘54-3。芯片接合焊盘54-2、54-5、54-6和54-9不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线64都不必跨越芯片顶表面52，任何的接合导线64也不必与其他接合导线交叉。
图5C是附接至第二引线框架66的芯片50的俯视图，第二引线框架66具有被编号为1至6并且被称为引脚1至6的6条引线或引线指68。第二引线框架66是用于DFN类型封装件的引线框架。因此，如在图2A、图2B、图3B和图4C中那样，芯片50附接至引线68的顶表面(通过引线框架标志的方式概括地显示)。
在该实施例中，引脚1连接至芯片接合焊盘54-1；引脚2利用接合导线64连接至芯片接合焊盘54-2；引脚3连接至芯片接合焊盘54-5；引脚4连接至芯片接合焊盘54-10；引脚5连接至芯片接合焊盘54-9；以及引脚6连接至芯片接合焊盘54-6。芯片接合焊盘54-3、54-4、54-7和54-8不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线64都不必跨越芯片顶表面52，任何的接合导线64也不必与其他接合导线交叉。而且，同一个芯片50既用于图5B的TSSOP又用于图5C的DFN，并仅仅通过使芯片旋转90°来维持相同的引脚分配。
现在参考图6A，图6A示出了根据本发明的又一实施例的半导体芯片70的俯视图。芯片70具有顶表面或有效表面72以及形成在顶表面72下方的多个层上的内部电路。如参考图4A所讨论的，层数和内部电路可以是传统的。
多个接合焊盘74被布置在芯片70的顶表面72上。在示出的实施例中，存在沿着顶表面72的周边布置的6个接合焊盘，并且为了方便，它们被编号为1至6。接合焊盘74连接至内部电路从而以传统方式向内部电路提供输入和输出信号(例如，利用到达下金属层的过孔)。此外，还存在电连接一对或多对芯片接合焊盘74的一条或多条连接线76，从而限定了接合焊盘布局。在示出的实施例中，存在2条连接线。每条连接线76将两个接合焊盘74彼此电连接(在该情况下，焊盘1和焊盘5、以及焊盘2和焊盘6分别彼此连接)。连接线76对角地跨越芯片顶表面72并且连接顶表面72的相对侧上的接合焊盘74。连接线76还大致彼此平行。
芯片接合焊盘74被布置并且与连接线76连接使得接合焊盘布局是可翻转的。即，如将参考图6B和图6C更详细地说明的那样(并且与图4A至图4C和图5A至图5C示出的芯片30和芯片50类似)，芯片70可附接至引线框架的顶部或底部，并且芯片接合焊盘74仍然可以使用接合导线连接至引线框架的同一引线，而不需要长的接合导线或交叉的接合导线，以便使用同一芯片而在不同的封装类型上维持标准引脚分配。
图6B是芯片70的俯视图，芯片70附接至用于组装与TSSOP 10(图1A、图1B和图3A)、TSSOP 40(图4B)和TSSOP 60(图5B)类似的TSSOP的第一引线框架80。引线框架80具有多个引线指82，在该实施例中是4个引线指，其包括标签1至4。引线指82-1至82-4也被称为引脚1至引脚4。因此，在示出的实施例中，引脚1利用接合导线84连接至芯片接合焊盘74-1；引脚2连接至芯片接合焊盘74-3；引脚3连接至芯片接合焊盘74-6；以及引脚4连接至芯片接合焊盘74-4。芯片接合焊盘74-2和74-5不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线84都不必跨越芯片顶表面72，任何的接合导线84也不必与其他接合导线交叉。
图6C是附接至第二引线框架86的芯片70的俯视图，第二引线框架86具有被编号为1至4并且被称为引脚1至引脚4的4条引线或引线指88。第二引线框架86是用于DFN类型封装件的引线框架。因此，与在图2A、图2B、图3B、图4C和图5C中类似，芯片70附接至引线88的顶表面(通过引线框架标志的方式概括地显示)。
在该实施例中，引脚1连接至芯片接合焊盘74-5；引脚2连接至芯片接合焊盘74-3；引脚3连接至芯片接合焊盘74-3；以及引脚4连接至芯片接合焊盘74-4。芯片接合焊盘74-1和74-6不具有直接附接至其上的接合导线。可以看出，根据良好的组装实践，接合导线84都不必跨越芯片顶表面72，任何的接合导线84也不必与其他接合导线交叉。而且，同一个芯片70既用于图6B的TSSOP又用于图6C的DFN，并仅仅通过使芯片旋转90°来维持相同的引脚分配。
根据本发明，已经描述了具有若干连接的接合焊盘对(CP)的半导体芯片，其中CP＝(P-2)/2，P为接合焊盘的数量。接合焊盘通常沿着芯片的有效表面的周边对齐，但是在一些实施例中，一个或多个接合焊盘从其他对齐的接合焊盘偏离。芯片接合焊盘也可以形成在有效电路上(在有效表面上接合)，如本领域已知的，或形成在芯片的非有效区上。
图7示出了两个接合焊盘90和92如何可以通过连接线连接，连接线包括过孔94至100以及在半导体芯片104的下层中的金属迹线102。图7还示出了接合焊盘90和92如何可以与连接线106电连接，如虚线所示，连接线106形成在芯片104的顶表面上。
以上已经参照本发明的实施例的具体示例描述了本发明。然而，显然，在不脱离所附权利要求所阐述的概括的精神和范围的情况下，可以做出各种变型和修改。
本领域的技术人员将认识到，上述操作之间的界限仅仅是示例性的。多个操作可以组合成单个操作，单个操作可以分布在附加操作中，并且各操作可以在时间上至少部分重叠地执行。此外，替代实施例可以包括特定操作的多个实例，并且除非明确排序的步骤之外，在各种其它实施例中可以改变操作顺序。
说明书和权利要求中的术语“前面”、“背面”、“顶部”、“底部”、“上方”、“下方”等(如果存在的话)，用于描述目的，而不一定用于描述永久的相对位置。应当理解，如此使用的术语在适当的情况下是可互换的，使得本文所述的本发明的实施例例如能够以除本文所示或另外描述的其它情况操作。
在权利要求中，词语“包括”或“具有”并不排除权利要求中所列出的之外的其它元件或步骤的存在。此外，如本文所使用的术语“一”或“一个”被定义为一个或多于一个。此外，在权利要求中使用诸如“至少一个”和“一个或多个”等介绍性短语不应被解释为暗示由不定冠词“一”或“一个”引入另一个权利要求元素而限定将这种引入的权利要求元素包含到仅包含一个这种元素的发明的任何特定的权利要求，即使同一权利要求包括介绍性短语“一个或多个”或“至少一个”以及例如“一”或“一个”的不定冠词。使用定冠词也是如此。除非另有说明，术语如“第一”和“第二”用于任意区分这些术语描述的要素。因此，这些术语不一定意在表示这些元素的时间或其他优先级。在相互不同的权利要求中叙述某些措施的事实并不表示这些措施的组合不能有利地使用。

Claims (13)

1.一种半导体芯片，包括：
内部电路，其形成在所述半导体芯片的有效顶表面下方的多个层上；
多个芯片接合焊盘，其被布置在所述芯片的所述有效顶表面上，其中，所述接合焊盘连接至位于所述半导体芯片的所述顶表面下方的所述有效内部电路，并且构造为向位于所述有效顶表面之下的层上的所述有效内部电路提供输入和输出信号；以及
接合焊盘布局，所述接合焊盘布局包括多条连接线，所述多条连接线从所述芯片的一侧延伸至所述芯片的相对侧，以电连接对应的多对接合焊盘，
其中，所述接合焊盘被布置并且与所述连接线连接使得所述接合焊盘布局是可翻转的，以及
其中，CP＝(P-2)/2，CP是所电连接的接合焊盘对的数量，以及P是所述芯片接合焊盘的数量。
2.根据权利要求1所述的半导体芯片，其中，所述接合焊盘沿着所述芯片顶表面的周边布置。
3.根据权利要求2所述的半导体芯片，其中，两个或更多个所述接合焊盘沿着所述芯片的一侧彼此对齐，并且从所述对齐的接合焊盘偏离的另外的一个或多个所述接合焊盘彼此对齐。
4.根据权利要求1所述的半导体芯片,其中，所述连接线包括跨越所述有效顶表面的金属迹线。
5.根据权利要求1所述的半导体芯片,其中，所述连接线从所述芯片的一侧对角地延伸至所述芯片的所述相对侧。
6.根据权利要求5所述的半导体芯片,其中，所述连接线实质上彼此平行。
7.一种半导体器件，包括：
衬底，其具有标志区和多条引线；
半导体芯片，其附接至所述标志区，其中，所述半导体芯片包括：有效内部电路；多个接合焊盘，其被布置在所述芯片的有效顶表面上，并电连接至形成在所述芯片的所述有效顶表面下方的多个层上的所述有效内部电路，并且所述多个接合焊盘构造为向位于所述有效顶表面之下的层上的所述有效内部电路提供输入和输出信号；以及接合焊盘布局，所述接合焊盘布局包括多条连接线，所述多条连接线从所述芯片的一侧对角地延伸至所述芯片的相对侧，以电连接对应的多对芯片接合焊盘；
多条接合导线，其将预定的所述芯片接合焊盘与预定的所述引线电连接；以及
包封材料，其覆盖所述半导体芯片和所述接合导线，其中所述引线的至少一部分被暴露，
其中，所述接合焊盘被布置并且与所述连接线连接使得所述接合焊盘布局是可翻转的，并且
其中，所述连接线实质上彼此平行。
8.根据权利要求7所述的半导体器件，其中：
CP＝(P-2)/2，
其中，CP是所电连接的接合焊盘对的数量，以及P是接合焊盘的数量。
9.根据权利要求8所述的半导体器件，其中，每个所连接的接合焊盘对中的仅一个接合焊盘利用一条所述接合导线连接至引线。
10.根据权利要求7所述的半导体器件，其中，所述接合焊盘沿着所述芯片有效顶表面的周边布置。
11.根据权利要求10所述的半导体器件，其中，两个或更多个所述接合焊盘沿着所述芯片一侧彼此对齐，并且另外的一个或多个所述接合焊盘与所述对齐的接合焊盘偏离。
12.根据权利要求7所述的半导体器件，其中，所述连接线包括跨越所述顶表面的金属迹线。
13.根据权利要求7所述的半导体器件，其中，所述包封材料是环氧树脂。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164627A (ja) * 1998-11-25 2000-06-16 Mitsubishi Electric Corp 半導体装置及びモジュール及びそれを用いたｉｃカード
CN103703549A (zh) * 2011-04-05 2014-04-02 德克萨斯仪器股份有限公司 用于直接表面安装的裸露芯片封装

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164627A (ja) * 1998-11-25 2000-06-16 Mitsubishi Electric Corp 半導体装置及びモジュール及びそれを用いたｉｃカード
CN103703549A (zh) * 2011-04-05 2014-04-02 德克萨斯仪器股份有限公司 用于直接表面安装的裸露芯片封装

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