TW201816962A - 改良之扇出球狀柵格陣列封裝結構及其製造方法 - Google Patents

改良之扇出球狀柵格陣列封裝結構及其製造方法 Download PDF

Info

Publication number
TW201816962A
TW201816962A TW106134704A TW106134704A TW201816962A TW 201816962 A TW201816962 A TW 201816962A TW 106134704 A TW106134704 A TW 106134704A TW 106134704 A TW106134704 A TW 106134704A TW 201816962 A TW201816962 A TW 201816962A
Authority
TW
Taiwan
Prior art keywords
electrical connector
package
substantially planar
semiconductor device
core
Prior art date
Application number
TW106134704A
Other languages
English (en)
Other versions
TWI756275B (zh
Inventor
葉俊良
王盟仁
蔡宗岳
洪志明
Original Assignee
日月光半導體製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日月光半導體製造股份有限公司 filed Critical 日月光半導體製造股份有限公司
Publication of TW201816962A publication Critical patent/TW201816962A/zh
Application granted granted Critical
Publication of TWI756275B publication Critical patent/TWI756275B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15322—Connection portion the connection portion being formed on the die mounting surface of the substrate being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明提供一種表面黏著結構，其包含一重佈結構、一電連接件及一封裝體。該重佈結構具有一第一表面及與該第一表面相對之一第二表面。該電連接件在該重佈結構之該第一表面上。該封裝體囊封該重佈結構之該第一表面及該電連接件。該電連接件之一部分藉由該封裝體暴露。

Description

改良之扇出球狀柵格陣列封裝結構及其製造方法
本發明大體上係關於一種扇出球狀柵格陣列(BGA)封裝結構，且更特定而言，係關於具有較小厚度、具有條帶型扇出BGA結構及具有低製造成本之封裝結構。
半導體裝置封裝持續受到電子產品之設計者及製造商的大量關注。該關注係基於對於效率更大、效能更高及尺寸更小之電子產品的市場需求。 開發BGA封裝以期滿足對於具有較高導線計數及較小佔據面積之封裝的需求。BGA封裝通常為正方形封裝，其末端呈自該封裝之底部突起的焊球陣列之形式。此等末端經設計以安裝在位於印刷電路板之表面上的複數個墊或其他互連件上。BGA之跡線通常製造於層壓基板(例如，基於雙順丁烯二醯亞胺三嗪(BT)之基板)或基於聚醯亞胺之薄膜上。因此，此基板或薄膜之整個區域可用於路由互連。BGA之優勢為更低的接地電感或電力電感，由此經由較短電流路徑將接地網或電力網分配至印刷電路板(PCB)。熱增強型機構(散熱片、熱球等)可應用於BGA以減小熱阻。BGA封裝技術之功能能力使指定增強型電及熱效能之高功率及高速整合晶片(IC)受益。
在一些實施例中，表面黏著結構包含重佈結構、電連接件及封裝體。該重佈結構具有第一表面及與該第一表面相對之第二表面。該電連接件在該重佈結構之該第一表面上。該封裝體囊封該重佈結構之第一表面及該電連接件。該電連接件之一部分藉由該封裝體暴露。 在一些實施例中，半導體裝置封裝將藉由表面黏著技術安裝於外部電路板上。該半導體裝置封裝包含重佈結構、半導體裝置、電連接件及封裝體。該重佈結構具有第一表面及與該第一表面相對之第二表面。該半導體裝置在該重佈結構之第一表面上。該電連接件在該重佈結構之第一表面上。該封裝體囊封重佈結構之第一表面、半導體裝置及電連接件。該電連接件之一部分藉由該封裝體暴露。 在一些實施例中，電子裝置包含電路板及半導體裝置封裝。該電路板具有第一表面。半導體裝置封裝安裝在電路板之第一表面上。該半導體裝置封裝包含重佈結構、半導體裝置、電連接件及封裝體。該重佈結構具有第一表面及與該第一表面相對之第二表面。該半導體裝置在該重佈結構之第一表面上。該電連接件在該重佈結構之第一表面上。該封裝體囊封重佈結構之第一表面、半導體裝置及電連接件。
相關申請案之交叉參考 本申請案主張於2016年10月17日申請之美國臨時專利申請案62/409,252之權益及優先權，該申請案以全文引用之方式併入本文中。 在諸如BGA封裝技術之封裝技術中，可在封裝之晶粒周圍形成模製化合物以提供用於支撐扇出互連結構之額外表面區域。互連結構之重佈層(RDL)將晶粒上之輸入/輸出(I/O)墊電連接至扇出互連結構上的外部I/O墊。特定而言，BGA封裝結構可包括半導體裝置(例如，覆晶晶粒或線接合晶粒)，其通常附接至載體(例如，基板、導線框架等)且由囊封層模製以形成半導體裝置封裝。 然而，一些提供某些特定功能之半導體裝置(例如，指紋感測器晶粒)可安裝至頂部載體(例如，具有感測區域之載體)，且該頂部載體經組裝至底部載體(例如，用於電路扇出之載體)，以便安裝至系統板(例如，PCB)。此類多載體結構可具有在大小(X-Y平面及Z高度)及製造成本方面的缺陷。 圖1A說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。表面黏著結構10包含重佈結構11、電連接件12、封裝體13、半導體裝置14、凸塊15、電子組件16及底填充層17。重佈結構11具有表面111及與表面111相對之表面112。電連接件12中之至少一者在重佈結構11之表面111上。封裝體13囊封重佈結構11之表面111及電連接件12。各電連接件12之一部分藉由封裝體13暴露。 半導體裝置14安裝於重佈結構11之表面111上。半導體裝置14及重佈結構11由凸塊15電連接。在一些實施例中，凸塊之間的空間以底填充層17填充。電連接件12圍繞半導體裝置14之周邊且用於扇出半導體裝置14之輸入及輸出。電子組件16 (例如，電阻器或電容器)亦安裝於重佈結構11之表面111上。半導體裝置14及電子組件16兩者藉由封裝體13囊封。在一些實施例中，表面黏著結構10進一步包含鄰近於重佈結構11之第二表面112的感測區域18。感測區域18可用於(例如)指紋感測或任何其他光感測目的。 如圖1A中所示，重佈結構11不延伸至封裝體13之側壁。因此，表面黏著結構10之寬度(由封裝體13之兩個側壁之間的距離定義)可藉由切割封裝體13調整以滿足表面黏著結構10之所要寬度。 在一些實施例中，電連接件12包含芯，該芯包含金屬芯或球體121及圍繞該金屬芯或球體121之障壁層122。電連接件12進一步包含圍繞芯之金屬球體121及障壁層122之焊料層123。 在一些實施例中，電連接件12可為(例如)焊球、金屬柱(例如，銅柱)、包括由焊料殼(例如，Sn)圍繞之銅芯的導電球、包括由低熔融溫度之焊料殼(例如，高熔融溫度Sn)圍繞之高熔融溫度焊料芯(例如，高熔融溫度Sn)的導電球，或其兩者或多於兩者之組合。 在一些實施例中，底填充層17可為(例如)毛細管底膠。在一些實施例中，延伸至晶粒下方之封裝體13之一部分亦可充當底膠。 圖1B說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖1B中所示之表面黏著結構10在某些態樣類似於圖1A中所示之表面黏著結構10，不同之處在於在圖1B中，重佈結構11延伸至封裝體13之側壁。因此，在至少一些實施例中，表面黏著結構10之寬度(由封裝體13之兩個側壁之間的距離定義)可能並未藉由切割封裝體13來調整。與圖1B中所示之表面黏著結構10相比，圖1A中所示之表面黏著結構10之封裝大小可由單體化之後的封裝體13之大小判定，而非由重佈結構11之大小指定，由此提供較大的封裝大小設計靈活性。 圖2A說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖2A中所示之表面黏著結構10在某些態樣類似於圖1A中所示之表面黏著結構10，不同之處在於在圖2A中，半導體裝置14經由接線25電連接至重佈結構11。在一些實施例中，接線25可為(例如)金(Au)線、銅(Cu)線、金屬合金線、銀(Ag)線、鋁(Al)線，或其兩者或多於兩者之組合。 圖2B說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖2B中所示之表面黏著結構10在某些態樣類似於圖2A中所示之表面黏著結構10，不同之處在於在圖2B中，重佈結構11延伸至封裝體13之側壁。因此，在至少一些實施例中，表面黏著結構10之寬度(由封裝體13之兩個側壁之間的距離定義)可能並未藉由切割封裝體13來調整。與圖2B中所示之表面黏著結構10相比，圖2A中所示之表面黏著結構10之封裝大小可由單體化之後的封裝體13之大小判定，而非由重佈結構11之大小指定，由此提供較大的封裝大小設計靈活性。 圖3說明根據本發明之一些實施例的表面黏著結構之電連接件之橫截面圖。電連接件12包含芯，該芯包含金屬球體121及圍繞該金屬球體121之障壁層122。電連接件12進一步包含圍繞芯之金屬球體121及障壁層122之焊料層123。障壁層122在金屬球體121與焊料層123之間的介面上。障壁層122之厚度相對薄(例如，約1微米(μm)、約2 μm、約3 μm、約5 μm、約10 μm或約1 μm至約10 μm)。 在一些實施例中，金屬球體121可由(例如)銅(Cu)、金(Au)或其組合形成。障壁層122可由(例如)鎳(Ni)形成。焊料層可由(例如)基於錫(Sn)之焊料(例如，錫-銀-銅(SAC)焊料、錫-銀(SnAg)焊料等)形成。在一些實施例中，包括金屬球體121及障壁層122之芯在模製程序期間經壓製成類橢圓或類卵形形狀(例如，具有大於1之縱橫比)，其中薄膜層用以抑制封裝體13並使其成形。然而，至少在一些實施例中，即使在移除薄膜層之後，包括金屬球體121及障壁層122之芯可能不會自類橢圓或類卵形形狀恢復至類球體形狀，係因為包括金屬球體121及障壁層122之芯之彈性模數(例如，彈性模數、拉伸模數或楊氏模數(Young's modulus))可能相對高。 圖4說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖4中所示之表面黏著結構10在某些態樣類似於圖1A中所示之表面黏著結構10，不同之處在於在圖4中，電連接件42包含芯，該芯包含彈性球體或芯420、圍繞該彈性球體或芯420之金屬層421，及圍繞該金屬層421之障壁層422。電連接件42包含圍繞該芯之焊料層423。在一些實施例中，彈性球體420包含(例如)聚合物。在一些實施例中，彈性球體420具有範圍自大致1吉帕斯卡(GPa)至大致50 GPa、自大致0.5 GPa至大致100 GPa或自大致0.1 GPa至大致500 GPa之彈性模數(例如，彈性模數、拉伸模數或楊氏模數)。在一些實施例中，彈性球體420具有範圍自大致3 GPa至大致6 GPa、自大致1 GPa至大致10 GPa、自大致0.5 GPa至大致50 GPa之彈性模數(例如，彈性模數、拉伸模數或楊氏模數)。銅之彈性模數(例如，彈性模數、拉伸模數或楊氏模數)為約117 GPa。 圖5說明根據本發明之一些實施例的表面黏著結構之電連接件之橫截面圖。電連接件42包含芯，該芯包含彈性球體420、金屬層421及障壁層422。金屬層421圍繞彈性球體420。障壁層422圍繞金屬層421。電連接件42進一步包含圍繞該芯之焊料層423。障壁層422在金屬層421與焊料層423之間的介面上。障壁層422之厚度相對薄。 在一些實施例中，彈性球體420可由聚合物形成。金屬層421可由(例如)銅(Cu)、金(Au)或其組合形成。障壁層422可由(例如)鎳(Ni)形成。焊料層423可由(例如)基於錫(Sn)之焊料(例如，錫-銀-銅(SAC)焊料、錫-銀(SnAg)焊料等)形成。在一些實施例中，包括420、421及422之芯在模製程序期間經壓製成類橢圓或類卵形形狀，其中薄膜層用以抑制封裝體13並使其成形。 在至少一些實施例中，由於彈性球體420之彈性模數(例如，彈性模數、拉伸模數或楊氏模數)之範圍可為自大致1 GPa至大致50 GPa、自大致0.5 GPa至大致100 GPa或自大致0.1 GPa至大致500 GPa，彈性球體420可在移除薄膜層之後自類橢圓或類卵形形狀恢復至類球體形狀(例如，具有約1之縱橫比)。然而，金屬層421及障壁層422可能不會自類橢圓或類卵形形狀恢復至類球體形狀，因為相較於彈性球體420之彈性模數，金屬層421及障壁層422之彈性模數(例如，彈性模數、拉伸模數或楊氏模數)相對較高。因此，彈性球體420可藉由空間50與金屬層421分離。金屬層421接著定義類橢圓或類卵形球面空間50。空間50中可能沒有物質且其可為真空。空間50中可能不存在可氧化金屬層421之空氣或其他氣體。 另外，歸因於彈性球體420之相對較低的彈性模數，與圖3中藉由封裝體13暴露之電連接件12之部分的高度相比，圖5中藉由封裝體13暴露之電連接件42之部分的高度可更容易控制。如圖5之實施例中所示，藉由封裝體13暴露之電連接件42之部分的高度可至少為或大於(例如)約100 μm、約200 μm或約400 μm。為了進行比較，如圖3之實施例中所示，藉由封裝體13暴露之電連接件12之部分的高度相對較小。為了表面黏著至印刷電路板上，藉由封裝體13暴露之電連接件12之部分的高度可經指定為至少為或大於約50 μm。 圖6A說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖6A中所示之表面黏著結構10在某些態樣類似於圖1A中所示之表面黏著結構10，不同之處在於在圖6A中，電連接件62接地以在圖6A之表面黏著結構10之底部形成實質上平面表面624。封裝體13具有表面131，且電連接件62具有實質上平面表面624。電連接件62之實質上平面表面624相對於封裝體13之表面131突出。 圖6B說明圖6A之表面黏著結構10之仰視圖。在一些實施例中，電連接件62包含金屬類球面芯621及圍繞該金屬類球面芯621之障壁層622。金屬類球面芯621具有實質上平面表面，且障壁層622具有實質上平面表面。金屬類球面芯621之實質上平面表面及障壁層622之實質上平面表面藉由封裝體13暴露。電連接件62進一步包含圍繞障壁層622之焊料層623。焊料層623具有實質上平面表面。焊料層623之實質上平面表面亦藉由封裝體13暴露。 圖7A說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖7A中所示之表面黏著結構10在某些態樣類似於圖1A中所示之表面黏著結構10，不同之處在於在圖7A中，電連接件72接地以在圖7A之表面黏著結構10之底部形成實質上平面表面724。封裝體13具有第一表面131，且電連接件72具有實質上平面表面724。電連接件72之實質上平面表面724與封裝體131之表面131實質上共面。 圖7B說明圖7A之表面黏著結構10之仰視圖。在一些實施例中，電連接件72包含金屬類球面芯721及圍繞該金屬類球面芯721之障壁層722。金屬類球面芯721具有實質上平面表面，且障壁層722具有實質上平面表面。金屬類球面芯721之實質上平面表面及障壁層722之實質上平面表面藉由封裝體13暴露。電連接件72進一步包含圍繞障壁層722之焊料層723。焊料層723具有實質上平面表面。焊料層723之實質上平面表面亦藉由封裝體13暴露。 圖8A說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。圖8A中所示之表面黏著結構10在某些態樣類似於圖4中所示之表面黏著結構10，不同之處在於在圖8A中，電連接件82接地以在底部形成實質上平面表面824。封裝體13具有第一表面131，且電連接件82具有實質上平面表面824。電連接件82之實質上平面表面824與封裝體131之表面131實質上共面。 圖8B說明圖8A之表面黏著結構10之仰視圖。在一些實施例中，電連接件82包含彈性類球面芯820、金屬層821及障壁層822。金屬層821圍繞彈性類球面芯820。障壁層822圍繞金屬層821。彈性類球面芯820具有實質上平面表面，金屬層821具有實質上平面表面，且障壁層822具有實質上平面表面。彈性類球面芯820之實質上平面表面、金屬層821之實質上平面表面及障壁層822之實質上平面表面藉由封裝體13暴露。電連接件82進一步包含圍繞障壁層822之焊料層823。焊料層823具有實質上平面表面。焊料層823之實質上平面表面亦藉由封裝體13暴露。 圖9A、圖9B及圖9C說明根據本發明之一些實施例的製造表面黏著結構之方法之各種階段。圖9A說明已經經由以下階段處理之基板(例如，重佈結構) 11：烘烤基板條帶；藉由表面黏著技術(SMT)將電子組件16安裝於基板條帶上；將電連接件12安裝於基板條帶上；將基板條帶鋸割成個別基板11；及將基板11安置於載體19上。 如圖9B中所示，接著對基板11執行以下階段：藉由覆晶(FC)接合將晶粒14安裝至基板11上；回焊焊料；助熔劑清洗；分散底膠(UF) 17；及固化UF 17。 如圖9C中所示，薄膜型模製化合物(例如，封裝體) 13經應用於基板11、電連接件12及晶粒14上。最終，執行以下階段以形成一或多個表面黏著結構(例如，如圖1A中所示之表面黏著結構)：解包帶及藉由鋸割成個別封裝結構而單體化。 圖10A、圖10B及圖10C說明根據本發明之一些實施例的製造表面黏著結構之方法之各種階段。圖10A、圖10B及圖10C中所示之方法在某些態樣類似於圖9A、圖9B及圖9C中所示之方法，不同之處在於在圖10A、圖10B及圖10C中，基板條帶20不會在模製之前鋸割成個別基板。因此，在圖10A、圖10B及圖10C中所示之方法中不使用載體。圖10C中所示之基板條帶20藉由鋸割成個別封裝結構而單體化以形成一或多個表面黏著結構(例如，如圖1B中所示之表面黏著結構10)。 圖11A、圖11B及圖11C說明根據本發明之一些實施例的製造表面黏著結構之方法之各種階段。圖11A、圖11B及圖11C中所示之方法在某些態樣類似於圖9A、圖9B及圖9C中所示之方法，不同之處在於晶粒14藉由線接合安裝至基板11上。因此，在一些實施例中，可省略以下階段：焊料回焊；助熔劑清洗；底膠(UF) 17分散；及UF 17固化。在一些實施例中，執行以下階段以形成一或多個表面黏著結構(例如，如圖2A中所示之表面黏著結構10)：解包帶及藉由鋸割成個別封裝結構而單體化。在一些實施例中，圖2B中之表面黏著結構10亦可使用在某些態樣與圖11A、圖11B及圖11C中所示之方法類似的方法來製造，不同之處在於基板條帶在模製之前不會經鋸割成個別基板。 圖12說明根據本發明之一些實施例的電子裝置90之橫截面圖。類似與圖1A中所示之表面黏著結構10之半導體裝置封裝10將藉由表面黏著技術安裝於外部電路板80上。半導體裝置封裝10包含重佈結構11、半導體裝置14、電連接件12及封裝體13。重佈結構11具有第一表面111及與該第一表面111相對之第二表面112。該半導體裝置14在該重佈結構11之第一表面111上。電連接件12在重佈結構11之第一表面111上。封裝體13囊封重佈結構11之第一表面111、半導體裝置14及電連接件12。電連接件12中之每一者之一部分藉由封裝體13暴露。 在一些實施例中，如圖12中所示之電子裝置90包含電路板80及半導體裝置封裝10。電路板80具有第一表面801。類似於圖1A中所示之表面黏著結構10之半導體裝置封裝10安裝於電路板80之第一表面801上。電連接件12中之每一者之經暴露部分直接安裝至且電連接至電路板80。在一些實施例中，圖1B、圖2A及圖2B中所示之表面黏著結構亦可以與圖12中所示相同之方式安裝於電路板80之第一表面801上。 圖13說明根據本發明之一些實施例的電子裝置90之橫截面圖。圖13中所示之電子裝置90在某些態樣類似於圖12中所示之電子裝置90，不同之處在於在圖13中，各電連接件62接地以在電連接件62之底部形成實質上平面表面624。半導體裝置封裝10與圖6A中所示之表面黏著結構10類似或相同。電連接件62之實質上平面表面624相對於封裝體13之表面131突出。 圖14說明根據本發明之一些實施例的電子裝置90之橫截面圖。圖14中所示之電子裝置90在某些態樣類似於圖12中所示之電子裝置90，不同之處在於在圖14中，各電連接件72接地以在電連接件72之底部形成實質上平面表面724。半導體裝置封裝10與圖7A中所示之表面黏著結構10類似或相同。電連接件72之實質上平面表面724與封裝體131之表面131實質上共面。 圖15說明根據本發明之一些實施例的表面黏著結構10之橫截面圖。表面黏著結構10包含重佈結構11、電連接件12、封裝體13、半導體裝置14、凸塊15、電子組件16、底填充層17及封裝結構91。重佈結構11具有表面111及與表面111相對之表面112。電連接件12中之至少一者在重佈結構11之表面111上。在一些實施例中，表面黏著結構10進一步包含鄰近於重佈結構11之表面112的感測區域18。感測區域18可用於(例如)指紋感測或任何其他光感測目的。 半導體裝置14安裝於重佈結構11之表面111上。半導體裝置14及重佈結構11由凸塊15電連接。在一些實施例中，凸塊之間的空間以底填充層17填充。封裝結構91具有表面911及與表面911相對之表面912。重佈結構11安裝於封裝結構91之表面911上。電連接件12用於將重佈結構11與封裝結構91電連接。 電子組件16 (例如，電阻器或電容器)亦安裝於封裝結構91之表面911上。封裝體13囊封重佈結構11之表面111、電連接件12及封裝結構91之表面911。封裝結構91進一步包含在封裝結構91之表面912上的墊913。墊913用於扇出半導體裝置14之輸入及輸出。 與圖1A、圖1B、圖2A、圖2B、圖4、圖6A、圖7A及圖8A中所示之表面黏著結構10相比較，圖15中所示之表面黏著結構10之厚度可較大，因為在圖15中所示之表面黏著結構10中存在兩個基板(例如，基板11及基板91)。在圖15中所示之表面黏著結構10之製造期間，可執行關於將重佈結構11安裝至封裝結構91之階段，由此增加製造成本。 圖16說明根據本發明之一些實施例的電子裝置90之橫截面圖。電子裝置90包含電路板80及半導體裝置封裝10。電路板80具有第一表面801。類似於圖15中所示之表面黏著結構10之半導體裝置封裝10安裝於電路板80之第一表面801上。與圖12、圖13及圖14中所示之電子裝置90相比較，圖16中所示之電子裝置90之厚度可較大，因為在圖16中所示之電子裝置90中存在兩個基板(例如，基板11及基板91)。 如本文中所使用，相對術語，諸如「內」、「內部」、「外」、「外部」、「頂部」、「底部」、「前」、「後」、「上」、「向上」、「下」、「向下」、「豎直」、「豎直地」、「側向」、「側向地」、「在...上方」及「在...下方」係指一組組件關於彼此之定向；此定向係根據圖式，而非係製造或使用期間所需要的。 除非本文另外明確規定，否則如本文所用，單數形式「一(a/an)」及「該」可包括複數個指示物。 如本文中所使用，術語「連接(connect/connected/connection)」係指可操作性耦接或鏈接。經連接組件可(例如)經由另一組組件直接或間接地耦接至彼此。 如本文所使用，術語「導電(conductive/electrically conductive)」、及「導電率」係指輸送電流之能力。導電材料通常指示展現對於電流流動之極小或無反作用之彼等材料。導電率之一個量度為西門子/米(S/m)。通常，導電材料為具有大於約104 S/m (諸如至少105 S/m或至少106 S/m)之導電率的一種材料。材料之導電率有時可隨溫度變化。除非另外規定，否則材料之導電率係在室溫下量測。 如本文中所使用，術語「大致」、「實質上」、「實質」及「約」係指相當大的程度或範圍。當與事件或情況結合使用時，術語可指事件或情況精確發生之例項以及事件或情況近似地發生之例項，諸如解釋本文中所描述之製造方法之典型容限水平。舉例而言，當結合數值使用時，該等術語可指小於或等於該數值之±10%的變化範圍，諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或者小於或等於±0.05%。舉例而言，若兩個數值之間的差小於或等於該等值之平均值的±10% (諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%)，則可認為該等值「實質上」相同。 若兩個表面之間的移位不大於5 μm、不大於2 μm、不大於1 μm或不大於0.5 μm，則可認為該兩個表面共面或實質上共面。 若表面上之最高點與最低點之間的差不大於5 μm、不大於2 μm、不大於1 µm或不大於0.5 μm，則可認為該表面係平面或實質上平面的。 另外，有時在本文中按範圍格式呈現量、比率及其他數值。應理解，此類範圍格式為了便利及簡潔起見而使用，且應靈活地解釋為包括明確地指定為範圍限值之數值，以及包括涵蓋於該範圍內之所有個別數值或子範圍，如同明確地指定每一數值及子範圍一般。 在對一些實施例之描述中，提供「在」另一組件「上」之一組件可涵蓋前一組件直接在後一組件上(例如，與後一組件實體接觸)的狀況以及一或多個介入組件位於前一組件與後一組件之間的狀況。 儘管已參考本發明之特定實施例描述並說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍定義的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。 如各種實例實施例中所展示之結構及方法之構造及配置僅為說明性的。因此，所有此等修改意欲包括於本發明之範疇內。任何過程或方法步驟之次序或順序可根據替代實施例變化或重新定序。可在不脫離本發明之範疇的情況下在實例實施例之設計、操作條件及配置上進行其他替代、修改、改變及省略。
10‧‧‧表面黏著結構/半導體裝置封裝
11‧‧‧重佈結構/基板
12‧‧‧電連接件
13‧‧‧封裝體
14‧‧‧半導體裝置
15‧‧‧凸塊
16‧‧‧電子組件
17‧‧‧底填充層
18‧‧‧感測區域
19‧‧‧載體
25‧‧‧接線
42‧‧‧電連接件
50‧‧‧球面空間
62‧‧‧電連接件
72‧‧‧電連接件
80‧‧‧外部電路板
82‧‧‧電連接件
90‧‧‧電子裝置
91‧‧‧封裝結構
111‧‧‧表面
112‧‧‧表面
121‧‧‧金屬芯或球體
122‧‧‧障壁層
123‧‧‧焊料層
131‧‧‧表面
420‧‧‧彈性球體或芯
421‧‧‧金屬層
422‧‧‧障壁層
423‧‧‧焊料層
621‧‧‧金屬類球面芯
622‧‧‧障壁層
623‧‧‧焊料層
624‧‧‧實質上平面表面
721‧‧‧金屬類球面芯
722‧‧‧障壁層
723‧‧‧焊料層
724‧‧‧實質上平面表面
801‧‧‧第一表面
820‧‧‧彈性類球面芯
821‧‧‧金屬層
822‧‧‧障壁層
823‧‧‧焊料層
824‧‧‧實質上平面表面
911‧‧‧表面
912‧‧‧表面
913‧‧‧墊
圖1A說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖1B說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖2A說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖2B說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖3說明根據本發明之一些實施例的表面黏著結構之電連接件之橫截面圖； 圖4說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖5說明根據本發明之一些實施例的表面黏著結構之電連接件之橫截面圖； 圖6A說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖6B說明根據本發明之一些實施例的圖6A之表面黏著結構之仰視圖； 圖7A說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖7B說明根據本發明之一些實施例的圖7A之表面黏著結構之仰視圖； 圖8A說明根據本發明之一些實施例的表面黏著結構之橫截面圖； 圖8B說明根據本發明之一些實施例的圖8A之表面黏著結構之仰視圖； 圖9A說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖9B說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖9C說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖10A說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖10B說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖10C說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖11A說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖11B說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖11C說明根據本發明之一些實施例的製造表面黏著結構之方法之一或多個階段； 圖12說明根據本發明之一些實施例的電子裝置之橫截面圖； 圖13說明根據本發明之一些實施例的電子裝置之橫截面圖； 圖14說明根據本發明之一些實施例的電子裝置之橫截面圖； 圖15說明根據本發明之一些實施例的表面黏著結構之橫截面圖；及 圖16說明根據本發明之一些實施例的電子裝置之橫截面圖。 貫穿圖式及實施方式使用共同參考編號以指示相同或類似組件。本發明將自以下結合隨附圖式所作之詳細描述更顯而易見。

Claims (28)

  1. 一種表面黏著結構，其包含： 一重佈結構，其具有一第一表面及與該第一表面相對之一第二表面； 在該重佈結構之該第一表面上之一電連接件；及 一封裝體，其囊封該重佈結構之該第一表面及該電連接件； 其中該電連接件之一部分藉由該封裝體暴露。
  2. 如請求項1之表面黏著結構，其中該電連接件包含一芯。
  3. 如請求項2之表面黏著結構，其中該芯包含一金屬芯及圍繞該金屬芯之一障壁層。
  4. 如請求項3之表面黏著結構，其中該電連接件進一步包含圍繞該障壁層之一焊料層。
  5. 如請求項2之表面黏著結構，其中該芯包含一彈性芯及圍繞該彈性芯之一金屬層。
  6. 如請求項5之表面黏著結構，其中該芯進一步包含圍繞該金屬層之一障壁層。
  7. 如請求項6之表面黏著結構，其中該電連接件進一步包含圍繞該障壁層之一焊料層。
  8. 如請求項5之表面黏著結構，其中該彈性芯具有範圍自大致1吉帕斯卡(GPa)至大致50 GPa之一彈性模數。
  9. 如請求項5之表面黏著結構，其中該彈性芯具有範圍自大致3 GPa至大致6 GPa之一彈性模數。
  10. 如請求項5之表面黏著結構，其中該彈性芯包含一聚合物。
  11. 如請求項5之表面黏著結構，其中該金屬層定義一空間且該彈性芯之至少一部分藉由該空間與該金屬層分離。
  12. 如請求項5之表面黏著結構，其中該金屬層定義具有大於1之一縱橫比的一空間。
  13. 如請求項1之表面黏著結構，其中該封裝體具有一第一表面且該電連接件具有一實質上平面表面，且其中該電連接件之該實質上平面表面相對於該封裝體之該第一表面突出。
  14. 如請求項1之表面黏著結構，其中該封裝體具有一第一表面且該電連接件具有一實質上平面表面，且其中該電連接件之該實質上平面表面與該封裝體之該第一表面實質上共面。
  15. 如請求項1之表面黏著結構，其中該電連接件包含一金屬芯及圍繞該金屬芯之一障壁層，且其中該金屬芯具有一第一實質上平面表面且該障壁層具有一第一實質上平面表面，且其中該金屬芯之該第一實質上平面表面及該障壁層之該第一實質上平面表面藉由該封裝體暴露。
  16. 如請求項15之表面黏著結構，其中該電連接件進一步包含圍繞該障壁層之一焊料層，且其中該焊料層具有一第一實質上平面表面且其中該焊料層之該第一實質上平面表面藉由該封裝體暴露。
  17. 如請求項1之表面黏著結構，其進一步包含鄰近於該重佈結構之該第二表面之一感測區域。
  18. 如請求項1之表面黏著結構，其中該電連接件之該暴露部分具有一實質上平面表面。
  19. 一種半導體裝置封裝，其包含： 一重佈結構，其具有一第一表面及與該第一表面相對之一第二表面； 在該重佈結構之該第一表面上之一半導體裝置； 在該重佈結構之該第一表面上之一電連接件；及 一封裝體，其囊封該重佈結構之該第一表面、該半導體裝置及該電連接件； 其中該電連接件之一部分藉由該封裝體暴露。
  20. 如請求項19之半導體裝置封裝，其中該封裝體具有一第一表面且該電連接件具有一實質上平面表面，且其中該電連接件之該實質上平面表面相對於該封裝體之該第一表面突出。
  21. 如請求項19之半導體裝置封裝，其中該封裝體具有一第一表面且該電連接件具有一實質上平面表面，且其中該電連接件之該實質上平面表面與該封裝體之該第一表面實質上共面。
  22. 如請求項19之半導體裝置封裝，其中該電連接件包含一金屬芯及圍繞該金屬芯之一障壁層，且其中該金屬芯具有一第一實質上平面表面且該障壁層具有一第一實質上平面表面，且其中該金屬芯之該第一實質上平面表面及該障壁層之該第一實質上平面表面藉由該封裝體暴露。
  23. 如請求項22之半導體裝置封裝，其中該電連接件進一步包含圍繞該障壁層之一焊料層，且其中該焊料層具有一第一實質上平面表面且其中該焊料層之該第一實質上平面表面藉由該封裝體暴露。
  24. 如請求項19之半導體裝置封裝，其進一步包含鄰近於該重佈結構之該第二表面之一感測區域。
  25. 如請求項19之半導體裝置封裝，其中該電連接件之該暴露部分具有一實質上平面表面。
  26. 一種電子裝置，其包含： 一電路板，其具有一第一表面；及 一半導體裝置封裝，其安裝在該電路板之該第一表面上，該半導體裝置封裝包含： 一重佈結構，其具有一第一表面及與該第一表面相對之一第二表面； 在該重佈結構之該第一表面上之一半導體裝置； 在該重佈結構之該第一表面上之一電連接件；及 一封裝體，其囊封該重佈結構之該第一表面、該半導體裝置及該電連接件； 其中該電連接件之一部分藉由該封裝體暴露。
  27. 如請求項26之電子裝置，其中該電連接件之該暴露部分經安裝至該電路板之該第一表面。
  28. 如請求項26之電子裝置，其中該電連接件之該暴露部分具有一實質上平面表面。
TW106134704A 2016-10-17 2017-10-11 改良之扇出球狀柵格陣列封裝結構及其製造方法 TWI756275B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662409252P 2016-10-17 2016-10-17
US62/409,252 2016-10-17
US15/655,724 2017-07-20
US15/655,724 US10242940B2 (en) 2016-10-17 2017-07-20 Fan-out ball grid array package structure and process for manufacturing the same

Publications (2)

Publication Number Publication Date
TW201816962A true TW201816962A (zh) 2018-05-01
TWI756275B TWI756275B (zh) 2022-03-01

Family

ID=61904761

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106134704A TWI756275B (zh) 2016-10-17 2017-10-11 改良之扇出球狀柵格陣列封裝結構及其製造方法

Country Status (3)

Country Link
US (1) US10242940B2 (zh)
CN (1) CN107958893B (zh)
TW (1) TWI756275B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10242940B2 (en) * 2016-10-17 2019-03-26 Advanced Semiconductor Engineering, Inc. Fan-out ball grid array package structure and process for manufacturing the same
US10522505B2 (en) * 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
JP7251951B2 (ja) * 2018-11-13 2023-04-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US11387210B2 (en) * 2019-03-15 2022-07-12 Fuji Electric Co., Ltd. Semiconductor module and manufacturing method therefor
US11664300B2 (en) * 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080173792A1 (en) * 2007-01-23 2008-07-24 Advanced Chip Engineering Technology Inc. Image sensor module and the method of the same
JP4453763B2 (ja) * 2007-10-19 2010-04-21 セイコーエプソン株式会社 電子部品とその実装構造及び実装方法
US20110221018A1 (en) * 2010-03-15 2011-09-15 Xunqing Shi Electronic Device Package and Methods of Manufacturing an Electronic Device Package
US9966350B2 (en) * 2011-06-06 2018-05-08 Maxim Integrated Products, Inc. Wafer-level package device
KR101419600B1 (ko) * 2012-11-20 2014-07-17 앰코 테크놀로지 코리아 주식회사 지문인식센서 패키지 및 그 제조 방법
US9406533B2 (en) 2013-06-27 2016-08-02 STATS ChipPAC Pte. Ltd. Methods of forming conductive and insulating layers
US9305877B1 (en) * 2014-10-30 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package with through substrate vias
US10242940B2 (en) * 2016-10-17 2019-03-26 Advanced Semiconductor Engineering, Inc. Fan-out ball grid array package structure and process for manufacturing the same

Also Published As

Publication number Publication date
CN107958893B (zh) 2020-09-11
US20180108602A1 (en) 2018-04-19
TWI756275B (zh) 2022-03-01
US10242940B2 (en) 2019-03-26
CN107958893A (zh) 2018-04-24

Similar Documents

Publication Publication Date Title
TWI756275B (zh) 改良之扇出球狀柵格陣列封裝結構及其製造方法
US7372151B1 (en) Ball grid array package and process for manufacturing same
US6781242B1 (en) Thin ball grid array package
US12009343B1 (en) Stackable package and method
US7476976B2 (en) Flip chip package with advanced electrical and thermal properties for high current designs
CN203644756U (zh) 半导体装置
US7573137B2 (en) Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
JP5227501B2 (ja) スタックダイパッケージ及びそれを製造する方法
US20070254406A1 (en) Method for manufacturing stacked package structure
US20110244633A1 (en) Package assembly for semiconductor devices
CN103703549A (zh) 用于直接表面安装的裸露芯片封装
US7692276B2 (en) Thermally enhanced ball grid array package formed in strip with one-piece die-attached exposed heat spreader
US9666506B2 (en) Heat spreader with wiring substrate for reduced thickness
US11682653B2 (en) Semiconductor device package and method for manufacturing the same
US11869829B2 (en) Semiconductor device with through-mold via
US9412729B2 (en) Semiconductor package and fabricating method thereof
US7696618B2 (en) POP (package-on-package) semiconductor device
US11495531B2 (en) Semiconductor device package and method of manufacturing the same
US11862585B2 (en) Semiconductor package structures and methods of manufacturing the same
US20100289145A1 (en) Wafer chip scale package with center conductive mass
CN108447829B (zh) 封装结构及其制法
US20120326304A1 (en) Externally Wire Bondable Chip Scale Package in a System-in-Package Module
US20120292756A1 (en) Semiconductor device with heat spreader
US9761435B1 (en) Flip chip cavity package
KR100876864B1 (ko) 양방향 입출력 단자를 갖는 반도체 패키지 및 그 제조 방법