CN107863332A - 电子器件、电子模块及其制造方法 - Google Patents

电子器件、电子模块及其制造方法 Download PDF

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Publication number
CN107863332A
CN107863332A CN201710854614.XA CN201710854614A CN107863332A CN 107863332 A CN107863332 A CN 107863332A CN 201710854614 A CN201710854614 A CN 201710854614A CN 107863332 A CN107863332 A CN 107863332A
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China
Prior art keywords
layer
semiconductor substrate
metal stack
stack body
electronic module
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CN201710854614.XA
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CN107863332B (zh
Inventor
G·阿德马
T·贝尔托
M·埃曼
P·弗兰克
E·格雷茨
K·卡尔洛夫斯基
E·纳佩特施尼格
W·罗布尔
T·施密特
J·塞弗特
F·瓦格纳
S·韦勒特
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to CN202110735338.1A priority Critical patent/CN113471162A/zh
Publication of CN107863332A publication Critical patent/CN107863332A/zh
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Publication of CN107863332B publication Critical patent/CN107863332B/zh
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

示出了一种电子器件、一种包括所述电子器件的电子模块及其制造方法。所述电子器件包括半导体衬底和设置在所述半导体衬底上的金属堆叠体，其中，所述金属堆叠体包括第一层，其中，所述第一层包括NiSi。

Description

电子器件、电子模块及其制造方法
技术领域
本发明涉及一种电子器件、一种电子模块及其制造方法。
背景技术
电子器件的制造商不断努力提高其产品性能，同时努力降低其制造成本。在电子器件或电子模块的制造中的成本密集区域是布置在半导体衬底的表面上的金属堆叠体的制备。背侧金属化(BSM：BackSide Metallization)可以是这种金属堆叠体的一个示例。这种金属堆叠体可以包括当将半导体衬底焊接到载体时与焊料层反应的第一层。这种金属堆叠体的改进、例如第一层的改进以及改良的焊接方法可能有助于降低制造成本、提高焊点的可靠性并减少晶片翘曲和芯片翘曲。由于这些和其它原因，需要本发明。
发明内容
根据本发明的一个方面，提供了一种电子器件，包括半导体衬底以及设置在所述半导体衬底上的金属堆叠体，所述金属堆叠体包括：第一层，其中，所述第一层包含NiSi。
根据本发明的一个可选实施例，所述半导体衬底包括功率半导体芯片、IGBT和二极管中的一种或两种以上，所述金属堆叠体布置在所述功率半导体芯片的、IGBT的或二极管的芯片焊盘上。
根据本发明的一个可选实施例，所述金属堆叠体在所述第一层中包含N杂质、特别是成NiN和SiN中的一种或两种以上形式。
根据本发明的一个可选实施例，所述金属堆叠体还包括设置在所述第一层与所述半导体衬底之间的第二层、特别是包括以下材料中的一种或两种以上的第二层：Ti、WTi、Ta或包括这些材料中的至少一种的合金。
根据本发明的一个可选实施例，所述金属堆叠体还包括设置在所述第一层上的第三层、特别是包括Ag、Pt、Pd和Au中的一种或两种以上的第三层。
根据本发明的一个可选实施例，所述金属堆叠体还包括设置在所述半导体衬底与所述第一层之间的第四层、特别是包括Al和Ti中的一种或两种以上的第四层。
根据本发明的一个可选实施例，所述第一层具有在50nm至2000nm、特别是100nm至1000nm、更特别是200nm至600nm、甚至更特别是400nm至500nm范围内的厚度。
根据本发明的一个可选实施例，所述第一层包含在2wt％至50wt％、特别是2wt％至20wt％、更特别是3wt％至10wt％、更特别是4wt％至5wt％范围内的Si量，甚至更特别是4.5wt％的Si量。
根据本发明的另一个方面，提供了一种电子模块，包括：载体；设置在载体上的半导体芯片；设置在所述载体与所述半导体衬底之间的金属堆叠体，所述金属堆叠包括第一层；以及设置在第一层上的焊料层，其中，所述第一层包含NiSi。
根据本发明的一个可选实施例，所述载体包括功率电子衬底、引线框架、DCB、DAB、AMB、IMS或PCB。
根据本发明的一个可选实施例，所述电子模块还包括包封半导体芯片的包装体。
根据本发明的一个可选实施例，所述焊料层包括基于Pb或无Pb焊料。
根据本发明的一个可选实施例，所述焊料层包括Sn或SnAg。
根据本发明的一个可选实施例，所述电子模块还包括形成在所述第一层与所述焊料层之间的金属间相。
根据本发明的一个可选实施例，所述金属堆叠体包括N杂质。
根据本发明的一个可选实施例，N杂质沿所述第一层与所述焊料层之间的界面定位。
根据本发明的又一个方面，提供了一种用于制造电子模块的方法，包括：提供载体和半导体衬底，在所述半导体衬底上设置第一层，在所述第一层与所述载体之间设置焊料层，以及将所述半导体衬底焊接到所述载体上，其中，所述第一层包含NiSi，以及其中，在所述半导体衬底上设置所述第一层包括在存在包含N的工艺气体的情况下溅射。
根据本发明的一个可选实施例，溅射包括磁控溅射工艺。
根据本发明的一个可选实施例，所述工艺气体中的N的量约为80％、或70％、或60％、或50％、或40％、或30％、或20％、或10％或5％。
根据本发明的一个可选实施例，所述工艺气体还包含Ar、Xe、Kr或Ne。
附图说明
包括附图以提供对实施例的进一步理解，结合附图并构成该描述的一部分。附图说明了实施例，并且与描述一起用于解释实施例的原理。通过参考以下详细描述，可以更好地理解其它实施例和实施例的许多预期优点。附图的元件不一定相对于彼此成比例。相同的附图标记指代相应的类似部分。
图1示意性地示出了根据本发明的一种电子器件的一个示例的横截面图。
图2示意性地示出了根据本发明的一种电子模块的一个示例的横截面图。
图3示出了根据本发明的一种用于制造电子器件的方法的流程图。
图4示出了根据本发明的一种用于制造电子模块的方法的流程图。
具体实施方式
在以下详细描述中，参考了构成说明书的一部分的附图，所述附图通过图示说明可以实施本发明的具体实施例。然而，对于本领域技术人员来说，可以显见，可以以较小程度的具体细节来实施实施例的一个或多个方面。在其它情况下，以示意图形式示出已知的结构和元件，以便于描述实施例的一个或多个方面。在这点上，参考所描述的图的取向使用诸如“顶”、“底”、“左”、“右”、“上”、“下”等的方向性术语。因为实施例的部件可以以多个不同的取向定位，所以方向性术语用于说明的目的，而不是限制性的。应当理解，在不脱离本发明的范围的情况下，可以利用其它实施例，并且可以进行结构或逻辑改变。
此外，尽管可以仅针对几个实施方式中的一个来公开实施例的特定特征或方面，但是对于任何给定的或特定的应用可能期望和有利的是，这样的特征或方面可以与其它实施方式的一个或两个以上的其它特征或方面组合，除非明确指出不能如此或除非在技术上受到限制。可以使用术语“耦合”和“连接”以及其派生词。应当理解，这些术语可以用于指示两个元件彼此协作或相互作用，而不管它们彼此是直接的物理接触或电接触，还是彼此不直接接触；可以在“结合”、“附连”或“连接”元件之间提供中间元件或层。
下面进一步描述的半导体衬底或半导体芯片可以是不同类型的，并且可以通过不同的技术制造。电子器件和电子模块以及电子器件和电子模块的制造方法的实施例可以使用各种类型的半导体芯片或合并到半导体芯片中的电路，它们例如可以为AC/DC或DC/DC变换器电路、功率MOS晶体管、功率肖特基二极管、JFET(结栅场效应晶体管：Junction GateField Effect Transistor)、功率双极晶体管、逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS(微机电系统：Micro-Electro-Mechanical-System)、功率集成电路、具有集成的无源器件的芯片等。实施例也可以使用例如包括MOS晶体管结构或垂直晶体管结构的半导体芯片，例如IGBT(绝缘栅双极晶体管：Insulated Gate BipolarTransistor)结构、二极管或者总体上讲的至少一个电接触焊盘布置在半导体芯片的第一主面上以及至少一个其它的电接触焊盘布置在半导体芯片的与半导体芯片的第一主面相反的第二主面上的晶体管结构。此外，绝缘材料的实施例可以例如用于在电路和部件的各种类型封闭或绝缘中提供绝缘层和/或用于在各种类型的半导体芯片或合并到半导体芯片中的电路(包括以上提到的半导体芯片和电路)中提供绝缘层。
本文考虑的半导体衬底或半导体芯片可能是薄型的。半导体衬底或半导体芯片可以由特定的半导体材料、例如Si、SiC、SiGe、GaAs、GaN或任何其它半导体材料制成，此外，可以例如包含一种或两种以上的不是半导体材料的无机材料和有机材料，例如绝缘体、塑料或金属。
半导体衬底或芯片可以具有允许与半导体衬底或芯片中包括的集成电路电接触的接触焊盘(或电极)。所述电极可以全部仅布置在半导体衬底或芯片的一个主面处或者布置在两个主面处。它们可以包括施加到半导体材料的一个或两个以上电极金属层。所述电极金属层可以以任何期望的几何形状和任何期望的材料组分制造。例如，它们可以包括或由选自以下组的材料制成：Cu、Ni、NiSn、Au、Ag、Pt、Pd、这些金属中的一种或两种以上的合金、导电有机材料或导电半导体材料。
半导体衬底或芯片可以结合到载体。所述载体可以是用于封装的(永久性的)器件载体。所述载体可以例如包括或由任何种类的材料、例如陶瓷或金属材料、铜或铜合金或铁/镍合金组成。所述载体可以包括功率电子衬底、引线框架、DCB(直接铜结合：DirectCopper Bond)、DAB(直接铝结合：Direct Aluminum Bond)、AMB(活性金属硬焊：ActiveMetal Braze)衬底、IMS(绝缘金属衬底：Insulated Metal Substrate)或PCB(印刷电路板：Printed Circuit Board)。所述载体可以与所述半导体衬底或芯片的一个接触元件机械连接和电连接。所述半导体衬底或芯片可以通过焊接、例如通过回流焊接、真空焊接和扩散焊接中的一种或两种以上连接到载体。如果扩散焊接用作半导体衬底或半导体芯片与载体之间的连接技术，则可以使用在焊接工艺之后由于界面扩散过程导致半导体与载体之间的界面处的金属间相的焊料材料。可以使用软的焊料材料或特别是能够形成扩散焊料结合的焊料材料，例如包括选自Sn、SnAg、SnAu、SnCu、In、InAg、InCu和InAu组中的一种或两种以上金属材料的焊料材料。所述焊料材料可以包括Pb，或者可以使用无Pb焊料材料。
电子模块可以包括覆盖半导体芯片的封装材料。封装材料可以是电绝缘的。封装材料可以例如包括或由任何合适的塑料或聚合物材料、例如硅凝胶、硬质塑料、热塑性或热固性材料或层压材料(预浸料)制成，并可例如包含填充料。可以采用各种技术、例如压塑成型、注射成型、粉末成型、液态成型或层压来用封装材料封装半导体芯片。可以使用热量和/或压力来施加封装材料。
在几个实施例中，将多个层或层堆叠体彼此施加或将材料施加或沉积到层上。应当理解，任何诸如“施加”或“沉积”这样的术语旨在字面上涵盖将层施加到彼此上的所有种类和技术。特别地，它们旨在涵盖层作为一个整体一次施加的技术、例如层压技术以及以顺序方式沉积层的技术、例如溅射、镀覆、模制成型、CVD等。
以下公开了包括设置在半导体衬底或半导体芯片上的金属堆叠体的电子器件的示例。所述金属堆叠体可以设置在半导体衬底的背侧。所述金属堆叠体可以设置在半导体衬底的芯片焊盘上，并且可以被配置为在芯片焊盘与半导体衬底附接到的载体之间提供电连接。所述金属堆叠体可以包括单一的金属层，或者它可以包括多层金属层、例如两层、三层、四层或多于四层。金属堆叠体可以具有任何合适的尺寸或形式。所述金属堆叠体可以完全覆盖半导体衬底的表面，或者它可以仅部分地覆盖所述表面。
金属堆叠体可以包括配置成在焊接期间用作焊料沉积物的反应配物的第一层。第一层可以包括镍硅(NiSi)复合物，并且可以特别地由NiSi组成。与其它材料、例如纯镍或镍钒(Ni)复合物相比，NiSi作为第一层可以表现出更优异的性能。例如，与Ni或NiV相比，NiSi在焊接过程中与Sn反应较慢。特别地，如果进行相同的焊接工艺，消耗的NiV是NiSi的大约两倍。因此，与NiV相比，在金属堆叠体中可以使用更薄的NiSi层。这可以减少金属堆叠体的制造时间和成本，并且还可以最小化由半导体衬底和金属堆叠体的热膨胀系数(CTE：Coefficient of Thermal Expansion)的差异引起的晶片翘曲或芯片翘曲。
可以使用本领域中已知的多种沉积技术来制造第一层。例如，可以使用磁控溅射来制造第一层。与纯Ni不同，NiSi不是铁磁性的，因此不会干扰沉积室的磁控管。
可以在存在工艺气体的情况下进行磁控溅射。工艺气体可以包括惰性气体、例如Ar、Xe、Kr或Ne。根据本发明的一个方面，工艺气体可以包括N(氮)。工艺气体可以例如包括约5％、10％、20％、30％、40％、50％、60％、70％、80％或甚至大于80％的N。工艺气体的其余部分可以由Ar构成。在磁控溅射期间工艺气体中的N的存在可以导致N杂质掺入金属堆叠体中。例如，可以将N杂质掺入到第一层中。N可以掺入到包含NiSi的第一层中，使得在第一层中形成NiN和SiN中的一种或两种以上。N可以对金属堆叠体的性能产生积极地影响、例如对金属堆叠体与载体之间的焊点的质量产生积极地影响。
图1示出了根据本发明的第一方面的电子器件100的一个示例。电子器件100包括半导体衬底110和设置在半导体衬底的第一表面110A上的金属堆叠体120。半导体衬底110可以包括半导体晶片或单个半导体芯片。第一表面110A可以是半导体衬底110的背侧。半导体衬底可以包括布置在第一表面110A上的芯片焊盘(未示出)，并且金属堆叠体120可以设置在芯片焊盘上并电连接到芯片焊盘。
金属堆叠体120可以完全覆盖第一表面110A或者如图1所示它可以仅部分地覆盖第一表面110A。金属堆叠体120可以具有任何适当的形状且相对于第一表面110A侧向或垂直方向具有任何适当的尺寸。金属堆叠体120可以被结构化或未被结构化。如上所述，金属堆叠体120可以包括N杂质。
金属堆叠体120可以包括第一层126，其中，第一层126包括或由NiSi组成。第一层126可以根据对第一层126的相应要求而具有任何合适的厚度，其中，沿垂直于第一表面110A的方向测量厚度。第一层126可以具有在50nm至2000nm、特别是100nm至1000nm、更特别是200nm至600nm、甚至更特别是400nm至500nm范围内的厚度。第一层126的厚度也可以是约300nm或恰好是300nm。
第一层126包含的Si量可在第一层126的材料总量的2wt％(2重量百分数)至50wt％、特别是2wt％至20wt％、更特别是3wt％至10wt％、更特别是4wt％至5wt％的范围内，甚至更特别是约4.5wt％或恰好是4.5wt％。
金属堆叠体120可以包括除第一层126之外的附加层。例如，金属堆叠体可以包括设置在第一层126上的第三层128。第三层128可以配置为保护第一层126免受腐蚀。第三层可以包括或由任何合适的材料或材料复合物组成。例如，第三层可以包括或由Ag、Pt、Pd和Au中的一种或两种以上组成。第三层128可以具有任何合适的厚度，并且可以例如具有在50nm至2000nm、特别是100nm至1000nm、更特别是150nm至500nm、甚至更特别是200nm至300nm范围内的厚度。第三层128的厚度也可以是约200nm或恰好是200nm。
金属堆叠体120可以包括第二层124，其中，第二层124布置在第一层126与半导体衬底110之间。第二层124可以充当阻挡层并且可以防止杂质扩散到半导体衬底110中。第二层可以具有任何合适的厚度，例如约200nm或恰好是200nm的厚度。第二层124可以包括任何合适的材料，例如可以包括或由以下材料组成：Ti、WTi、Ta中的一种或两种以上或包括这些材料中的至少一种的合金。
金属堆叠体120可以包括布置在第一层126与半导体衬底110之间的第四层122。在金属堆叠体120包括第二层124的情况下，第四层122布置在第二层124与半导体衬底110之间。第四层122可以具有任何合适的厚度，例如在50nm至2000nm、特别是100nm至1000nm、更特别是200nm至600nm、甚至更特别是300nm至500nm范围内的厚度。第四层122的厚度也可以是约或恰好是400nm。第四层122可以包括任何合适的材料，例如可以包括或由Al和Ti中的一种或两种以上组成。
图2示出了根据本发明的电子模块200的一个示例。电子模块200包括电子器件100(包括半导体衬底110和金属堆叠体120')和电子器件100附连到的载体240。电子模块200还可以包括包封半导体衬底110的包封体250。
电子模块200还包括布置在载体240上并焊接到金属堆叠体120'的焊料层230。焊料层230可以例如包括SnAg或Sn。
除了通过将电子器件100焊接到焊料层230而引入的变化之外，电子模块200的金属堆叠体120'可以与图1的电子器件100的金属堆叠体120相同。根据电子模块200的一个示例，第一层126在焊接之后可以比在焊接之前更薄。第一层126可以例如薄四分之一、薄一半、薄四分之三或者在焊接之后在金属堆叠体120'中甚至可以没有第一层。除了一些在焊接之后可以保留在金属堆叠体120'中的包含NiSi的贴片232之外，第一层也可能通过焊接工艺几乎完全消耗掉。贴片232可以沿着第一层与焊料层之间的界面定位。贴片232可以包含比前体第一层126更高的Si浓度，因为在焊接期间可能“提取出”Ni。例如，在第一层126包含4.5％的Si的情况下，贴片232可以包含约四倍的Si，或者换句话说可以包含约20％的Si。
根据电子模块200的一个示例，金属堆叠体120'可以包括在第一层126与焊料层230之间形成的金属间相。
根据电子器件200的一个示例，金属堆叠体120'可以包括N杂质。N可以提高在金属堆叠体120'与焊料层230之间形成的焊点的质量。例如，在第一层126被焊接工艺完全消耗的情况下，电子模块200不会显示金属堆叠体120'从焊料层230分层的分层问题，因为金属堆叠体120'中的N可以抵消分层。在金属堆叠体120'包括贴片232的情况下，贴片232可以包括N、例如成NiN和SiN中的一种或两种以上的形式。
电子模块200的半导体衬底110可以包括在第一表面110A上的第一电极和在与第一表面110A相反的第二表面110B上的第二电极。电子模块200可以被配置为用于电流从第二电极垂直地流向第一电极并进一步穿过金属堆叠体120'到载体240。
图2所示的电子模块200仅示出一个半导体衬底110、一个金属堆叠体120'和一个载体240。然而，电子模块200的不同示例当然可以包括例如附加的半导体衬底、附加的金属堆叠体或附加的载体等附加的部件或其它合适的附加的部件。附加的部件可以相对于图2所示的部件并排布置和/或垂直堆叠布置。
图3示出了一种用于制造如图1的电子器件100的电子器件的方法300。方法300包括第一工艺步骤301，其中，第一工艺步骤301包括提供如半导体衬底110的半导体衬底。方法300还包括第二工艺步骤302，其中，第二工艺步骤302包括在半导体衬底上布置如金属堆叠体120的金属堆叠体。
在第二工艺步骤302中的金属堆叠体的布置可以包括将第一层溅射到半导体衬底上。溅射可以如上所述在存在包含N的工艺气体的情况下进行。
在第二工艺步骤302中的金属堆叠体的布置还可以如上所述包括将N杂质掺入到金属堆叠体中。
图4示出了一种用于制造如图2的电子模块200的电子模块的方法400。方法400包括第一工艺步骤401，其中，第一工艺步骤401包括提供半导体衬底和载体。方法400包括第二工艺步骤402，其中，第二工艺步骤402包括在半导体衬底上布置金属堆叠体。方法400包括第三工艺步骤403，其中，第三工艺步骤403包括在载体上布置焊料层。方法400包括第四工艺步骤404，其中，第四工艺步骤404包括将半导体衬底焊接到载体上。
虽然已经针对一个或多个实施例示出和描述了本发明，但是在不脱离所附权利要求的精神和范围的情况下，可以对所示示例进行改变和/或修改。特别是关于由上述部件或结构(组件、器件、电路、系统等)执行的各种功能，除非另有说明，否则用于描述这些部件的术语(包括对“方法”的引用)旨在对应于执行所述部件的指定功能的任何部件或结构(例如，功能上相同)，即使在结构上不等同于在本文所示的本发明的示例性实施方式中执行功能的所公开的结构。

Claims (20)

1.一种电子器件，包括：
半导体衬底，以及
设置在所述半导体衬底上的金属堆叠体，所述金属堆叠体包括：
第一层
其中，所述第一层包含NiSi。
2.根据权利要求1所述的电子器件，其中，所述半导体衬底包括功率半导体芯片、IGBT和二极管中的一种或两种以上，所述金属堆叠体布置在所述功率半导体芯片的、IGBT的或二极管的芯片焊盘上。
3.根据权利要求1或2所述的电子器件，其中，所述金属堆叠体在所述第一层中包含N杂质、特别是成NiN和SiN中的一种或两种以上形式。
4.根据前述权利要求中任一所述的电子器件，其中，所述金属堆叠体还包括设置在所述第一层与所述半导体衬底之间的第二层、特别是包括以下材料中的一种或两种以上的第二层：Ti、WTi、Ta或包括这些材料中的至少一种的合金。
5.根据前述权利要求中任一所述的电子器件，其中，所述金属堆叠体还包括设置在所述第一层上的第三层、特别是包括Ag、Pt、Pd和Au中的一种或两种以上的第三层。
6.根据前述权利要求中任一所述的电子器件，其中，所述金属堆叠体还包括设置在所述半导体衬底与所述第一层之间的第四层、特别是包括Al和Ti中的一种或两种以上的第四层。
7.根据前述权利要求中任一所述的电子器件，其中，所述第一层具有在50nm至2000nm、特别是100nm至1000nm、更特别是200nm至600nm、甚至更特别是400nm至500nm范围内的厚度。
8.根据前述权利要求中任一所述的电子器件，其中，所述第一层包含在2wt％至50wt％、特别是2wt％至20wt％、更特别是3wt％至10wt％、更特别是4wt％至5wt％范围内的Si量，甚至更特别是4.5wt％的Si量。
9.一种电子模块，包括：
载体，
设置在载体上的半导体芯片，
设置在所述载体与所述半导体衬底之间的金属堆叠体，所述金属堆叠包括：
第一层，以及
设置在第一层上的焊料层，
其中，所述第一层包含NiSi。
10.根据权利要求9所述的电子模块，其中，所述载体包括功率电子衬底、引线框架、DCB、DAB、AMB、IMS或PCB。
11.根据权利要求9或10所述的电子模块，其中，所述电子模块还包括包封半导体芯片的包装体。
12.根据权利要求9至11中任一项所述的电子模块，其中，所述焊料层包括基于Pb或无Pb焊料。
13.根据权利要求12所述的电子模块，其中，所述焊料层包括Sn或SnAg。
14.根据权利要求9至13中任一项所述的电子模块，其中，所述电子模块还包括形成在所述第一层与所述焊料层之间的金属间相。
15.根据权利要求9至14中任一项所述的电子模块，其中，所述金属堆叠体包括N杂质。
16.根据权利要求15所述的电子模块，其中，N杂质沿所述第一层与所述焊料层之间的界面定位。
17.一种用于制造电子模块的方法，包括：
提供载体和半导体衬底，
在所述半导体衬底上设置第一层，
在所述第一层与所述载体之间设置焊料层，以及
将所述半导体衬底焊接到所述载体上，
其中，所述第一层包含NiSi，以及
其中，在所述半导体衬底上设置所述第一层包括在存在包含N的工艺气体的情况下溅射。
18.根据权利要求17所述的方法，其中，溅射包括磁控溅射工艺。
19.根据权利要求17或18所述的方法，其中，所述工艺气体中的N的量约为80％、或70％、或60％、或50％、或40％、或30％、或20％、或10％或5％。
20.根据权利要求17至19中任一项所述的方法，其中，所述工艺气体还包含Ar、Xe、Kr或Ne。
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