CN117936500A - 电子封装件及其制法与基板结构 - Google Patents

电子封装件及其制法与基板结构 Download PDF

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CN117936500A
CN117936500A CN202211370330.0A CN202211370330A CN117936500A CN 117936500 A CN117936500 A CN 117936500A CN 202211370330 A CN202211370330 A CN 202211370330A CN 117936500 A CN117936500 A CN 117936500A
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substrate structure
layer
section
contact pad
electrical contact
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曹佳雯
谢雯贞
纪雅婷
蔡苡琳
简秀芳
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority claimed from TW111140684A external-priority patent/TW202418486A/zh
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

一种电子封装件及其制法与基板结构，该基板结构包括于具有多个电性接触垫的基板本体上形成绝缘保护层，且该绝缘保护层具有对应外露多个该电性接触垫的多个开孔，且令该绝缘保护层于至少一该开孔处形成有围绕至少一该电性接触垫局部边缘的镂空部，以减少该绝缘保护层的阻隔。

Description

电子封装件及其制法与基板结构
技术领域
本发明有关一种半导体制程用的基板结构，尤指一种具有防焊层的基板结构及其电子封装件与制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术亦随之开发出不同的封装型态。为满足半导体装置的高集成度(Integration)以及微型化(Miniaturization)需求，业界多采用覆晶(Flip chip)式封装结构。
图1A为现有半导体封装件1的剖视示意图。如图1A所示，一半导体芯片13通过多个焊锡凸块130结合至一封装基板10的线路层11的电性接触垫110上并电性连接该线路层11的导电迹线111，再形成底胶14于该半导体芯片13与该封装基板10之间，以包覆该些焊锡凸块130，其中，该封装基板10上形成有一绝缘保护层12，其对应置晶区形成单一开窗120，如图1B所示，以外露各该电性接触垫110与部分该导电迹线111。
但是，由于该底胶14与介电材(即该封装基板10的表面材料)或绝缘保护层12之间的结合力佳而与铜质线路层11之间结合力不佳，故于该置晶区中，该底胶14接触结合较多的线路层11，导致容易发生脱层(delamination)的问题，即该底胶14与该封装基板10发生分离的问题。
再者，该绝缘保护层12亦可采用多个对应外露各该电性接触垫110的开孔121取代该开窗120，如图1C所示，以减少该底胶14接触该线路层11的面积。然而，于该底胶14流入该半导体芯片13与该封装基板10间时，该底胶14中具较大颗粒的填充材(filler)无法通过该半导体芯片13与该封装基板10间而产生空隙(void)，以致于后续制程中容易发生爆米花现象(Popcorn)，致使产品良率降低。
因此，如何克服上述现有技术的种种缺陷，已成目前亟欲解决的课题。
发明内容
为解决上述现有技术的问题，本发明遂提出一种电子封装件及其制法与基板结构，可减少该绝缘保护层的阻隔。
本发明的基板结构，包括：基板本体，其具有一接合面；线路层，其形成于该接合面上且具有多个电性接触垫，其中，至少一该电性接触垫的边缘定义有第一区段与第二区段，以令至少一该电性接触垫于该第一区段的周长大于或等于至少一该电性接触垫于该第二区段的周长；以及绝缘保护层，其形成于该接合面上且设有多个开孔，以令多个该电性接触垫对应外露于多个该开孔，其中，该绝缘保护层于至少一该开孔处还形成有包围至少一该电性接触垫的至少一作用区，其包含有一围绕该第一区段的强化部及一连通至少一该开孔且围绕该第二区段的镂空部。
前述的基板结构中，该电性接触垫的形状为圆形、椭圆形或多边形。
前述的基板结构中，该至少一作用区为多个作用区，其布设呈并排设置或交错设置。
前述的基板结构中，该强化部为该绝缘保护层的绝缘材。
前述的基板结构中，该镂空部的宽度大于该开孔的宽度。
前述的基板结构中，该开孔的形式为防焊定义规格或非防焊定义规格。
本发明还提供一种电子封装件，包括：前述的基板结构；以及电子元件，其设于该基板结构上以电性连接该线路层。
本发明亦提供一种电子封装件的制法，包括：提供一前述的基板结构；以及将电子元件设于该基板结构上，以令该电子元件电性连接该线路层。
前述的电子封装件及其制法中，该电子元件通过多个导电元件设于多个该电性接触垫上，且以封装层包覆该多个导电元件。
由上可知，本发明的电子封装件及其制法与基板结构，主要通过该作用区的设计，使该电性接触垫的周围环绕该强化部，以遮盖部分该线路层而减少该线路层外露的面积，故相比于现有技术中，该封装层于该置晶区中能接触结合较少的线路层而接触较多的介电材与绝缘保护层，因而该封装层与该基板结构的结合力可大幅提升，以有效避免发生脱层的问题。
再者，通过该作用区的设计，使该电性接触垫的周围环绕该镂空部，以减少该绝缘保护层的阻隔，故相比于现有技术，当如底胶的封装层流入该电子元件与该基板结构之间时，该底胶中较大的颗粒可顺利通过该电子元件与该基板结构之间的通道，以避免该封装层发生空隙的问题，因而于后续制程中不会发生爆米花现象，进而提升产品良率。
附图说明
图1A为现有半导体封装件的剖视示意图。
图1B为现有半导体封装件的封装基板的局部上视平面示意图。
图1C为现有半导体封装件的封装基板的另一实施例的局部上视平面示意图。
图2A至图2B为本发明的电子封装件的制法的剖视示意图。
图2C为图2B的另一区域的剖视示意图。
图3A为本发明的基板结构的局部上视平面示意图。
图3B为图3A的局部放大示意图。
图3C为图3A的另一实施例的局部上视平面示意图。
图4A为本发明的基板结构的另一实施例的局部上视平面示意图。
图4B为图4A的另一实施例的局部上视平面示意图。
图5为图3B的另一实施例的局部上视平面示意图。
图6A为图4A的另一实施例的局部上视平面示意图。
图6B为图6A的另一实施例的局部上视平面示意图。
图7为本发明的基板结构的电性接触垫的各种形状的上视平面示意图。
主要组件符号说明
1 半导体封装件
10 封装基板
11,21 线路层
110,210,510,610,710 电性接触垫
111,211,411 导电迹线
12,22 绝缘保护层
120,220 开窗
121,221,421,521,621 开孔
13 半导体芯片
130 焊锡凸块
14 底胶
2 基板结构
20 基板本体
20a 接合面
20b 植球面
200 介电层
201 布线层
210a 第一区段
210b 第二区段
23 强化部
24,44 镂空部
25 焊球
3 电子封装件
30 电子元件
30a 作用面
30b 非作用面
300 导电元件
A 作用区
D 置晶区
R1,R2 宽度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当视为本发明可实施的范畴。
图2A至图2B为本发明的电子封装件3的制法的剖视示意图。
如图2A所示，提供一基板结构2，其包括一基板本体20、一线路层21以及一绝缘保护层22。
所述的基板本体20具有相对的接合面20a与植球面20b，以于该接合面20a上配置该线路层21与该绝缘保护层22，且该接合面20a上定义有一置晶区D，如图3A所示。
于本实施例中，该基板本体20为具有核心层或无核心层(coreless)的线路结构，如封装基板(substrate)，其包含至少一介电层200与至少一结合该介电层的布线层201。例如，以线路重布层(redistribution layer，简称RDL)方式形成该布线层201，其材料为铜，且形成该介电层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该基板本体20亦可为其它可供接置电子元件的承载单元，例如晶圆、芯片、硅中介板(siliconinterposer)、硅材、玻璃等的半导体板材，并不限于上述。
所述的线路层21形成于该基板本体20的接合面20a上且电性连接该基板本体20的布线层201。
请同时配合参阅图3A及图3B，于本实施例中，该线路层21包含多个导电迹线(trace)211及一体结合该多个导电迹线211的多个电性接触垫210，且各该导电迹线211相互分离而不会短路(如图3A所示)，而该电性接触垫210的边缘定义有第一区段210a与第二区段210b(如图3B所示)，且令该电性接触垫210于该第一区段210a的周长大于或等于该电性接触垫210于该第二区段210b的周长。
再者，该线路层21的规格可采用凸块接线(bump on lead/bump on trace，简称BOL)方式进行线路设计，如图4A所示的电性接触垫210位于导电迹线411的线段上，使该电性接触垫210的两侧延伸有该导电迹线411。
所述的绝缘保护层22形成于该基板本体20的接合面20a上且对应该置晶区D配置有多个开孔221及至少一开窗220，如图3A所示，以令该基板本体20的部分接合面20a、部分该些导电迹线211及部分该电性接触垫210外露于该开窗220，且令部分该多个电性接触垫210对应外露于该多个开孔221，使该绝缘保护层22仅覆盖部分该线路层21与部分该接合面20a。此外，该绝缘保护层22还形成有至少一位于该置晶区D的作用区A，其包围该置晶区D的电性接触垫210，其中，该作用区A包含一围绕该第一区段210a的强化部23，以及一连通用以外露出该电性接触垫210的开孔221且围绕该第二区段210b的镂空部24，如图3A及图3B所示，使该强化部23对应该电性接触垫210的边缘长度大于或等于该镂空部24对应该电性接触垫210的边缘长度。
于本实施例中，该强化部23为该绝缘保护层22一体成形的绝缘体，因而可视为该绝缘保护层22的一部分，且该镂空部24为连结该强化部23的孔洞，其宽度R1大于该开孔221的宽度R2，如图3B所示。例如，该电性接触垫210为圆形，且该镂空部24为该开窗220的其中一部分，以令位于该开孔221与该开窗220相互连通，使该开窗220的边缘呈现齿状或凹凸状。然而，该镂空部44亦可未连通该开窗220(仅连通该开孔221)，如图4A或图4B所示，且该镂空部44可外露该导电迹线211。
再者，如图3A所示，于本实施例中，该置晶区D配置有多个作用区A，且该些作用区A的布设呈并排设置。或者，该些作用区A的布设呈交错设置，如图3C所示。
如图3A或图4B所示，开孔221的形式可为防焊定义(Solder-Mask Defined PadDesign，简称SMD)规格，或如图4A所示，开孔421的形式可为非防焊定义(Non－Solder MaskDefined，简称NSMD)规格，且相对应的镂空部24,44的宽度R1均大于该两规格开孔221,421的宽度R2。
另外，于其它实施例中，该电性接触垫510,610可为非圆形，如图5、图6A及图6B所示的椭圆形或类椭圆形(如长条状)，且该开孔421,521,621亦对应该电性接触垫510,610的形状而呈非圆形。应可理解地，该电性接触垫的形状可依需求设计，如图7所示的矩形或其它多边形等各种几何形状的电性接触垫710，并无特别限制。
如图2B所示，于该基板结构2的电性接触垫210上接置至少一电子元件30，使该电子元件30电性连接该线路层21，且于该植球面20b上形成多个焊球25。
该电子元件30可为主动元件、被动元件、封装基板或封装模块等，且该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。于本实施例中，该电子元件30具有相对的作用面30a与非作用面30b，且该作用面30a具有多个的电极垫(图未示)并通过多个导电元件300结合并电性连接至该些电性接触垫210，其中，该些导电元件300为例如含有焊锡材料或金属块(如铜柱)的块体。
再者，于后续制程中，可将封装层29形成于该基板结构2的接合面20a上以包覆该些导电元件300，甚至包覆该电子元件30。例如，该封装层29可为底胶、聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)的封装胶体或封装材(molding compound)等绝缘材，并无特别限制。
因此，本发明的电子封装件3的制法中，主要通过该作用区A的设计，使该电性接触垫210,510,610,710的部分周围环绕有该强化部23，以遮盖部分该导电迹线211,411而减少该导电迹线211,411外露的面积，故相比于现有技术中，该封装层29于该置晶区D中能接触结合较少的线路层21而接触较多的介电材(即该基板结构2的介电层200)与绝缘保护层22，因而该封装层29与该基板结构2的结合力大幅提升，以有效避免该封装层29与该基板结构2发生分离脱层(delamination)的问题。
再者，通过该作用区A的设计，使该电性接触垫210,510,610,710的部分周围环绕有该镂空部24,44，以减少该绝缘保护层22的阻隔，故相比于现有技术，当该封装层29(如底胶)流入该电子元件30与该基板结构2之间时，该封装层29中较大的颗粒能顺利通过该电子元件30与该基板结构2之间的通道，以避免该封装层29发生空隙的问题，因而于后续制程中不会发生爆米花现象(Popcorn)，进而提升产品良率。
本发明还提供一种电子封装件3包括一基板结构2以及至少一电子元件3，且该基板结构2包括：一基板本体20、一线路层21以及一绝缘保护层22。
所述的基板本体20具有一接合面20a。
所述的线路层21形成于该接合面20a上且具有多个电性接触垫210,510,610,710，其中，该电性接触垫210,510,610,710的边缘定义有第一区段210a与第二区段210b，以令该电性接触垫210,510,610,710于该第一区段210a的周长大于或等于该电性接触垫210,510,610,710于该第二区段210b的周长。
所述的绝缘保护层22形成于该接合面20a上且配置有多个开孔221,421，以令该多个电性接触垫210,510,610,710对应外露于该多个开孔221,421，其中，该绝缘保护层22于至少一该开孔221,421,521,621处还形成有包围该电性接触垫210,510,610,710的至少一作用区A，其包含有一围绕该第一区段210a的强化部23及一连通该开孔221,421,521,621且围绕该第二区段210b的镂空部24,44。
所述的电子元件30设于该基板结构2的接合面20a上以电性连接该线路层21。
于一实施例中，该电性接触垫210,510,610,710的形状为圆形、椭圆形或多边形。
于一实施例中，该至少一作用区A为多个作用区A，其布设呈并排设置或交错设置。
于一实施例中，该强化部23为该绝缘保护层22的绝缘材。
于一实施例中，该镂空部24,44的宽度R1大于该开孔221,421的宽度R2。
于一实施例中，该开孔221,421,521,621的形式为防焊定义规格或非防焊定义规格。
于一实施例中，该电子元件30通过多个导电元件300设于该多个电性接触垫210,510,610,710上，且以封装层29包覆该多个导电元件300。
综上所述，本发明的电子封装件及其制法与基板结构中，通过该作用区的设计，使该强化部遮盖该电性接触垫周围的导电迹线而减少线路层外露的面积，故该封装层于该置晶区中能接触结合较少的线路层而接触较多的介电材与绝缘保护层，因而该封装层与该基板结构的结合力能大幅提升，以有效避免发生脱层的问题。
再者，通过该作用区的设计，使该镂空部减少该电性接触垫周围受该绝缘保护层的阻隔区域，故当该封装层流入该电子元件与该基板结构之间时，该封装层中较大的颗粒能顺利通过该电子元件与该基板结构之间的通道，以避免该封装层发生空隙的问题，因而于后续制程中不会发生爆米花现象，进而提升产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种基板结构，包括：
基板本体，其具有一接合面；
线路层，其形成于该接合面上且具有多个电性接触垫，其中，至少一该电性接触垫的边缘定义有第一区段与第二区段，以令至少一该电性接触垫于该第一区段的周长大于或等于至少一该电性接触垫于该第二区段的周长；以及
绝缘保护层，其形成于该接合面上且设有多个开孔，以令多个该电性接触垫对应外露于多个该开孔，其中，该绝缘保护层于至少一该开孔处还形成有包围至少一该电性接触垫的至少一作用区，其包含有一围绕该第一区段的强化部及一连通至少一该开孔且围绕该第二区段的镂空部。
2.如权利要求1所述的基板结构，其中，多个该电性接触垫的形状为圆形、椭圆形或多边形。
3.如权利要求1所述的基板结构，其中，该至少一作用区为多个作用区，其布设呈并排设置或交错设置。
4.如权利要求1所述的基板结构，其中，该强化部为该绝缘保护层的绝缘材。
5.如权利要求1所述的基板结构，其中，该镂空部的宽度大于该开孔的宽度。
6.如权利要求1所述的基板结构，其中，多个该开孔的形式为防焊定义规格或非防焊定义规格。
7.一种电子封装件，包括：
如权利要求1至6中任一者所述的基板结构；以及
电子元件，其设于该基板结构上且电性连接该线路层。
8.如权利要求7所述的电子封装件，其中，该电子元件通过多个导电元件设于该电性接触垫上，且以封装层包覆该多个导电元件。
9.一种电子封装件的制法，包括：
提供一如权利要求1至6任一者所述的基板结构；以及
将电子元件设于该基板结构上，且令该电子元件电性连接该线路层。
10.如权利要求9所述的电子封装件的制法，其中，该电子元件通过多个导电元件设于多个该电性接触垫上，且以封装层包覆该多个导电元件。
CN202211370330.0A 2022-10-26 2022-11-03 电子封装件及其制法与基板结构 Pending CN117936500A (zh)

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