CN116759410A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN116759410A
CN116759410A CN202210246848.7A CN202210246848A CN116759410A CN 116759410 A CN116759410 A CN 116759410A CN 202210246848 A CN202210246848 A CN 202210246848A CN 116759410 A CN116759410 A CN 116759410A
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China
Prior art keywords
electronic
package
layer
wiring structure
electrically connected
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CN202210246848.7A
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Inventor
卜昭强
何祈庆
符毅民
王愉博
刘帅麟
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN116759410A publication Critical patent/CN116759410A/zh
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract

本发明涉及一种电子封装件及其制法，包括于承载组件的布线结构上配置一芯片封装模块、具有多个接点的电子元件、以及电子连接器，以经由该电子元件及电子连接器通讯连接该芯片封装模块，进而提升信号传输速度。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种具电子连接器的电子封装件及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂开发出不同的立体封装技术，以将不同功能的集成电路整合于单一封装结构，例如将不同功用的电子元件(如：存储器、中央处理器、绘图处理器、影像应用处理器等)，经由堆叠设计达到统的整合，以应用于轻薄型电子产品。
图1为现有半导体封装件1的剖面示意图。该半导体封装件1包括：一基板结构14及一设于该基板结构14上的芯片封装模块1a，其中该芯片封装模块1a包含一第一封装胶体15、一嵌埋于该第一封装胶体15中的第一半导体芯片11、一设于该第一封装胶体15相对两侧的线路结构10与多个导电元件17、多个嵌埋于该第一封装胶体15中以电性连接该线路结构10与导电元件17的导电柱13、多个设于该线路结构10上的第二半导体芯片12以及一包覆该第二半导体芯片12的第二封装胶体16，以令该导电元件17接置于该基板结构14上。另外，该基板结构14上侧可配置一散热件18，并于该基板结构14下侧形成多个焊球19，以供接合一电路板(图略)。
然而，现有半导体封装件1仅配置一个芯片封装模块1a，故于该电路板上，多个芯片封装模块1a之间的通讯仅能依靠该基板结构14进行电性传输，致使传输速度相当缓慢，尤其是，当该半导体封装件1应用于高数据速率、逐渐增加的频宽及逐渐降低时延等需求的人工智能(artificial intelligence，简称AI)相关的电子产品时，更将凸显该半导体封装件1的不适用。
再者，随着包含高性能计算(high-performance computing，简称HPC)元件的半导体封装件1的封装尺寸需要增大的情况下，各该芯片封装模块1a之间的通讯更难以符合运行需求。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，可提升信号传输速度。
本发明的电子封装件，包括：承载组件，其具有布线结构；芯片封装模块，其设于该承载组件上并电性连接该布线结构；具有多个接点的电子元件，其设于该承载组件上并电性连接该布线结构，以接收该芯片封装模块的电性信号；以及电子连接器，其设于该承载组件上并电性连接该布线结构，以接收该电子元件的电性信号。
本发明还提供一种电子封装件的制法，包括：提供一具有布线结构的承载组件；以及将芯片封装模块、具有多个接点的电子元件及电子连接器设于该承载组件上，使该芯片封装模块、电子元件及电子连接器电性连接该布线结构，以令该电子元件接收该芯片封装模块的电性信号，且令该电子连接器接收该电子元件的电性信号。
前述的电子封装件及其制法中，该布线结构包含线路重布层。例如，该布线结构还包含介电层，使该线路重布层结合该介电层。
前述的电子封装件及其制法中，还包括将该承载组件设于一基板结构上。
前述的电子封装件及其制法中，该承载组件包含一嵌埋有多个第二导电柱的第二封装层，以令该布线结构设于该第二封装层上并电性连接该多个第二导电柱。进一步，该芯片封装模块包含一埋设有多个第一导电柱的第一封装层。例如，该第一封装层与该第二封装层配置于该布线结构的相对两侧。另外，该第一封装层的硬度大于该第二封装层的硬度。
前述的电子封装件及其制法中，该芯片封装模块包含桥接元件。
前述的电子封装件及其制法中，该电子连接器设有一用以连接外部装置的信号传输线。
由上可知，本发明的电子封装件及其制法中，主要经由该第二电子元件及电子连接器通讯连接该芯片封装模块，以提升信号传输速度，因而可避免多个电子封装件之间的通讯速度太慢的问题，故相比于现有技术，本发明于该电路板上，多个电子封装件上的芯片封装模块之间的通讯经由该电子连接器进行电性传输，以增快传输速度，尤其是，当该电子封装件应用于高数据速率、逐渐增加的频宽及逐渐降低时延等需求的人工智能相关的电子产品时，更可凸显该电子封装件的适用性极佳。
再者，随着包含高性能计算元件的电子封装件的封装尺寸需要增大的情况下，各该芯片封装模块之间的通讯更能符合运行需求。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2H为本发明的电子封装件的制法的剖视示意图。
主要组件符号说明
1 半导体封装件
1a,2a 芯片封装模块
10,20 线路结构
11 第一半导体芯片
12 第二半导体芯片
13 导电柱
14,34 基板结构
15 第一封装胶体
16 第二封装胶体
17,37 导电元件
18,38 散热件
19,39 焊球
2 电子封装件
200,300,81,91 绝缘层
201,301 线路重布层
202,302 电性接触垫
21 第一桥接元件
210 电极垫
211 保护膜
212 导电体
213 结合层
22 第一电子元件
220,27 导电凸块
221,36 底胶
23 第一导电柱
23a,23b 端面
24 线路部
240 导电迹线
241 外接垫
25 第一封装层
25a 第一表面
25b 第二表面
26 包覆层
28 第二电子元件
280 接点
29 电子连接器
290 信号传输线
3a 承载组件
30 布线结构
303 凸块底下金属层
31 第二桥接元件
32 第三桥接元件
33 第二导电柱
340 布线层
35 第二封装层
8 支撑板
80,90 离型层
9 承载板
S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，于一整版面(panel)规格或晶圆级(wafer level)规格的承载板9上形成多个第一导电柱23，且设置至少一第一桥接元件21(本实施例显示有多个第一桥接元件21)于该承载板9上。接着，形成第一封装层25于该承载板9上，以令该第一封装层25包覆该些第一桥接元件21与该些第一导电柱23。
所述的承载板9例如为半导体材料(如硅或玻璃)的板体，其上以例如涂布方式依序形成有一离型层90与一如介电材或防焊材的绝缘层91。
所述的第一桥接元件21为半导体芯片，其底侧经由一如置晶膜(die attachedfilm，简称DAF)的结合层213黏固于该绝缘层91上，而上侧具有多个电极垫210与一如钝化材的保护膜211，且各该电极垫210上设有导电体212，以令该保护膜211包覆多个导电体212。
于本实施例中，该多个导电体212为如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)导电件，但不限于此。
所述的第一导电柱23为如铜柱的金属柱或含焊锡材料的柱体，且该多个第一导电柱23贯穿该绝缘层91。
所述的第一封装层25具有相对的第一表面25a与第二表面25b，且令该保护膜211与该多个导电体212的上表面及该第一导电柱23的端面23a外露于该第一封装层25的第一表面25a，并令该第一封装层25以其第二表面25b结合至该承载板9的绝缘层91上。
于本实施例中，该第一封装层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如，该第一封装层25的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该绝缘层91上。
再者，可经由整平制程，使该第一封装层25的第一表面25a齐平该保护膜211与该多个导电体212的上表面及该第一导电柱23的端面23a，以令该保护膜211、第一导电柱23的端面23a与该多个导电体212外露于该第一封装层25的第一表面25a。例如，该整平制程经由研磨方式，移除该保护膜211的部分材料、该第一导电柱23的部分材料、该多个导电体212的部分材料与该第一封装层25的部分材料。
如图2B所示，形成一线路结构20于该第一封装层25的第一表面25a上，且令该线路结构20电性连接该多个第一导电柱23与该多个导电体212。
于本实施例中，该线路结构20包括多个绝缘层200及设于该绝缘层200上的多个线路重布层(redistribution layer，简称RDL)201，其中，最外层的绝缘层200可作为防焊层，且令最外层的线路重布层201外露于该防焊层，从而以供作为电性接触垫202，如微形垫(u-pad)。进一步，可形成一凸块底下金属层(Under Bump Metallurgy，简称UBM)(图略)于该电性接触垫202上。应可理解地，该线路结构20亦可仅包括单一绝缘层200及单一线路重布层201。
再者，形成该线路重布层201的材料为铜，且形成该绝缘层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(PI)、预浸材(Prepreg，简称PP)等的介电材、或如绿漆、油墨等的防焊材。
如图2C所示，设置至少一第一电子元件22于该线路结构20上，以令该第一电子元件22电性连接该线路结构20(本实施例显示有多个第一电子元件22)。接着，移除该承载板9及其上的离型层90，并保留该绝缘层91，使该些第一导电柱23的端面23b外露于该绝缘层91。
所述的第一电子元件22为主动元件、被动元件或其二者组合，且该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
于本实施例中，该第一电子元件22例如为图形处理器(graphics processingunit，简称GPU)、高频宽存储器(High Bandwidth Memory，简称HBM)或其它类型半导体芯片的主动元件，但并无特别限制。例如，该第一电子元件22经由多个如焊锡凸块、铜凸块或其它等的导电凸块220电性连接该电性接触垫202，且可经由包覆层26同时包覆该第一电子元件22与该些导电凸块220。或者，亦可先形成底胶221于该第一电子元件22与该线路结构20之间以包覆该些导电凸块220，再形成该包覆层26以包覆该底胶221与该第一电子元件22。
所述的包覆层26为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20上。应可理解地，形成该包覆层26的材料可相同或不相同该第一封装层25的材料。
于本实施例中，可经由整平制程，如研磨方式，移除该包覆层26的部分材料，使该包覆层26的上表面齐平该第一电子元件22的表面，以令该第一电子元件22外露于该包覆层26。
再者，当配置多个个第一电子元件22时，可使单一该第一桥接元件21经由该线路结构20电性桥接至少两个第一电子元件22。
如图2D所示，形成多个如多个焊锡凸块或焊球(其规格为C4型)的导电凸块27于该绝缘层91上，以令该多个导电凸块27电性连接该多个第一导电柱23。
于本实施例中，可于该绝缘层91上进行RDL制程，以形成包含导电迹线240及外接垫241的线路部24，供该多个导电凸块27结合于该外接垫241上；或者，也可于该多个第一导电柱23的端面23b上直接结合该多个导电凸块27。
如图2E所示，沿如图2D所示的切割路径S进行切单制程，以获取多个芯片封装模块2a。
如图2F所示，于一支撑板8上制作一整版面规格或晶圆级规格的承载组件3a。于本实施例中，该承载组件3a的制程可如图2A至图2B所示的方式，故该承载组件3a包含设于该支撑板8上的至少一第二桥接元件31、至少一第三桥接元件32及多个第二导电柱33，再形成一包覆该第二桥接元件31、该第三桥接元件32及该些第二导电柱33的第二封装层35，并于该第二封装层35上形成一布线结构30。
所述的支撑板8上依序具有一离型层80及一如介电材或防焊材的绝缘层81，以结合该第二桥接元件31、该第三桥接元件32、该些第二导电柱33及该第二封装层35。
所述的布线结构30包含至少一绝缘层300及结合该绝缘层300的至少一线路重布层(redistribution layer，简称RDL)301，且最外层的线路重布层301具有多个如微形垫(u-pad)的电性接触垫302。进一步，可形成一凸块底下金属层(UBM)303于该电性接触垫302上。
于本实施例中，形成该线路重布层301的材料为铜，且形成该绝缘层300的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它适合的介电材，且可采用线路重布层(redistribution layer，简称RDL)制程形成该布线层301与该绝缘层300。
所述的第二桥接元件31为半导体芯片构造，其电性连接该线路重布层301。
所述的第三桥接元件32为半导体芯片构造，其电性连接该线路重布层301。
所述的第二导电柱33为如铜柱的金属柱或含焊锡材料的柱体，其电性连接该线路重布层301，并与该第二桥接元件31及该第三桥接元件32相互间隔配置。
所述的第二封装层35为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。
于本实施例中，该第二封装层35的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该支撑板8上。
再者，可经由整平制程，如研磨方式，使该第二封装层35的表面齐平该多个第二导电柱33的端面，以令该第二导电柱33的端面外露于该第二封装层35的表面。应可理解地，该第二桥接元件31及该第三桥接元件32可依需求外露或不外露出该第二封装层35的表面。
另外，该第二封装层35的材料与该第一封装层25的材料可相同或不相同。例如，该第一封装层25的硬度大于该第二封装层35的硬度。
如图2G所示，于该承载组件3a的布线结构30上设置该芯片封装模块2a、第二电子元件28及电子连接器(connector)29。接着，移除该支撑板8及离型层80，以外露出该承载组件3a的多个第二导电柱33的端面。
所述的芯片封装模块2a以其导电凸块27电性接合于该布线结构30上。
所述的第二电子元件28为半导体芯片构造，其具有多个接点280，并以覆晶方式电性连接该布线结构30，以接收该芯片封装模块2a的电性(如数字或模拟)信号。
所述的电子连接器29以例如焊接方式电性接合该布线结构30，以接收该第二电子元件28的电性(如数字或模拟)信号。
于本实施例中，该电子连接器29设有一用以连接外部装置(图略)的信号传输线290，以将信号传输至如其它封装件的外部装置。应可理解地，可依需求形成底胶36以固定该芯片封装模块2a、第二电子元件28及电子连接器29。
再者，该第二桥接元件31电性桥接该芯片封装模块2a与该第二电子元件28，且该第三桥接元件32电性桥接该第二电子元件28与该电子连接器29，使该第二电子元件28可经由该第二桥接元件31与该布线结构30接收该芯片封装模块2a的电性信号，并将该电性信号经由该布线结构30与该第三桥接元件32传输至该电子连接器29，使该电子连接器29将该电性信号传输至该外部装置。
如图2H所示，接着于该承载组件3a的绝缘层81上形成多个电性连接该第二导电柱32的导电元件37，再进行切单制程，且该承载组件3a可经由该些导电元件37堆叠于一基板结构34上。
所述的基板结构34例如具有核心层的封装基板(substrate)或无核心层(coreless)式封装基板，其配置有至少一布线层340。
所述的导电元件37为含有焊锡材料的金属凸块，其电性连接该基板结构34的布线层340，并可经由底胶36包覆该些导电元件37。
于本实施例中，于该基板结构34的上侧(即配置该承载组件3a之侧)可设置至少一散热件38，且可于该基板结构34下侧的布线层340上进行植球制程，以形成多个焊球39，供设于一电路板(图略)上。
因此，本发明的制法主要经由增设第二电子元件28及电子连接器29，以提升信号传输速度，故相比于现有技术，本发明的电子封装件2能避免多个电子封装件之间的通讯速度太慢的问题。例如，于该电路板上，多个芯片封装模块2a之间的通讯经由该信号传输线290进行电性传输，而无需通过该基板结构34，以增快传输速度，尤其是，当该电子封装件2应用于高数据速率、逐渐增加的频宽及逐渐降低时延等需求的人工智能(artificialintelligence，简称AI)相关的电子产品时，更能凸显该电子封装件2的适用性极佳。
再者，随着包含高性能计算(high-performance computing，简称HPC)元件的电子封装件2的封装尺寸需要增大的情况下，各该芯片封装模块2a之间的通讯更能符合运行需求。
本发明还提供一种电子封装件2，包括：一承载组件3a、一芯片封装模块2a、一具有多个接点280的第二电子元件28以及一电子连接器29。
所述的承载组件3a具有布线结构30。
所述的芯片封装模块2a设于该承载组件3a上并电性连接该布线结构30。
所述的第二电子元件28设于该承载组件3a上并电性连接该布线结构30，以接收该芯片封装模块2a的电性信号。
所述的电子连接器29设于该承载组件3a上并电性连接该布线结构30，以接收该第二电子元件28的电性信号。
于一实施例中，该布线结构30包含绝缘层300及结合该绝缘层300的线路重布层301。
于一实施例中，所述的电子封装件2还包括一用以设置该承载组件3a的基板结构34。
于一实施例中，该承载组件3a包含一嵌埋有多个第二导电柱33的第二封装层35，以令该布线结构30设于该第二封装层35上并电性连接该多个第二导电柱33。进一步，该芯片封装模块2a包含一埋设有多个第一导电柱23及第一桥接元件21的第一封装层25。例如，该第一封装层25与该第二封装层35配置于该布线结构30的相对两侧。另外，该第一封装层25的硬度大于该第二封装层35的硬度。
于一实施例中，该芯片封装模块2a包含第一桥接元件21。
于一实施例中，该电子连接器29设有一用以连接外部装置的信号传输线290。
综上所述，本发明的电子封装件及其制法，经由该第二电子元件及电子连接器通讯连接该芯片封装模块，以提升信号传输速度，故本发明能避免多个电子封装件之间的通讯速度太慢的问题。
再者，随着包含高性能计算元件的电子封装件的封装尺寸需要增大的情况下，各该芯片封装模块之间的通讯更能符合运行需求。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种电子封装件，包括：
承载组件，其具有布线结构；
芯片封装模块，其设于该承载组件上并电性连接该布线结构；
具有多个接点的电子元件，其设于该承载组件上并电性连接该布线结构，以接收该芯片封装模块的电性信号；以及
电子连接器，其设于该承载组件上并电性连接该布线结构，以接收该电子元件的电性信号。
2.如权利要求1所述的电子封装件，其中，该布线结构包含介电层及结合该介电层的线路重布层。
3.如权利要求1所述的电子封装件，其中，该电子封装件还包括一用以设置该承载组件的基板结构。
4.如权利要求1所述的电子封装件，其中，该承载组件包含一嵌埋有多个第二导电柱的第二封装层，以令该布线结构设于该第二封装层上并电性连接该多个第二导电柱。
5.如权利要求4所述的电子封装件，其中，该芯片封装模块包含一埋设有多个第一导电柱的第一封装层。
6.如权利要求5所述的电子封装件，其中，该第一封装层与该第二封装层配置于该布线结构的相对两侧。
7.如权利要求5所述的电子封装件，其中，该第一封装层的硬度大于该第二封装层的硬度。
8.如权利要求1所述的电子封装件，其中，该芯片封装模块包含桥接元件。
9.如权利要求1所述的电子封装件，其中，该电子连接器设有一用以连接外部装置的信号传输线。
10.一种电子封装件的制法，包括：
提供一设有布线结构的承载组件；以及
将芯片封装模块、具有多个接点的电子元件及电子连接器设于该承载组件上，并使该芯片封装模块、电子元件及电子连接器电性连接该布线结构，以令该电子元件接收该芯片封装模块的电性信号，且令该电子连接器接收该电子元件的电性信号。
11.如权利要求10所述的电子封装件的制法，其中，该布线结构包含介电层及结合该介电层的线路重布层。
12.如权利要求10所述的电子封装件的制法，其中，该制法还包括将该承载组件设于一基板结构上。
13.如权利要求10所述的电子封装件的制法，其中，该承载组件包含一嵌埋有多个第二导电柱的第二封装层，以令该布线结构设于该第二封装层上并电性连接该多个第二导电柱。
14.如权利要求13所述的电子封装件的制法，其中，该芯片封装模块包含一埋设有多个第一导电柱的第一封装层。
15.如权利要求14所述的电子封装件的制法，其中，该第一封装层与该第二封装层配置于该布线结构的相对两侧。
16.如权利要求14所述的电子封装件的制法，其中，该第一封装层的硬度大于该第二封装层的硬度。
17.如权利要求10所述的电子封装件的制法，其中，该芯片封装模块包含桥接元件。
18.如权利要求10所述的电子封装件的制法，其中，该电子连接器设有一用以连接外部装置的信号传输线。
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