TW201724389A - 終極薄扇出型晶片封裝構造及其製造方法 - Google Patents
終極薄扇出型晶片封裝構造及其製造方法 Download PDFInfo
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- TW201724389A TW201724389A TW104143306A TW104143306A TW201724389A TW 201724389 A TW201724389 A TW 201724389A TW 104143306 A TW104143306 A TW 104143306A TW 104143306 A TW104143306 A TW 104143306A TW 201724389 A TW201724389 A TW 201724389A
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- 238000000034 method Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims description 181
- 239000011241 protective layer Substances 0.000 claims description 71
- 239000000565 sealant Substances 0.000 claims description 55
- 230000002093 peripheral effect Effects 0.000 claims description 33
- 238000005538 encapsulation Methods 0.000 claims description 22
- 239000012790 adhesive layer Substances 0.000 claims description 17
- 238000007789 sealing Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 8
- 238000010276 construction Methods 0.000 claims description 6
- 239000008393 encapsulating agent Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 230000008707 rearrangement Effects 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract 5
- 235000012431 wafers Nutrition 0.000 description 71
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02379—Fan-out arrangement
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
揭示一種終極薄扇出型晶片封裝構造,包含一晶片、一封膠層、一第一有機保護層、一重配置線路層、一第二有機保護層以及複數個縱向導通元件。封膠層包覆晶片之側面,封膠層與晶片之兩者厚度控制為一致。第一有機保護層覆蓋於晶片之主動面與封膠層之周邊表面並具有複數個扇出開孔。重配置線路層延伸至扇出開孔,以形成貼附於封膠層之扇出墊。第二有機保護層形成於第一有機保護層上。縱向導通元件嵌埋於封膠層中並接合至扇出墊。因此,縱向導通元件只需要貫穿封膠層且重配置線路層不易斷裂。
Description
本發明係有關於半導體晶片封裝領域,特別係有關於一種終極薄扇出型晶片封裝構造。
隨著半導體晶片的封裝構造往微小化與密集堆疊的趨勢演進,封裝構造的內部電性連接元件也開始導入重配置線路層(RDL)的設計,例如晶圓級扇出型晶片封裝構造與面板級扇出型晶片封裝構造。扇出型晶片封裝構造在結構上可以省略基板厚度,在製程上可以整合於晶圓或面板製程,相對於傳統的晶片封裝製程下,模封步驟係實施於線路形成步驟之前。
在習知面朝下(face-down)扇出型晶片封裝構造中,重配置線路層係同時形成於封膠層與晶片主動面,使得重配置線路層的線路扇出在晶片之外,但重配置線路層的線路容易發生斷裂的問題。此外,當扇出型晶片封裝構造應用於立體封裝堆疊(POP)產品,對於產品厚度要求也越來越高。
為了解決上述之問題,本發明之主要目的係在於提供一種終極薄扇出型晶片封裝構造及其製造方法,封膠層內縱向
導通元件只需要貫穿封膠層而易於製作,並且重配置線路層不易斷裂。
本發明之次一目的係在於提供一種終極薄扇出型晶片封裝構造及其製造方法,可以應用於立體封裝堆疊(POP)產品並符合薄化需求。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明係揭示一種終極薄扇出型晶片封裝構造,包含一晶片、一封膠層、一第一有機保護層、一重配置線路層、一第二有機保護層以及複數個縱向導通元件。該晶片係具有一主動面、一背面以及複數個側面,其中複數個銲墊係設置於該主動面上。該封膠層係包覆該晶片之該些側面,該封膠層係提供有一由該主動面擴張之周邊表面,該封膠層與該晶片之兩者厚度係控制為一致,並且該封膠層不覆蓋該晶片之該主動面與該背面。該第一有機保護層係順從於該封膠層與該晶片上,該第一有機保護層係覆蓋於該晶片之該主動面與該封膠層之該周邊表面,該第一有機保護層係具有複數個扇入開孔與複數個扇出開孔,該些扇入開孔係顯露該些銲墊,該些扇出開孔係位於該封膠層之該周邊表面。該重配置線路層係形成於該第一有機保護層上,該重配置線路層係經由該些扇入開孔連接至該些銲墊並延伸至該些扇出開孔,該重配置線路層係具有複數個扇出墊,其係經由該些扇出開孔設置於該封膠層之該周邊表面。該第二有機保護層係形成於該第一有機保護層上,以覆蓋該重配置線路層。該些縱向導通元件
係嵌埋於該封膠層中並接合至該些扇出墊。本發明另揭示上述終極薄扇出型晶片封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述終極薄扇出型晶片封裝構造中,可另包含複數個連接端子,其係可設置於該些扇出墊上而突出於該第二有機保護層。
在前述終極薄扇出型晶片封裝構造中,該些連接端子係可位於一由該封膠層縱向投射之周邊覆蓋區域,而不位於一由該晶片縱向投射之中央覆蓋區域。
在前述終極薄扇出型晶片封裝構造中,可另包含一非導電黏著層,其係可形成於該第二有機保護層上,以嵌埋該些連接端子。
在前述終極薄扇出型晶片封裝構造中,該重配置線路層係可另包含一虛置圖案,其係可形成於該第一有機保護層上,複數個虛置端子係可設置於該虛置圖案上而突出於該第二有機保護層,並且複數個虛置墊係可設置於該封膠層共平面於該背面之一擴散表面,並對準於該些虛置端子。
在前述終極薄扇出型晶片封裝構造中,該重配置線路層係可另包含一虛置圖案,該第一有機保護層係可另具有一槽孔,其係可顯露該晶片之該主動面與該封膠層之該周邊表面之間的接縫,該虛置圖案係可填入至該槽孔。
在前述終極薄扇出型晶片封裝構造中,該些縱向導通元件係可為模封貫孔。
藉由上述的技術手段,本發明可以達成堆疊八個封裝層在1毫米(1.0mm)的高度要求內,而製程中係包含了晶圓級模封與重配置線路層的電性連接,並可利用貫穿封膠層的縱向導通元件(例如模封貫孔的孔內鍍銅)縱向導接上下封膠層。
10‧‧‧暫時載體
20‧‧‧切割工具
100‧‧‧終極薄扇出型晶片封裝構造
110‧‧‧晶片
111‧‧‧主動面
112‧‧‧背面
113‧‧‧側面
114‧‧‧銲墊
120‧‧‧封膠層
121‧‧‧周邊表面
122‧‧‧貫穿孔
130‧‧‧第一有機保護層
131‧‧‧扇入開孔
132‧‧‧扇出開孔
140‧‧‧重配置線路層
141‧‧‧扇出墊
142‧‧‧虛置圖案
150‧‧‧第二有機保護層
151‧‧‧接合孔
160‧‧‧縱向導通元件
170‧‧‧連接端子
171‧‧‧虛置端子
180‧‧‧非導電黏著層
190‧‧‧虛置墊
200‧‧‧終極薄扇出型晶片封裝構造
233‧‧‧槽孔
242‧‧‧虛置圖案
第1圖:依據本發明之第一具體實施例,一種終極薄扇出型晶片封裝構造之截面示意圖。
第2圖:依據本發明之第一具體實施例,該終極薄扇出型晶片封裝構造其中一封裝層之截面示意圖。
第3A至3L圖:依據本發明之第一具體實施例,繪示在製造該終極薄扇出型晶片封裝構造之過程中各主要步驟之元件截面示意圖。
第4圖:依據本發明之第二具體實施例,另一種終極薄扇出型晶片封裝構造之截面示意圖。
第5圖:依據本發明之第二具體實施例,該終極薄扇出型晶片封裝構造其中一封裝層之截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明
本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例,一種終極薄扇出型晶片封裝構造100舉例說明於第1圖之截面示意圖以及第2圖其中一封裝層之截面示意圖。第3A至3L圖係繪示在製造該終極薄扇出型晶片封裝構造100之過程中各主要步驟之元件截面示意圖。一種終極薄扇出型晶片封裝構造100係可由複數封裝層堆疊所組成,每一封裝層係包含一晶片110、一封膠層120、一第一有機保護層130、一重配置線路層140、一第二有機保護層150以及複數個縱向導通元件160。
請參閱第1及2圖,該晶片110係具有一主動面111、一背面112以及複數個側面113,其中複數個銲墊114係設置於該主動面111上。該晶片110係為以半導體為基底的積體電路元件,該主動面111係為積體電路的形成表面,該些銲墊114係為可為鋁墊、銅墊或複合式金屬墊並作為電連接內部積體電路的接點,該背面112係相對於該主動面111而無積體電路元件,該些側面113係為連接該主動面111之周邊至該背面112之周邊之切割表面。
該封膠層120係包覆該晶片110之該些側面113。該封膠層120係為模封環氧化合物,其係具有熱固性與電絕緣性。該封
膠層120係提供有一由該主動面111擴張之周邊表面121,該封膠層120之周邊表面121係可與該主動面111為共平面,並且該封膠層120與該晶片110之兩者厚度係控制為一致,並且該封膠層120不覆蓋該晶片110之該主動面111與該背面112。上述控制厚度的方法請容詳述於後述製程。該封膠層120與該晶片110之一致化厚度係可約為30~100微米,具體可為50微米。
該第一有機保護層130係順從於該封膠層120與該晶片110上,該第一有機保護層130係覆蓋於該晶片110之該主動面111與該封膠層120之該周邊表面121。前述所稱之「順從」係指該封膠層120與該晶片110為先成形為承載體,該第一有機保護層130係依據該封膠層120與該晶片110之表面外形而形成,其形成方法包含氣態的沉積(gas deposition)與液態的披覆(liquid coating),但不包含兩物件的固態貼附(solid attachment)。並且,該第一有機保護層130係具有複數個扇入開孔131與複數個扇出開孔132,該些扇入開孔131係顯露該些銲墊114,該些扇出開孔132係位於該封膠層120之該周邊表面121。該些扇出開孔132之間距與開孔尺寸係應大於該些扇入開孔131之間距與開孔尺寸。該第一有機保護層130之材質係具體可為聚亞醯胺(polyimide,PI),該第一有機保護層130之厚度係介於3~20微米,具體可為5微米。該第一有機保護層130之楊氏係數係小於該封膠層120之楊氏係數而更具有彈性。
該重配置線路層140係形成於該第一有機保護層130上,該重配置線路層140之扇出線路係經由該些扇入開孔131連接
至該些銲墊114並延伸至該些扇出開孔132,該重配置線路層140係具有複數個扇出墊141,其係經由該些扇出開孔132設置於該封膠層120之該周邊表面121,故該些扇出墊141係可直接貼觸該封膠層120。因此,該重配置線路層140之扇出線路係完整附著於該第一有機保護層130,而不直接貼觸該晶片110與該封膠層120。該重配置線路層140係為利用積體電路製程製作的複合金屬層,包含例如銅之導電主層,銅導電主層之厚度係可為3微米,在銅導電主層之底部通常有一例如鈦(Ti)之接著層與銅(Cu)晶種層,鈦接著層之厚度係可為0.1微米,銅晶種層之厚度係可為0.2微米,而非必要地,在銅導電主層之上方另可形成鎳金層,鎳層之厚度係可為2微米,金層之厚度係可為0.3微米,以增加該重配置線路層140的防銹能力與焊接能力。因此,該重配置線路層140相較於習知基板之線路結構,不需要電鍍線的連接。
該第二有機保護層150係形成於該第一有機保護層130上,以覆蓋該重配置線路層140。具體地,該第二有機保護層150係具有複數個接合孔151,其係顯露該些扇出墊141。該第二有機保護層150之材質係具體可為聚亞醯胺(polyimide,PI),該第二有機保護層150之厚度係介於3~20微米,具體可為5微米。由該第一有機保護層130、該重配置線路層140與該第二有機保護層150構成一重配置結構,其厚度係可控制在不大於20微米。
該些縱向導通元件160係嵌埋於該封膠層120中並接合至該些扇出墊141。該些縱向導通元件160係具體為模封貫孔
(Through Mold TMV)。該些縱向導通元件160之材質係可為銅、金或銲料,具體為銅;該些縱向導通元件160之形狀係可為直立柱體、直立線體或球體,具體為柱體;該些縱向導通元件160之高度係可等於或略大於該封膠層120之厚度。該些縱向導通元件160為導電性。
在本發明提供之一種終極薄扇出型晶片封裝構造100中,該封膠層120內嵌埋的該些縱向導通元件160只需要貫穿該封膠層120而不需要貫穿該第一有機保護層130,故容易製作,並且該重配置線路層140因夾層於該第一有機保護層130與該第二有機保護層150之間而不易斷裂。此外,該終極薄扇出型晶片封裝構造100之封裝層單位厚度可以控制到100微米以內,可以應用於如第1圖所示的立體封裝堆疊(POP)產品並符合薄化需求。
該終極薄扇出型晶片封裝構造100係可另包含複數個連接端子170,例如銲球或凸塊,其係可透過該些接合孔151設置於該些扇出墊141上而突出於該第二有機保護層150。該些連接端子170係用以接合鄰近封裝層的該些縱向導通元件160或其端部的接墊。具體地,該些連接端子170係可位於一由該封膠層120縱向投射之周邊覆蓋區域,而不位於一由該晶片110縱向投射之中央覆蓋區域。故該晶片110可省略矽穿孔的結構。
該終極薄扇出型晶片封裝構造100係可另包含一非導電黏著層180,其係可形成於該第二有機保護層150上,以嵌埋該些連接端子170。該非導電黏著層180係用以黏著鄰近封裝層的
晶片110與封膠層120,堆疊封裝層之間將不會留有空隙。該非導電黏著層180之材質係可包含可固化樹脂;該非導電黏著層180之之厚度係可控制為等於或略大於該些連接端子170之高度,而不大於30微米。該非導電黏著層180係具有電絕緣性與固化收縮特性。
因此,該終極薄扇出型晶片封裝構造100之封裝層之單位厚度係控制在100微米以內。八個封裝層的堆疊可完成八個晶片的縱向立體排列,總堆疊厚度係可控制在1微米。
較佳地,該重配置線路層140係可另包含一虛置圖案142,其係可形成於該第一有機保護層130上,該虛置圖案142係不具有訊號傳遞之連接功能,而作為散熱、重配置結構增強輔助與接合平衡之用途。複數個虛置端子171係可設置於該虛置圖案142上而突出於該第二有機保護層150,並且複數個虛置墊190係可設置於該封膠層120共平面於該背面112之一擴散表面,並對準於該些虛置端子171。該些虛置端子171係用於接合鄰近封裝層之虛置墊190。
上述終極薄扇出型晶片封裝構造100之製造方法係配合第3A至3L圖並說明如後。首先,請參閱第3A圖,設置一晶片110在一暫時載體10上,該晶片110係具有一主動面111、一背面112以及複數個側面113,其中複數個銲墊114係設置於該主動面111上,該主動面111係貼附於該暫時載體10。該暫時載體10係為一晶圓模擬載體或一面板模擬載體,具體可為模擬成12吋晶圓之玻璃片,該暫時載體10之表面係具有可剝離黏性。複數個晶片110係可
依據晶圓地圖的配置以取放方式暫時貼附於該暫時載體10,該些晶片110之該些主動面111係朝向該暫時載體10。
之後,請參閱第3B圖,以晶圓等級模封或面板等級模封方式形成一封膠層120在該暫時載體10上,以密封該些晶片110,該封膠層120係包覆該些晶片110之該些側面113。在本步驟中,該封膠層120係更包覆該些晶片110之該些背面112。該封膠層120之形狀係可為一晶圓或一面板。
之後,請參閱第3C圖,以晶圓等級研磨或面板等級研磨方式降低該封膠層120之厚度,使得該封膠層120與該些晶片110之兩者厚度係控制為一致,並且該封膠層120不覆蓋該晶片110之該主動面111與該背面112。在本步驟中,該些晶片110之厚度亦同步被降低。
之後,請參閱第3C與3D圖,由該暫時載體10剝離該封膠層120,該封膠層120係提供有一由該主動面111擴張之周邊表面121。上述剝離的方式係可為UV照射,以降低或喪失該暫時載體10的黏性。在本步驟中,該些晶片110之該些主動面111與該封膠層120之該周邊表面121為顯露。
之後,請參閱第3E圖,以氣態沉積或液態塗佈方式順從地形成一第一有機保護層130於該封膠層120與該些晶片110上,該第一有機保護層130係覆蓋於該些晶片110之該些主動面111與該封膠層120之該周邊表面121。之後,在該第一有機保護層130成形之後,以曝光顯影方式圖案化該第一有機保護層130,該第一
有機保護層130係具有複數個扇入開孔131與複數個扇出開孔132,該些扇入開孔131係顯露該些銲墊114,該些扇出開孔132係位於該封膠層120之該周邊表面121。
之後,請參閱第3F圖,以金屬沉積與電鍍方式形成一重配置線路層140於該第一有機保護層130上,該重配置線路層140係經由該些扇入開孔131連接至該些銲墊114並延伸至該些扇出開孔132,該重配置線路層140係具有複數個扇出墊141,其係經由該些扇出開孔132設置於該封膠層120之該周邊表面121。
之後,請參閱第3G圖,以氣態沉積或液態塗佈方式形成一第二有機保護層150於該第一有機保護層130上,以覆蓋該重配置線路層140。
之後,請參閱第3H圖,以鑚孔或孔蝕刻方式使得該封膠層120具有複數個貫穿孔122,該些貫穿孔122之孔底係顯露該些扇出墊141。之後,請參閱第3I圖,以孔電鍍方式形成複數個縱向導通元件160在該些貫穿孔122中,故該些縱向導通元件160嵌埋於該封膠層120中,並且該些縱向導通元件160係接合至該些扇出墊141。該些縱向導通元件160係可微突出於該封膠層120,或者可以在該些縱向導通元件160之端部再形成對應之接墊。
請參閱第3J圖,利用電鍍與迴焊方式設置複數個連接端子170於該重配置線路層140之該些扇出墊141上而突出於該第二有機保護層150。並且,以印刷或膜貼附方式形成一非導電黏著層180於該第二有機保護層150上,以嵌埋該些連接端子170,
藉此可構成一封裝層,可為封裝晶圓或封裝面板型態。請參閱第3K圖,以晶圓對晶圓壓合或者是面板對面板壓合方式堆疊複數個封裝層。
請參閱第3L圖,該終極薄扇出型晶片封裝構造100之製造方法係可另包含一單體化切割步驟,利用鋸切刀具或雷射切割裝置之切割工具20切割該封膠層120,以形成上述單體化之終極薄扇出型晶片封裝構造100(如第1圖所示),其中在單體化切割步驟之前的上述前置步驟係實施於晶圓等級。或者,在單體化切割步驟之前的上述前置步驟係可實施於面板等級。
依據本發明之第二具體實施例,另一種終極薄扇出型晶片封裝構造200舉例說明於第4圖之截面示意圖以及第5圖其中一封裝層之截面示意圖。其中第二具體實施例中與第一具體實施例相同功能的元件將沿用相同圖號且不再細部贅述。該終極薄扇出型晶片封裝構造200係可由複數封裝層堆疊所組成,每一封裝層係包含一晶片110、一封膠層120、一第一有機保護層130、一重配置線路層140、一第二有機保護層150以及複數個縱向導通元件160。
請參閱第4及5圖,該晶片110係具有一主動面111、一背面112以及複數個側面113,其中複數個銲墊114係設置於該主動面111上。該封膠層120係包覆該晶片110之該些側面113,該封膠層120係提供有一由該主動面111擴張之周邊表面121,該封膠層120與該晶片110之兩者厚度係控制為一致,並且該封膠層120不覆
蓋該晶片110之該主動面111與該背面112。
該第一有機保護層130係形成於該封膠層120與該晶片110上,該第一有機保護層130係覆蓋於該晶片110之該主動面111與該封膠層120之該周邊表面121,該第一有機保護層130係具有複數個扇入開孔131與複數個扇出開孔132,該些扇入開孔131係顯露該些銲墊114,該些扇出開孔132係位於該封膠層120之該周邊表面121。該重配置線路層140係形成於該第一有機保護層130上,該重配置線路層140係經由該些扇入開孔131連接至該些銲墊114並延伸至該些扇出開孔132,該重配置線路層140係具有複數個扇出墊141,其係經由該些扇出開孔132設置於該封膠層120之該周邊表面121。該第二有機保護層150係形成於該第一有機保護層130上,以覆蓋該重配置線路層140。該些縱向導通元件160係嵌埋於該封膠層120中並接合至該些扇出墊141。
該終極薄扇出型晶片封裝構造200係可另包含複數個連接端子170,其係可設置於該些扇出墊141上而突出於該第二有機保護層150。一非導電黏著層180係可形成於該第二有機保護層150上,以嵌埋該些連接端子170。
在本較佳實施例中,該重配置線路層140係可另包含一虛置圖案242,該第一有機保護層130係可另具有一槽孔233,其係可顯露該晶片110之該主動面111與該封膠層120之該周邊表面121之間的接縫,該虛置圖案242係可填入至該槽孔233。該虛置圖案242可以增加對該晶片110之主動面111之抗應力特性。並且,即
使該虛置圖案242之斷裂亦不會造成該重配置線路層140之扇出線路的電性連接失敗。
因此,本發明係提供一種終極薄扇出型晶片封裝構造200,其包含之該封膠層120內的縱向導通元件160只需要貫穿該封膠層120而易於製作,並且該重配置線路層140不易斷裂。並且,可以應用於立體封裝堆疊(POP)產品並符合薄化需求。
以上所揭露的僅為本發明較佳實施例而已,當然不能以此來限定本發明之權利範圍,因此依本發明權利要求所作的等同變化,仍屬本發明所涵蓋的範圍。
110‧‧‧晶片
111‧‧‧主動面
112‧‧‧背面
113‧‧‧側面
114‧‧‧銲墊
120‧‧‧封膠層
130‧‧‧第一有機保護層
131‧‧‧扇入開孔
132‧‧‧扇出開孔
140‧‧‧重配置線路層
141‧‧‧扇出墊
142‧‧‧虛置圖案
150‧‧‧第二有機保護層
151‧‧‧接合孔
160‧‧‧縱向導通元件
170‧‧‧連接端子
171‧‧‧虛置端子
180‧‧‧非導電黏著層
190‧‧‧虛置墊
Claims (10)
- 一種終極薄扇出型晶片封裝構造,包含:一晶片,係具有一主動面、一背面以及複數個側面,其中複數個銲墊係設置於該主動面上;一封膠層,係包覆該晶片之該些側面,該封膠層係提供有一由該主動面擴張之周邊表面,該封膠層與該晶片之兩者厚度係控制為一致,並且該封膠層不覆蓋該晶片之該主動面與該背面;一第一有機保護層,係順從於該封膠層與該晶片上,該第一有機保護層係覆蓋於該晶片之該主動面與該封膠層之該周邊表面,該第一有機保護層係具有複數個扇入開孔與複數個扇出開孔,該些扇入開孔係顯露該些銲墊,該些扇出開孔係位於該封膠層之該周邊表面;一重配置線路層,係形成於該第一有機保護層上,該重配置線路層係經由該些扇入開孔連接至該些銲墊並延伸至該些扇出開孔,該重配置線路層係具有複數個扇出墊,其係經由該些扇出開孔設置於該封膠層之該周邊表面;一第二有機保護層,係順從於該第一有機保護層上,以覆蓋該重配置線路層;以及複數個縱向導通元件,係嵌埋於該封膠層中並接合至該些扇出墊。
- 如申請專利範圍第1項所述之終極薄扇出型晶片封裝構造,另包含複數個連接端子,其係設置於該些扇出墊而突出於該第二有機保護層。
- 如申請專利範圍第2項所述之終極薄扇出型晶片封裝構造,其中該些連接端子係位於一由該封膠層縱向投射之周邊覆蓋區域,而不位於一由該晶片縱向投射之中央覆蓋區域。
- 如申請專利範圍第2項所述之終極薄扇出型晶片封裝構造,另包含一非導電黏著層,其係形成於該第二有機保護層上,以嵌埋該些連接端子。
- 如申請專利範圍第2項所述之終極薄扇出型晶片封裝構造,其中該重配置線路層係另包含一虛置圖案,其係形成於該第一有機保護層上,複數個虛置端子係設置於該虛置圖案上而突出於該第二有機保護層,並且複數個虛置墊係設置於該封膠層共平面於該背面之一擴散表面,並對準於該些虛置端子。
- 如申請專利範圍第1項所述之終極薄扇出型晶片封裝構造,其中該重配置線路層係另包含一虛置圖案,該第一有機保護層係另具有一槽孔,其係顯露該晶片之該主動面與該封膠層之該周邊表面之間的接縫,該虛置圖案係填入至該槽孔。
- 如申請專利範圍第1至6項任一項所述之終極薄扇出型晶片封裝構造,其中該些縱向導通元件係為模封貫孔。
- 一種終極薄扇出型晶片封裝構造之製造方法,包含:設置一晶片在一暫時載體上,該晶片係具有一主動面、一背面以及複數個側面,其中複數個銲墊係設置於該主動面上,該主動面係貼附於該暫時載體;形成一封膠層在該暫時載體上,以密封該晶片,該封膠層係包覆該晶片之該些側面; 降低該封膠層之厚度,使得該封膠層與該晶片之兩者厚度係控制為一致,並且該封膠層不覆蓋該晶片之該主動面與該背面;由該暫時載體剝離該封膠層,該封膠層係提供有一由該主動面擴張之周邊表面;順從地形成一第一有機保護層於該封膠層與該晶片上,該第一有機保護層係覆蓋於該晶片之該主動面與該封膠層之該周邊表面;圖案化該第一有機保護層,該第一有機保護層係具有複數個扇入開孔與複數個扇出開孔,該些扇入開孔係顯露該些銲墊,該些扇出開孔係位於該封膠層之該周邊表面;形成一重配置線路層於該第一有機保護層上,該重配置線路層係經由該些扇入開孔連接至該些銲墊並延伸至該些扇出開孔,該重配置線路層係具有複數個扇出墊,其係經由該些扇出開孔設置於該封膠層之該周邊表面;形成一第二有機保護層於該第一有機保護層上,以覆蓋該重配置線路層;以及嵌埋複數個縱向導通元件於該封膠層中,並且該些縱向導通元件係接合至該些扇出墊。
- 如申請專利範圍第8項所述之終極薄扇出型晶片封裝構造之製造方法,另包含一單體化切割步驟,以形成上述單體化之終極薄扇出型晶片封裝構造,其中在單體化切割步驟之前的上述前置步驟係實施於晶圓等級。
- 如申請專利範圍第8項所述之終極薄扇出型晶片封裝構造之 製造方法,另包含一單體化切割步驟,以形成上述單體化之終極薄扇出型晶片封裝構造,其中在單體化切割步驟之前的上述前置步驟係實施於面板等級。
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2018
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI733056B (zh) * | 2018-09-19 | 2021-07-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Also Published As
Publication number | Publication date |
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US20170186678A1 (en) | 2017-06-29 |
US9899307B2 (en) | 2018-02-20 |
US10121736B2 (en) | 2018-11-06 |
TWI628757B (zh) | 2018-07-01 |
US20180145015A1 (en) | 2018-05-24 |
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