TWI284403B - Package structure and stiffener ring - Google Patents
Package structure and stiffener ring Download PDFInfo
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- TWI284403B TWI284403B TW94146558A TW94146558A TWI284403B TW I284403 B TWI284403 B TW I284403B TW 94146558 A TW94146558 A TW 94146558A TW 94146558 A TW94146558 A TW 94146558A TW I284403 B TWI284403 B TW I284403B
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- reinforcing ring
- wafer
- package structure
- wafer carrier
- ring
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
1284403 .1284403 .
三達編號TW2488PA 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種封裝結構’且特別是有關於具有 一種加固環(stiffener ring)之封裝結構。 【先前技術】 半導體封裝技術發展迅速,各式晶片藉由封裝技術達 到保護晶片且避免晶片受潮之目的’封裝結構更用以導引 B.晶片之内部導線路與印刷電路板之導線電性連接。 請同時參照第1A〜1B圖,第1A圖繪示傳統之封裝结 • 構的分解示意圖。第1B圖繪示第1A圖之封敦結構組合示 ,意圖。封裝結構10 0包括一散熱片11 〇、一加固環12 〇、 一晶片130、一基板140以及數個錫球170。散熱片11〇 係設置在加固環120之上表面121上,加固環120與基板 140藉由膠體145黏合。晶片130設置於基板140上,且 _ 晶片130包括數個凸塊160,如第1B圖所示。錫球170係 形成於基板140下方。封裝結構更100包括一底膠147, - 底膠147係藉由一點膠製程將底膠147填充於晶片130與 ‘基板140之間的間隙151,用以保護凸塊,如第1B圖 所示。 加固環120用以防止基板140之翹曲(Warpage)現 ,象。然而傳統之封裝結構100的加固環120具有一定程度 之寬度用以避免基板140發生翹曲變形現象。因此加固環 120與晶片130之間的底膠溢流範圍149狹小,而導致底 6 1284403TRIA TW2488PA IX. Description of the Invention: [Technical Field] The present invention relates to a package structure and particularly relates to a package structure having a stiffener ring. [Prior Art] The semiconductor packaging technology is developing rapidly. Various types of wafers are used to protect the wafer and protect the wafer from moisture by the packaging technology. The package structure is used to guide the electrical connection between the internal conductive lines of the wafer and the printed circuit board. . Please refer to FIG. 1A to FIG. 1B at the same time, and FIG. 1A is a schematic exploded view of a conventional package structure. Figure 1B shows the combination of the structure of the seal of Figure 1A, the intention. The package structure 100 includes a heat sink 11 , a reinforcement ring 12 , a wafer 130 , a substrate 140 , and a plurality of solder balls 170 . The heat sink 11 is disposed on the upper surface 121 of the reinforcing ring 120, and the reinforcing ring 120 and the substrate 140 are bonded by the glue 145. The wafer 130 is disposed on the substrate 140, and the wafer 130 includes a plurality of bumps 160 as shown in FIG. 1B. A solder ball 170 is formed under the substrate 140. The package structure 100 further includes a primer 147, and the primer 147 is filled with a primer 147 between the wafer 130 and the 'substrate 140 by a one-step adhesive process to protect the bumps, as shown in FIG. 1B. Show. The reinforcing ring 120 is used to prevent warpage of the substrate 140. However, the reinforcing ring 120 of the conventional package structure 100 has a certain degree of width to avoid warping deformation of the substrate 140. Therefore, the underfill overflow range 149 between the reinforcing ring 120 and the wafer 130 is narrow, resulting in a bottom 6 1284403
‘三達編號TW2488PA 膠147在點膠製程中容易流向加固環120。使得底膠147 無法完全流入晶片130與基板140之間的間隙151内,造 成底膠間隙151内具有孔洞152 (void)。不僅使得凸塊 160無法受到完整地保護,更降低封裝結構100之結構強 度。因此,如何避免間隙151具有孔洞152實為一極待解 決之重要問題。 【發明内容】 B 有鑑於此,本發明的目的就是在提供一種封裝結構, 其針對加固環的結構設計加以改良,使得加固環能維持原 - 來防止晶片承載體翹曲變形的功能,並且讓封裝結構在進 - 行點膠製程中,可有效地將底膠佈滿晶片與晶片承載體之 間隙。不僅防止晶片承載體翹曲變形,且維持加固環與散 熱片之接觸面積,更可完整地以底膠保護凸塊。大大地增 加封裝結構之結構強度。 > 根據本發明的目的,提出一種封裝結構。封裝結構包 括一晶片承載體、一晶片、一加固環及一散熱片。晶片設 . 置於晶片承載體上,並與晶片承載體電性連接。加固環設 、 置於晶片承載體上,並環繞晶片。加固環具有一第一表面 及一第二表面。第二表面係與第一表面相對,第一表面之 面積大於第二表面之面積。當第二表面貼合於晶片承載體 上時,加固環與晶片承載體之間形成一容置空間。散熱片 設置於晶片及加固環上。 根據本發明的另一目的,提出一種加固環,應用於一 7 1284403‘Sanda number TW2488PA glue 147 easily flows to the reinforcement ring 120 during the dispensing process. The primer 147 is not allowed to completely flow into the gap 151 between the wafer 130 and the substrate 140, resulting in a void 152 (void) in the underfill gap 151. Not only does the bump 160 be completely protected, but the structural strength of the package structure 100 is further reduced. Therefore, how to avoid the gap 151 having the hole 152 is an important problem to be solved. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a package structure which is improved in structural design of a reinforcing ring so that the reinforcing ring can maintain the original function of preventing warpage of the wafer carrier, and The package structure can effectively fill the gap between the wafer and the wafer carrier during the in-line dispensing process. Not only the warpage deformation of the wafer carrier is prevented, but also the contact area between the reinforcing ring and the heat sink is maintained, and the bump can be completely protected by the primer. The structural strength of the package structure is greatly increased. > In accordance with the purpose of the present invention, a package structure is proposed. The package structure includes a wafer carrier, a wafer, a reinforcement ring, and a heat sink. The wafer is placed on the wafer carrier and electrically connected to the wafer carrier. The reinforcing ring is placed on the wafer carrier and surrounds the wafer. The reinforcing ring has a first surface and a second surface. The second surface is opposite the first surface, the area of the first surface being greater than the area of the second surface. When the second surface is attached to the wafer carrier, an accommodating space is formed between the reinforcing ring and the wafer carrier. The heat sink is disposed on the wafer and the reinforcing ring. According to another object of the present invention, a reinforcement ring is proposed for use in a 7 1284403
三達編號TW2488PA 封裝結構上。此封裝結構包括晶片及基板’且晶片係與基 板電性連接。加固環包括一第一表面及一第二表面。第二 表面係與第一表面相對,第一表面之面積大於第二表面之 面積。當第二表面貼合於基板上時,加固環與基板之間形 成一容置空間。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明 如下: 【實施方式】 第一實施例 請參照第2A圖,其繪示依照本發明之第一實施例的 封裝結構之分解示意圖。封裝結構200包括一晶片承載體 240、一晶片230、一加固環220及一散熱片210。散熱片 210設置於晶片230及加固環220上,用以幫助晶片230 散熱。晶片230設置於晶片承載體240上,並與晶片承載 體240電性連接。加固環220設置於晶片承載體240上, 並環繞於晶片230,且加固環220具有一第一表面221及 一第二表面222。第二表面222係與第一表面221相對, 且第一表面221之面積大於第二表面222之面積。 請參照第2B圖,其繪示依照本發明之第一實施例的 封裝結構之組合侧視圖。當加固環220之第二表面222以 一膠體245貼合於晶片承載體240上時,加固環220與晶 片承載體240之間形成一容置空間250。容置空間250係 8 1284403The Santa Claus number is on the TW2488PA package structure. The package structure includes a wafer and a substrate ' and the wafer is electrically connected to the substrate. The reinforcing ring includes a first surface and a second surface. The second surface is opposite the first surface, the area of the first surface being greater than the area of the second surface. When the second surface is attached to the substrate, an accommodating space is formed between the reinforcing ring and the substrate. The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the preferred embodiments of the invention. Figure is an exploded perspective view of a package structure in accordance with a first embodiment of the present invention. The package structure 200 includes a wafer carrier 240, a wafer 230, a reinforcement ring 220, and a heat sink 210. The heat sink 210 is disposed on the wafer 230 and the reinforcement ring 220 to help the heat dissipation of the wafer 230. The wafer 230 is disposed on the wafer carrier 240 and electrically connected to the wafer carrier 240. The reinforcing ring 220 is disposed on the wafer carrier 240 and surrounds the wafer 230. The reinforcing ring 220 has a first surface 221 and a second surface 222. The second surface 222 is opposite to the first surface 221, and the area of the first surface 221 is larger than the area of the second surface 222. Referring to Figure 2B, a side view of a combination of package structures in accordance with a first embodiment of the present invention is shown. When the second surface 222 of the reinforcing ring 220 is attached to the wafer carrier 240 by a glue 245, an accommodating space 250 is formed between the reinforcing ring 220 and the wafer carrier 240. Housing space 250 series 8 1284403
三達編號TW2488PA 沿著加固環240之向内傾斜之内緣配置,由於加固環第一 表面221之面積大於第二表面222之面積,因此容置空間 250形成一上窄下寬之斜口槽,用以增加點膠製程中之底 膠247的溢流範圍249。至於點膠製成之細部步驟,在此 附圖並加以詳細說明如下。 請同時參照第3A〜3C圖,其繪示本發明之第一實施 例的封裝結構之點膠製程流程圖。首先,如第3A圖所示, 將晶片230設置於晶片承載體240上。並塗佈一膠體245 B 於晶片承載體240之表面的邊緣處,再將加固環220黏著 於晶片承載體240上,此時加固環220之内緣與晶片承載 ' 體240之間形成一容置空間250,由於加固環第一表面221 - 之面積大於第二表面222之面積,因此容置空間250係為 一上窄下寬之斜口槽。 接著,如第3B圖所示,在晶片230與加固環220之 間滴入一底膠247。底膠247藉由毛細現象擴散於晶片230 _ 與晶片承載體240之間隙251。由於容置空間250底部具 有一較大之溢流範圍249,因此底膠247在擴散過程中不 ; 至於流動至加固環220與晶片承載體240之間隙,使得底 膠247可完全填滿晶片230與晶片承載體240之間隙251, 而不具有任何孔洞。 然後,如第3C圖所示,接著,熱固化底膠247,使 底膠247呈現固體狀以保護間隙251中之凸塊260。並且 將散熱片210設置於加固環220之第一表面221及晶片230 上,用以幫助晶片散熱。由於加固環220之第一表面221 9 1284403The TW2488PA is disposed along the inner edge of the inward slanting of the reinforcing ring 240. Since the area of the first surface 221 of the reinforcing ring is larger than the area of the second surface 222, the accommodating space 250 forms an oblique groove with an upper narrow width. To increase the overflow range 249 of the primer 247 in the dispensing process. As for the detailed steps of dispensing, the drawings are described in detail below. Referring to Figures 3A to 3C, a flow chart of the dispensing process of the package structure of the first embodiment of the present invention is shown. First, as shown in FIG. 3A, the wafer 230 is placed on the wafer carrier 240. And coating a colloid 245 B at the edge of the surface of the wafer carrier 240, and then bonding the reinforcing ring 220 to the wafer carrier 240. At this time, the inner edge of the reinforcing ring 220 forms a space with the wafer carrying body 240. The space 250 is such that the area of the first surface 221 - of the reinforcing ring is larger than the area of the second surface 222 , so that the accommodating space 250 is an oblique groove having an upper narrow width. Next, as shown in Fig. 3B, a primer 247 is dropped between the wafer 230 and the reinforcing ring 220. The primer 247 is diffused by the capillary phenomenon in the gap 251 between the wafer 230 and the wafer carrier 240. Since the bottom of the accommodating space 250 has a large overflow range 249, the primer 247 does not flow during the diffusion process; as for the gap between the reinforcing ring 220 and the wafer carrier 240, the primer 247 can completely fill the wafer 230. There is a gap 251 with the wafer carrier 240 without any holes. Then, as shown in Fig. 3C, the primer 247 is then thermally cured so that the primer 247 is solid to protect the bumps 260 in the gap 251. The heat sink 210 is disposed on the first surface 221 of the reinforcing ring 220 and the wafer 230 to help dissipate heat from the wafer. Due to the first surface of the reinforcement ring 220 221 9 1284403
三達編號TW2488PA 於本發明之範圍。此外,加固環可為一體成型之結構,且 加固環之材質可選用高導熱係數且堅硬之材料,例如金 屬、陶瓷或聚合材料,更有效地防止基板翹曲及幫助晶片 散熱。另外5晶片承載體可以是一導線架或一基板。晶片 可藉由覆晶接合技術(flip chip),或者是表面黏著技術 (surface mounting technology,SMT)設置於晶片承載體 上。 本發明上述實施例所揭露之封裝結構,其將加固環的 B 結構設計加以改良,使得加固環維持原來防止晶片承載體 翹曲變形的功能,並且讓封裝結構在進行點膠製程中,可 有效地將底膠佈滿晶片與晶片承載體之間隙。不僅防止晶 片承載體翹曲變形及維持加固環與散熱片之接觸面積,更 可完整地以底膠保護凸塊,大大地增加封裝結構之結構強 度。 綜上所述,雖然本發明已以較佳實施例揭露如上,然 > 其並非用以限定本發明,任何熟習此技藝者,在不脫離本 發明之精神和範圍内,當可作各種之更動與潤飾,因此本 . 發明之保護範圍當視後附之申請專利範圍所界定者為準。 11 1284403Sanda number TW2488PA is within the scope of the invention. In addition, the reinforcing ring can be an integrally formed structure, and the material of the reinforcing ring can be made of a material having high thermal conductivity and hardness, such as metal, ceramic or polymer material, which can more effectively prevent the substrate from warping and help the heat dissipation of the wafer. The other 5 wafer carrier can be a lead frame or a substrate. The wafer can be placed on the wafer carrier by flip chip or surface mounting technology (SMT). The package structure disclosed in the above embodiments of the present invention improves the B structure design of the reinforcing ring, so that the reinforcing ring maintains the function of preventing the warpage deformation of the wafer carrier, and the package structure can be effectively used in the dispensing process. The underfill is filled with the gap between the wafer and the wafer carrier. It not only prevents the wafer carrier from warping and maintaining the contact area between the reinforcing ring and the heat sink, but also completely protects the bump with the primer, greatly increasing the structural strength of the package structure. In the above, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make various kinds without departing from the spirit and scope of the invention. Modifications and refinements, therefore, the scope of protection of this invention is subject to the definition of the scope of the patent application. 11 1284403
三達編號TW2488PA 【圖式簡單說明】 第1A圖繪示傳統之封裝結構的分解示意圖。 第1B圖繪示第1A圖之封裝結構組合示意圖。 第2A圖繪示依照本發明之第一實施例的封裝結構之 分解示意圖 第2B圖繪示依照本發明之第一實施例的封裝結構之 組合侧視圖。 第3A〜3C圖繪示本發明之第一實施例的封裝結構之 >點膠製程絲目。 第4A〜4B圖繪示依照本發明之第二實施例的封裝結 ^ 構之點膠流程圖。 【主要元件符號說明】 100、200、400 :封裝結構 110、210 :散熱片 I 120、220、420 :加固環 121 :上表面 130、230 :晶片 140、240 :晶片承載體 145、245 :膠體 147、247 :底膠 149、249、449 :溢流範圍 151、251 :間隙 152 :孔洞 12 1284403Sanda number TW2488PA [Simple description of the diagram] Figure 1A shows an exploded view of the conventional package structure. FIG. 1B is a schematic diagram showing the combination of the package structure of FIG. 1A. 2A is a schematic exploded perspective view of a package structure in accordance with a first embodiment of the present invention. FIG. 2B is a combined side view of a package structure in accordance with a first embodiment of the present invention. 3A to 3C are views showing the package structure of the first embodiment of the present invention. 4A to 4B are views showing a dispensing flow chart of a package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100, 200, 400: package structure 110, 210: heat sink I 120, 220, 420: reinforcement ring 121: upper surface 130, 230: wafer 140, 240: wafer carrier 145, 245: colloid 147, 247: primer 149, 249, 449: overflow range 151, 251: gap 152: hole 12 1284403
三達編號TW2488PA 221 :第一表面 222 :第二表面 250、450 :容置空間 • 160、260 :凸塊 170、270 :錫球Sanda number TW2488PA 221: first surface 222: second surface 250, 450: accommodation space • 160, 260: bumps 170, 270: solder balls
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Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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TW94146558A TWI284403B (en) | 2005-12-26 | 2005-12-26 | Package structure and stiffener ring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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TW94146558A TWI284403B (en) | 2005-12-26 | 2005-12-26 | Package structure and stiffener ring |
Publications (2)
Publication Number | Publication Date |
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TW200725856A TW200725856A (en) | 2007-07-01 |
TWI284403B true TWI284403B (en) | 2007-07-21 |
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TW94146558A TWI284403B (en) | 2005-12-26 | 2005-12-26 | Package structure and stiffener ring |
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US11101236B2 (en) | 2018-08-31 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
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