CN106057747B - Semiconductor package including heat spreader and method of manufacturing the same - Google Patents

Semiconductor package including heat spreader and method of manufacturing the same Download PDF

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Publication number
CN106057747B
CN106057747B CN201610110151.1A CN201610110151A CN106057747B CN 106057747 B CN106057747 B CN 106057747B CN 201610110151 A CN201610110151 A CN 201610110151A CN 106057747 B CN106057747 B CN 106057747B
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Prior art keywords
heat spreader
semiconductor chip
adhesive film
semiconductor
package
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CN201610110151.1A
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CN106057747A (en
Inventor
金载春
黄熙情
张彦铢
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Disclosed are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a semiconductor chip on the package substrate; a heat spreader on the semiconductor chip; a molding layer; an adhesive film between the semiconductor chip and the heat spreader; and a through hole passing through the heat sink. The heat sink includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and sidewalls of the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader.

Description

Semiconductor package including heat spreader and method of manufacturing the same
This application claims the rights of korean patent application No. 10-2015-0050149 filed on korean intellectual property office at 9.4.2015 and korean patent application No. 10-2015-0077974 filed on 3.6.2.2015, the disclosures of which are incorporated herein by reference in their entireties.
Technical Field
The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor package and a method of manufacturing the same.
Background
Generally, as the size of electronic devices has been reduced, the size of semiconductor packages has been reduced. A semiconductor package including a semiconductor device mounted on a Printed Circuit Board (PCB) protects the semiconductor device from an external environment and electrically connects the semiconductor device to an external device.
Disclosure of Invention
According to example embodiments of the inventive concepts, a semiconductor package may include: a semiconductor chip on the package substrate; a heat spreader on the semiconductor chip, the heat spreader including a first surface and a second surface; a molding layer covering sidewalls of the semiconductor chip and the heat spreader and exposing a first surface of the heat spreader; an adhesive film between the semiconductor chip and the heat spreader, wherein the adhesive film is on the second surface of the heat spreader; and a through hole passing through the heat sink.
In example embodiments of the inventive concepts, the first surface of the heat sink may be flat and the second surface of the heat sink may be uneven.
In example embodiments of the inventive concepts, a portion of the second surface of the heat spreader may be in direct contact with the semiconductor chip.
In example embodiments of the inventive concepts, the first surface of the heat sink may be flat, the first portion of the second surface of the heat sink may be uneven, and the second portion of the second surface of the heat sink may be flat.
In example embodiments of the inventive concepts, the second portion of the second surface of the heat spreader may be in direct contact with the semiconductor chip, and a portion of the first portion of the second surface of the heat spreader is in direct contact with the semiconductor chip.
In example embodiments of the inventive concepts, the through-hole may pass through the heat sink and may extend from the first surface of the heat sink to the first portion of the second surface of the heat sink.
In example embodiments of the inventive concepts, the through-hole may expose the adhesive film.
In example embodiments of the inventive concepts, the first surface of the heat spreader may be substantially coplanar with the first surface of the molding layer.
In example embodiments of the inventive concepts, a surface roughness of the second surface of the heat sink may be greater than a surface roughness of the first surface of the heat sink.
In example embodiments of the inventive concepts, the adhesive film may include a thermosetting material.
According to example embodiments of the inventive concepts, a semiconductor package device may include: a semiconductor chip on the package substrate; a heat spreader on the semiconductor chip; a molding layer covering sidewalls of the heat spreader and sidewalls of the semiconductor chip; and an adhesive film disposed between the heat spreader and the semiconductor chip. The heat spreader may include a first surface exposed through the molding layer and a second surface facing the semiconductor chip and having a surface roughness greater than that of the first surface.
In example embodiments of the inventive concepts, the adhesive film may include a thermosetting material.
In example embodiments of the inventive concepts, the first surface of the heat sink may be flat and the second surface of the heat sink may be uneven. A portion of the second surface of the heat spreader may be in direct contact with the semiconductor chip.
In example embodiments of the inventive concepts, the semiconductor package may further include a plurality of through holes passing through the heat spreader and exposing the adhesive film.
In example embodiments of the inventive concepts, the second surface of the heat sink may include protruding portions and recessed portions between the protruding portions. The protruding portion may be in direct contact with the semiconductor chip. The adhesive film may be in the recessed portion.
In example embodiments of the inventive concept, the protruding portion may have a sharp tip or an arc-shaped tip.
In example embodiments of the inventive concepts, the protruding portion may have a flat surface.
In example embodiments of the inventive concepts, the adhesive film may be on a portion of the first surface of the heat spreader, a sidewall of the heat spreader, and a sidewall of the semiconductor chip.
According to example embodiments of the inventive concepts, a semiconductor package may include: a semiconductor chip on the package substrate; a first heat spreader on the semiconductor chip; an adhesive film on a portion of the first surface and the sidewall of the first heat spreader and on the sidewall of the semiconductor chip; and a molding layer on a portion of the adhesive film and covering the first heat spreader and the sidewalls of the semiconductor chip. The first heat spreader may include a first surface exposed through the adhesive film and a second surface facing and contacting the semiconductor chip.
In example embodiments of the inventive concepts, the semiconductor package may further include a second heat spreader on the first surface of the first heat spreader and in contact with the first heat spreader.
In example embodiments of the inventive concepts, the first heat spreader may extend to the first surface of the molding layer.
In example embodiments of the inventive concepts, the adhesive film may extend to the first surface of the package substrate at a side of the semiconductor chip.
According to example embodiments of the inventive concepts, a method of manufacturing a semiconductor package may include: mounting a semiconductor chip on a package substrate; bonding a heat spreader to the semiconductor chip through an adhesive film, the heat spreader including a first surface, a second surface having a surface roughness greater than a surface roughness of the first surface, and at least one through-hole therein; and covering the sidewalls of the heat spreader and the sidewalls of the semiconductor chip with a molding layer.
In example embodiments of the inventive concepts, the molding layer may include a first surface that is substantially coplanar with a first surface of the heat spreader.
In example embodiments of the inventive concepts, the adhesive film may be between the semiconductor chip and the heat spreader, and may be exposed by the at least one through hole.
In example embodiments of the inventive concepts, the at least one through hole may include a plurality of through holes passing through the heat sink, and the at least one through hole may discharge bubbles generated between the semiconductor chip and the heat sink when the heat sink is coupled to the semiconductor chip.
In example embodiments of the inventive concepts, the bonding of the heat spreader may include bringing a portion of the second surface of the heat spreader and the semiconductor chip into contact with each other.
In example embodiments of the inventive concepts, the second surface of the heat sink may include protruding portions and recessed portions between the protruding portions, and the adhesive film may be in the recessed portions.
In example embodiments of the inventive concept, the protruding portion may include a sharp or curved tip.
According to example embodiments of the inventive concepts, a method for manufacturing a semiconductor package may include: mounting a semiconductor chip on a package substrate; providing a first heat spreader on a semiconductor chip, the first heat spreader comprising a metal, a first surface, and a second surface; bonding the semiconductor chip to the first heat spreader with an adhesive film; and covering the sidewalls of the first heat spreader and the sidewalls of the semiconductor chip with a molding layer. The step of providing the first heat sink may include: at least a portion of the second surface of the first heat spreader is brought into contact with the semiconductor chip. The second surface of the first heat sink may have a surface roughness greater than a surface roughness of the first surface of the first heat sink.
In example embodiments of the inventive concepts, the adhesive film is on the second surface of the first heat spreader.
In example embodiments of the inventive concepts, the step of providing the first heat sink may further include forming a plurality of through holes passing through the first heat sink.
In example embodiments of the inventive concepts, the step of bonding the semiconductor chip to the first heat sink may include: an adhesive film is attached to a portion of the first surface of the first heat spreader, the sidewalls of the first heat spreader, and the sidewalls of the semiconductor chip.
In example embodiments of the inventive concepts, the method may further include: a second heat spreader is disposed on the first surface of the first heat spreader and the first surface of the molding layer, the second heat spreader being in contact with the first heat spreader.
According to example embodiments of the inventive concepts, a semiconductor package may include: a semiconductor chip disposed on the substrate; a heat spreader disposed on the semiconductor chip; an adhesive film disposed on a sidewall of the heat spreader and a sidewall of the semiconductor chip, wherein a first surface of the heat spreader is exposed by the adhesive film; and a molding layer disposed on the adhesive film along a sidewall of the heat spreader and a sidewall of the semiconductor chip.
In example embodiments of the inventive concepts, the heat sink may include a high thermal conductive material.
In example embodiments of the inventive concepts, an edge of the first surface of the heat sink may be covered by the adhesive film.
Drawings
The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1A, 1B, 1C, 1D, 1E and 1F are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept;
fig. 1D is an enlarged view illustrating a portion of a structure including the heat sink illustrated in fig. 1C according to an example embodiment of the inventive concept;
fig. 1E is a sectional view illustrating a structure including the heat sink illustrated in fig. 1D according to an example embodiment of the inventive concept;
fig. 1G and 1H are cross-sectional views illustrating a structure in which a semiconductor chip is mounted on a substrate according to an example embodiment of the inventive concept;
fig. 2A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 2B is a plan view of the semiconductor package shown in fig. 2A according to an example embodiment of the inventive concepts;
fig. 2C is a plan view illustrating the semiconductor package illustrated in fig. 2A according to an example embodiment of the inventive concepts;
fig. 2D is a cross-sectional view illustrating the semiconductor package shown in fig. 2A according to an example embodiment of the inventive concepts;
fig. 3A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 3B is a plan view of the semiconductor package shown in fig. 3A according to an example embodiment of the inventive concepts;
fig. 4A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 4B is a cross-sectional view illustrating a portion of the structure including the heat sink illustrated in fig. 4A according to an example embodiment of the inventive concepts;
fig. 4C is a plan view of the semiconductor package shown in fig. 4A according to an example embodiment of the inventive concepts;
fig. 5A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 5B is a plan view of the semiconductor package shown in fig. 5A according to an example embodiment of the inventive concepts;
fig. 6A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 6B is a plan view of the semiconductor package shown in fig. 6A according to an example embodiment of the inventive concepts;
fig. 7 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts;
fig. 8A, 8B, 8C and 8D are sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept;
fig. 8E is a plan view of the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts;
fig. 8F is a plan view illustrating the semiconductor package illustrated in fig. 8D according to an example embodiment of the inventive concepts;
fig. 9A is a cross-sectional view illustrating the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts;
fig. 9B is a cross-sectional view illustrating the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts;
fig. 10A is a schematic block diagram illustrating a memory system including at least one semiconductor package according to an example embodiment of the inventive concepts; and
fig. 10B is a schematic block diagram illustrating an electronic system including at least one semiconductor package according to an example embodiment of the inventive concepts.
Detailed Description
Example embodiments of the inventive concept will now be described more fully hereinafter with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. In the drawings, the size of layers and regions may be exaggerated for clarity.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
Further, example embodiments will be described using cross-sectional and/or plan views as idealized drawings of the inventive concept. Accordingly, the shape of the figures may be modified according to manufacturing techniques and/or tolerances. Accordingly, example embodiments of the inventive concept are not limited to the specific shapes illustrated in the drawings, but may include other shapes that may be created according to a manufacturing process.
Throughout the specification, the same reference numerals or the same reference numerals may denote the same elements.
Fig. 1A, 1B, 1C, 1D, 1E and 1F are sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. Fig. 1D is an enlarged view illustrating a portion of the structure including the heat sink illustrated in fig. 1C according to an example embodiment of the inventive concept. Fig. 1E is a cross-sectional view illustrating a structure including a heat sink illustrated in fig. 1D according to an example embodiment of the inventive concept. Fig. 1G and 1H are cross-sectional views illustrating a structure in which a semiconductor chip is mounted on a substrate according to an example embodiment of the inventive concept.
Referring to fig. 1A, a semiconductor chip 130 may be mounted on a package substrate 110. The semiconductor chip 130 may include a memory chip, a logic chip, or a combination thereof. As an example, the semiconductor chip 130 may be an Application Processor (AP). The semiconductor chip 130 may include a top surface 130a and a bottom surface 130b opposite the top surface 130 a. In example embodiments of the inventive concepts, the top surface 130a of the semiconductor chip 130 may be a non-active surface, and the bottom surface 130b of the semiconductor chip 130 may be an active surface on which an integrated circuit is disposed. In example embodiments of the inventive concepts, the top surface 130a of the semiconductor chip 130 may be an active surface on which an integrated circuit is disposed, and the bottom surface 130b of the semiconductor chip 130 may be a non-active surface. The semiconductor chip 130 may be mounted on the package substrate 110 in such a manner that the bottom surface 130b of the semiconductor chip 130 faces the top surface of the package substrate 110. The semiconductor chip 130 may be mounted on the package substrate 110 by a flip chip bonding technique. Solder balls 125 may be disposed between the semiconductor chip 130 and the package substrate 110 to connect the semiconductor chip 130 to the package substrate 110. In example embodiments of the inventive concept, as shown in fig. 1G, in the case where the solder balls 125 are disposed between the semiconductor chip 130 and the package substrate 110, the underfill member 127 may be further disposed between the semiconductor chip 130 and the package substrate 110.
In example embodiments of the inventive concept, as shown in fig. 1H, a Through Silicon Via (TSV)129 may be provided in the semiconductor chip 130. TSVs 129 may pass completely or partially through semiconductor chip 130 and may be connected to solder balls 125. The underfill member 127 may be further disposed between the semiconductor chip 130 and the package substrate 110 with the solder balls 125 disposed between the semiconductor chip 130 and the package substrate 110.
Referring to fig. 1B, a heat sink 150 may be provided. The heat sink 150 may include a metal or a metal alloy having high thermal conductivity. The heat sink 150 may comprise, for example, copper, aluminum, copper alloys, and/or aluminum alloys. The heat sink 150 may include a top surface 150a and a bottom surface 150 b. The heat sink 150 may have a plate shape. The bottom surface 150b of the heat sink 150 may have a surface roughness greater than that of the top surface 150 a. As an example, the top surface 150a of the heat sink 150 may be flat, but the bottom surface 150b of the heat sink 150 may be uneven. The bottom surface 150b of the heat sink 150 may include protruding portions 152 and recessed portions 151 between the protruding portions 152. Each projection 152 may have a pointed tip, such as a pointed tip. The bottom surface 150b of the heat spreader 150 may be processed using a sand blasting process or a shot blasting process, thereby becoming uneven. In example embodiments of the inventive concept, the bottom surface 150b of the heat sink 150 may be processed using a chiseling process, thereby becoming uneven.
An adhesive film 140 may be provided to bond the heat spreader 150 to the top surface 130a of the semiconductor chip 130. The adhesive film 140 may be disposed on the bottom surface 150b of the heat spreader 150. For example, the adhesive film 140 may be attached to the bottom surface 150b of the heat spreader 150. The adhesive film 140 may include silicone or a thermosetting material containing silicone. In an example, the adhesive film 140 may include a siloxane-based material or an epoxy-based material. In another example, the adhesive film 140 may include melamine cyanurate (TMAT) or a material containing TMAT.
Referring to fig. 1C, a heat spreader 150 having an adhesive film 140 disposed on a bottom surface 150b thereof may be stacked on the top surface 130a of the semiconductor chip 130. The sidewalls of the heat spreader 150 may be aligned with the sidewalls of the semiconductor chip 130. As shown in fig. 1D, because the bottom surface 150b of the heat spreader 150 may be uneven, the contact area between the adhesive film 140 and the bottom surface 150b of the heat spreader 150 may be greater than if the bottom surface 150b of the heat spreader 150 were flat. Accordingly, the bonding strength between the heat spreader 150 and the adhesive film 140 may be increased, thereby preventing or reducing adhesive failure between the semiconductor chip 130 and the heat spreader 150. In other words, the heat spreader 150 may be prevented from being separated from the semiconductor chip 130 due to the bonding strength between the heat spreader 150 and the adhesive film 140.
The protruding portion 152 of the bottom surface 150b of the heat spreader 150 may directly contact the semiconductor chip 130. Accordingly, efficient heat conduction from the semiconductor chip 130 to the heat sink 150 can be promoted. The adhesive film 140 may be disposed in the recessed portion 151 of the bottom surface 150b of the heat spreader 150. The adhesive film 140 may fill the recessed portion 151 of the bottom surface 150b of the heat spreader 150. In example embodiments of the inventive concept, the bottom surface 150b of the heat sink 150 may include protruding portions 152 each having a top end in an arc shape as shown in fig. 1E.
Referring to fig. 1F, a molding layer 160 may be disposed on the package substrate 110. The molding layer 160 may cover the heat spreader 150 and the sidewalls of the semiconductor chip 130. A top surface 160a of the molding layer 160 may be substantially coplanar with the top surface 150a of the heat spreader 150. Since the top surface 150a of the heat sink 150 may be exposed, heat generated from the semiconductor chip 130 may be discharged to the outside through the heat sink 150. The molding layer 160 may also be disposed between the semiconductor chip 130 and the package substrate 110 with the solder balls 125 disposed between the semiconductor chip 130 and the package substrate 110. The molding layer 160 may fill a space between the bottom surface 130b of the semiconductor chip 130 and the top surface of the package substrate 110 with the solder balls 125 disposed between the bottom surface 130b of the semiconductor chip 130 and the top surface of the package substrate 110.
The external connection terminals 108 may be disposed on the bottom surface of the package substrate 110. As a result, through the above process, the semiconductor package 11 can be realized.
The semiconductor package 11 may include a semiconductor chip 130 and a heat sink 150 on the semiconductor chip 130. Since a portion of the heat spreader 150 may directly contact the semiconductor chip 130, heat generated from the semiconductor chip 130 may be discharged without using an additional heat spreader. Therefore, the thickness of the semiconductor package 11 can be reduced. In addition, since the heat sink 150 is formed of a hard material (e.g., metal), warpage of the semiconductor package 11 is suppressed or reduced. The adhesive film 140 may include a thermosetting material, so that the bonding strength between the semiconductor chip 130 and the heat spreader 150 may be maintained when the semiconductor package 11 is operated at a high temperature.
Fig. 2A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Fig. 2B is a plan view of the semiconductor package shown in fig. 2A according to an example embodiment of the inventive concepts. Fig. 2C is a plan view illustrating the semiconductor package illustrated in fig. 2A according to an example embodiment of the inventive concepts. Fig. 2D is a cross-sectional view illustrating the semiconductor package shown in fig. 2A according to an example embodiment of the inventive concepts.
Referring to fig. 2A, 2B, 2C, and 2D, the semiconductor package 12 may further include a plurality of vias 155 passing through the heat spreader 150. The through hole 155 may extend from the top surface 150a of the heat sink 150 to the bottom surface 150b of the heat sink 150 in the thickness direction of the heat sink 150. The thickness direction of the heat spreader 150 may be a direction perpendicular to the surface of the package substrate 110. The via 155 may be formed using a mechanical or laser drilling process. As an example, the through-hole 155 may be formed before the adhesive film is disposed on the bottom surface 150b of the heat spreader 150. As another example, the through-hole 155 may be formed before the heat spreader 150 having the adhesive film 140 provided on the bottom surface 150b thereof is stacked on the semiconductor chip 130.
The top surface 150a of the heat spreader 150 may be flat and may be coplanar with the top surface 160a of the molding layer 160. In example embodiments of the inventive concept, the bottom surface 150b of the heat sink 150 may be an uneven surface. In other words, the bottom surface 150b of the heat sink 150 may include protruding portions 152, each protruding portion 152 having a sharp tip as shown in fig. 1D. In example embodiments of the inventive concept, the bottom surface 150b of the heat sink 150 may be an uneven surface and may include protruding portions 152, each protruding portion 152 having a top end in an arc shape as shown in fig. 1E.
The through hole 155 may pass through the heat sink 150, and may extend from the top surface 150a of the heat sink 150 to the bottom surface 150b of the heat sink 150. The heat sink 150 may be open at both the top surface 150a and the bottom surface 150b of the heat sink 150 through the through hole 155. The vias 155 may be regularly arranged to form an array as shown in fig. 2B. For example, the through holes 155 may be arranged in a matrix shape. In example embodiments of the inventive concept, the through holes 155 may be irregularly arranged, as shown in fig. 2C. For example, the number of through holes 155 distributed in the central region of the heat sink 150 may be greater than the number of through holes 155 distributed in the peripheral region of the heat sink 150.
The through-hole 155 may expose a portion of the adhesive film 140. When the heat spreader 150 is bonded to the semiconductor chip 130, air bubbles may form in the adhesive film 140 and/or between the heat spreader 150 and the semiconductor chip 130. The air bubbles may weaken the adhesive ability of the adhesive film 140 and/or may impede heat transfer from the semiconductor chip 130 to the heat sink 150. According to example embodiments of the inventive concepts, the through-hole 155 may serve as a path for discharging air bubbles, thus preventing or reducing deterioration of the adhesive ability of the adhesive film 140 and/or deterioration of heat transfer from the semiconductor chip 130 to the heat sink 150.
As shown in fig. 2D, the adhesive film 140 may be thick enough to separate the bottom surface 150b of the heat spreader 150 from the semiconductor chip 130. Accordingly, the bonding strength between the heat spreader 150 and the semiconductor chip 130 can be increased by the adhesive film 140.
Fig. 3A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Fig. 3B is a plan view of the semiconductor package shown in fig. 3A according to an example embodiment of the inventive concepts.
Referring to fig. 3A and 3B, the semiconductor package 13 may include a heat spreader 150 having a bottom surface 150B, the bottom surface 150B having various ranges of surface roughness. The bottom surface 150b of the heat sink 150 may include a first bottom surface 150b1 and a second bottom surface 150b 2. The first bottom surface 150b1 of the heat sink 150 may have a surface roughness greater than the second bottom surface 150b2 of the heat sink 150. For example, the first bottom surface 150b1 of the heat sink 150 may include recesses and protrusions similar to or identical to the recesses 151 and protrusions 152 of the bottom surface 150b of the heat sink 150 shown in fig. 1D and/or 1E. The adhesive film 140 may be partially disposed on the first bottom surface 150b1 of the heat spreader 150, as shown in fig. 3A. In the case where a Central Processing Unit (CPU) generating a large amount of heat is disposed in the portion 132 of the semiconductor chip 130, the second bottom surface 150b2 of the heat sink 150 may be in contact with the portion 132. Therefore, the heat dissipated from the CPU to the heat sink 150 can be increased. As an example, in the case where the portion 132 where the CPU is disposed is the center area of the semiconductor chip 130, as shown by a dotted rectangle in fig. 3B, the adhesive film 140 may be disposed on both side peripheral areas of the heat spreader 150. In this case, the second bottom surface 150b2 of the heat spreader 150 may be in contact with the central region of the semiconductor chip 130. The semiconductor package 13 may further include a through hole 155 passing through the heat sink 150. The through-hole 155 may expose the adhesive film 140 on the first bottom surface 150b1 of the heat spreader 150.
Fig. 4A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Fig. 4B is a cross-sectional view illustrating a portion of the structure including the heat sink illustrated in fig. 4A according to an example embodiment of the inventive concept. Fig. 4C is a plan view of the semiconductor package shown in fig. 4A according to an example embodiment of the inventive concepts.
Referring to fig. 4A, 4B, and 4C, the semiconductor package 14 may include a heat spreader 150, and the heat spreader 150 includes a bottom surface 150B having an uneven surface. The bottom surface 150b of the heat sink 150 may include protruding portions 152 and recessed portions 151 between the protruding portions 152. As shown in fig. 4B, each protruding portion 152 contacting the semiconductor chip 130 may have a flat surface, and the adhesive film 140 may be disposed in the recessed portion 151. The adhesive film 140 may fill the recessed portion 151. Therefore, heat can be easily transferred from the semiconductor chip 130 to the heat sink 150 through the protruding portion 152. As shown in fig. 4C, the adhesive film 140 may be formed in a plurality of linear shapes uniformly distributed on the bottom surface 150b of the heat spreader 150. In other words, each of the concave portions 151 may have a shape extending along a line.
Fig. 5A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Fig. 5B is a plan view of the semiconductor package shown in fig. 5A according to an example embodiment of the inventive concepts.
Referring to fig. 5A and 5B, the semiconductor package 15 may include a heat spreader 150, the heat spreader 150 having a bottom surface 150B including various ranges of surface roughness. The bottom surface 150b of the heat sink 150 may include a first bottom surface 150b1 and a second bottom surface 150b 2. The surface roughness of the first bottom surface 150b1 may be greater than the surface roughness of the second bottom surface 150b 2. The first bottom surface 150B1 may include recesses and protrusions similar to or identical to the recesses 151 and protrusions 152 shown in fig. 4B. The second bottom surface 150B2 may have a flat surface similar to or the same as the surface of the protruding portion 152 shown in fig. 4B. The adhesive film 140 may be partially disposed on the first bottom surface 150B1 of the heat spreader 150, as shown in fig. 5B. The second bottom surface 150b2 of the heat spreader 150 may be in contact with the semiconductor chip 130. In the case where a CPU that generates a large amount of heat is provided in the portion 132 of the semiconductor chip 130, the second bottom surface 150b2 of the heat sink 150 may be in contact with the portion 132.
Fig. 6A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts. Fig. 6B is a plan view of the semiconductor package shown in fig. 6A according to an example embodiment of the inventive concepts.
Referring to fig. 6A and 6B, the semiconductor package 16 may include a heat spreader 150, the heat spreader 150 including a bottom surface 150B having a flat surface. The adhesive film 140 may extend along the bottom surface 150b of the heat spreader 150 in a sheet-type shape. The semiconductor package 16 may further include a plurality of through holes 155 capable of discharging bubbles generated when the heat sink 150 is coupled to the semiconductor chip 130. The through holes 155 may be regularly distributed as shown in fig. 6B. In example embodiments of the inventive concept, the through holes 155 may be irregularly distributed, as shown in fig. 2C.
Fig. 7 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concepts.
Referring to fig. 7, the semiconductor package 17 may be a Package On Package (POP) type package in which an upper package 17b is stacked on a lower package 17 a. The lower package 17a may include at least one of the semiconductor packages 11 to 16 described above. As an example, the semiconductor package 12 of fig. 2A may be a lower package 17 a.
The upper package 17b may include at least one upper semiconductor chip 230 mounted on the upper package substrate 115 and an upper molding layer 165 covering the upper semiconductor chip 230, wherein an adhesive member 145 is disposed between the at least one semiconductor chip 230 and the upper package substrate 115. The upper semiconductor chip 230 may be electrically connected to the upper package substrate 115 through a bonding wire 175. The lower package 17a and the upper package 17b may be electrically connected to each other through the internal connection terminal 70 penetrating the molding layer 160 of the lower package 17 a.
The semiconductor package 17 may further include a heat transfer layer 60 (e.g., a Thermal Interface Material (TIM)) disposed between the lower package 17a and the upper package 17b and in contact with the heat sink 150 of the lower package 17 a. The heat transferred from the semiconductor chip 130 of the lower package 17a to the heat sink 150 may be released to the outside of the semiconductor package 17 through the heat transfer layer 60 and the upper package substrate 115.
Fig. 8A, 8B, 8C and 8D are sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. Fig. 8E is a plan view of the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts. Fig. 8F is a plan view illustrating the semiconductor package illustrated in fig. 8D according to an example embodiment of the inventive concepts.
Referring to fig. 8A, the semiconductor chips 130 may be mounted on the package substrate 110, and the heat sinks 150 may be stacked on the semiconductor chips 130, respectively. In example embodiments of the inventive concept, the semiconductor chip 130 may be mounted on the package substrate 110 using a flip chip bonding technique. Solder balls 125 may be disposed between each semiconductor chip 130 and the package substrate 110 to connect each semiconductor chip 130 to the package substrate 110. In example embodiments of the inventive concept, the TSV 129 shown in fig. 1H may be formed in each semiconductor chip 130 to be connected to the solder ball 125. Each heat sink 150 may include a top surface 150a and a bottom surface 150b, and have a plate shape. The top surface 150a and the bottom surface 150b may be flat. In example embodiments of the inventive concept, the top surface 150a may be flat and the bottom surface 150b may be uneven. For example, the surface roughness of the bottom surface 150b may be greater than the surface roughness of the top surface 150 a.
The adhesive film 140 may be attached to the heat spreader 150. The adhesive film 140 may partially cover the top surface 150a of each heat spreader 150 to expose a portion of the top surface 150a of each heat spreader 150. The adhesive film 140 may include a thermosetting material.
Referring to fig. 8B, the adhesive film 140 may be attached to the package substrate 110 and the semiconductor chip 130. The adhesive film 140 may be cut to partially cover the top surface 150a of each heat spreader 150, the sidewalls of each heat spreader 150, and the sidewalls of each semiconductor chip 130. In addition, the adhesive film 140 may extend from a side of each semiconductor chip 130 to the top surface of the package substrate 110, and may be bent to cover a portion of the top surface of the package substrate 110.
Referring to fig. 8C, a molding layer 160 may be formed on the package substrate 110 to cover the heat spreader 150 and the sidewalls of each semiconductor chip 130. The molding layer 160 may be disposed on a portion of the adhesive film 140 and cover a portion of the adhesive film 140. The top surface 160a of the molding layer 160 may be at substantially the same level as the top surface 150a of the heat spreader 150. For example, the top surface 160a of the molding layer 160 and the top surface 150a of the heat spreader 150 may be substantially coplanar.
Referring to fig. 8D, the semiconductor package 21 may be formed through a sawing process. For example, the package substrate 110 and the molding layer 160 may be sawed into a single package unit to form the semiconductor package 21. The external connection terminals 108 may be disposed on the bottom surface of the package substrate 110 before the sawing process. The adhesive film 140 may cover the entire peripheral area of the top surface 150a of the heat spreader 150. In example embodiments of the inventive concepts, the adhesive film 140 may cover opposite peripheral areas of the top surface 150a of the heat sink 150, as shown in fig. 8E. In example embodiments of the inventive concept, the adhesive film 140 may cover an edge area of the top surface 150a of the heat sink 150, as shown in fig. 8F.
According to example embodiments of the inventive concepts, since the heat sink 150 and the semiconductor chip 130 may be in direct contact with each other, the amount of heat transferred from the semiconductor chip 130 to the heat sink 150 may be increased. Further, since the adhesive film 140 may be disposed on a portion of the top surface 150a of the heat spreader 150, a portion of the sidewall of the heat spreader 150, and a portion of the sidewall of the semiconductor chip 130, and the molding layer 160 may surround the heat spreader 150 and the sidewall of the semiconductor chip 130, stable bonding of the heat spreader 150 and the semiconductor chip 130 may be achieved. Accordingly, warpage of the semiconductor package 21 manufactured according to example embodiments of the inventive concepts may be suppressed or reduced. In addition, since the adhesive layer 140 includes a thermosetting material, the thermosetting property of the semiconductor package 21 can be improved.
Fig. 9A is a cross-sectional view illustrating the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts. Fig. 9B is a cross-sectional view illustrating the semiconductor package shown in fig. 8D according to an example embodiment of the inventive concepts.
Referring to fig. 9A, the semiconductor package 22 may further include a supplemental heat sink 250 stacked on the heat sink 150. The supplemental heat spreader 250 may comprise a material that is the same as or similar to the material of the heat spreader 150. The supplemental heat sink 250 can include, for example, at least one of aluminum, copper, an aluminum alloy, and/or a copper alloy. The supplemental heat spreader 250 may have a plate shape extending from the top surface 150a of the heat spreader 150 to the top surface 160a of the molding layer 160. Due to the supplemental heat sink 250, the area for releasing heat can be increased.
Referring to fig. 9B, the semiconductor package 23 may be a Package On Package (POP) type package including a lower package 23a and an upper package 23B stacked on the lower package 23 a. The lower package 23a may be the semiconductor package 21 shown in fig. 8D. The upper package 23b may have the same or similar structure as that of the upper package 17b shown in fig. 7.
The lower package 23a and the upper package 23b may be electrically connected together through the internal connection terminal 70 passing through the molding layer 160. The semiconductor package 23 may further include a heat transfer layer 60 (e.g., TIM) disposed between the lower package 23a and the upper package 23b and in contact with the heat sink 150.
Fig. 10A is a schematic block diagram illustrating a memory system including at least one semiconductor package according to an example embodiment of the inventive concepts. Fig. 10B is a schematic block diagram illustrating an electronic system including at least one semiconductor package according to an example embodiment of the inventive concepts.
Referring to fig. 10A, a memory system 1200 according to an example embodiment of the inventive concepts may be a semiconductor memory apparatus. For example, the storage system 1200 may be a memory card or a Solid State Drive (SSD) device. The memory system 1200 may include a memory 1210 and a memory controller 1220 that controls the exchange of data between the memory 1210 and a host 1230. A Static Random Access Memory (SRAM)1221 may be utilized as a working memory for CPU 122. The host interface unit 1223 may include a data exchange protocol of the host 1230 connected to the storage system 1200. An Error Correction Code (ECC) unit 1224 may detect and correct errors in data read from memory 1210. A memory interface unit 1225 may interface with the memory 1210. The CPU unit 1222 may perform various control operations for data exchange of the memory controller 1220. The memory 1210 and/or the memory controller 1220 may include at least one of semiconductor packages according to example embodiments of the inventive concepts.
Referring to fig. 10B, an electronic system 1300 according to an example embodiment of the inventive concepts may include, for example, a mobile device or a computer. The electronic system 1300 may include a memory system 1310, a modem 1320, a CPU 1330, a Random Access Memory (RAM)1340, and a user interface unit 1350 electrically connected to a system bus 1360. The memory system 1310 may include a memory 1311 and a memory controller 1312, the same as or similar to the memory system 1200 shown in fig. 10A. Memory system 1310 may store data and/or instructions for execution by CPU 1330 and/or store data input from outside. The electronic system 1300 may be equipped with a memory card, an SSD, a camera image sensor, and/or an application chipset. The memory system 1310, the central processing unit 1330, and/or any other elements of fig. 10B may include at least one of the semiconductor packages according to example embodiments of the inventive concepts.
Example embodiments of the inventive concepts may provide a semiconductor package having improved thermal durability and mechanical durability and a method for manufacturing the same.
Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to the exemplary embodiments without departing from the scope of the inventive concept as defined in the following claims.

Claims (15)

1. A semiconductor package, comprising:
a semiconductor chip on the package substrate;
a heat spreader on the semiconductor chip, the heat spreader including a first surface and a second surface;
a molding layer covering the sidewalls of the semiconductor chip and the sidewalls of the heat spreader and exposing the first surface of the heat spreader;
an adhesive film between the semiconductor chip and the heat spreader, wherein the adhesive film is on the second surface of the heat spreader; and
the through hole is arranged on the radiator and penetrates through the radiator,
wherein the side walls of the heat spreader are aligned with the side walls of the semiconductor chip, the second surface of the heat spreader includes an uneven surface and the uneven surface of the heat spreader is bonded to the semiconductor chip by an adhesive film,
wherein a first portion of the second surface of the heat sink is an uneven surface and a second portion of the second surface of the heat sink is a flat surface,
wherein a second portion of the second surface of the heat spreader is in direct contact with the semiconductor chip and a portion of the first portion of the second surface of the heat spreader is in direct contact with the semiconductor chip.
2. The semiconductor package of claim 1, wherein the first surface of the heat spreader is planar.
3. The semiconductor package of claim 2, wherein the via passes through the heat spreader and extends from the first surface of the heat spreader to the first portion of the second surface of the heat spreader.
4. The semiconductor package of claim 1, wherein the via exposes the adhesive film.
5. The semiconductor package of claim 1, wherein the first surface of the heat spreader is coplanar with the first surface of the molding layer.
6. The semiconductor package of claim 1, wherein a surface roughness of the second surface of the heat spreader is greater than a surface roughness of the first surface of the heat spreader.
7. The semiconductor package of claim 1, wherein the adhesive film comprises a thermoset material.
8. A semiconductor package, comprising:
a semiconductor chip on the package substrate;
a heat spreader on the semiconductor chip;
a molding layer covering sidewalls of the heat spreader and sidewalls of the semiconductor chip; and
an adhesive film disposed between the heat spreader and the semiconductor chip,
wherein, the radiator includes:
a first surface exposed by the molding layer; and
a second surface facing the semiconductor chip and having a surface roughness greater than that of the first surface,
wherein the side walls of the heat spreader are aligned with the side walls of the semiconductor chip, the second surface of the heat spreader includes an uneven surface and the uneven surface of the heat spreader is bonded to the semiconductor chip by an adhesive film,
wherein a first portion of the second surface of the heat sink is an uneven surface and a second portion of the second surface of the heat sink is a flat surface,
wherein a second portion of the second surface of the heat spreader is in direct contact with the semiconductor chip and a portion of the first portion of the second surface of the heat spreader is in direct contact with the semiconductor chip.
9. The semiconductor package of claim 8, wherein the adhesive film comprises a thermoset material.
10. The semiconductor package of claim 8, wherein the first surface of the heat spreader is planar.
11. The semiconductor package of claim 8, further comprising a plurality of vias through the heat spreader and exposing the adhesive film.
12. The semiconductor package of claim 8, wherein the first portion of the second surface of the heat spreader comprises protruding portions and recessed portions between the protruding portions, and
wherein the protruding portion directly contacts the semiconductor chip and the adhesive film is in the recessed portion.
13. The semiconductor package according to claim 12, wherein the protruding portion has a sharp tip or an arc-shaped tip.
14. The semiconductor package according to claim 12, wherein the protruding portion has a flat surface.
15. A method of fabricating a semiconductor package, the method comprising:
mounting a semiconductor chip on a package substrate;
providing a first heat spreader on a semiconductor chip, the first heat spreader comprising a metal, a first surface, and a second surface;
bonding the semiconductor chip to the first heat spreader using the adhesive film; and
covering the sidewalls of the first heat spreader and the sidewalls of the semiconductor chip with a molding layer,
wherein the step of providing a first heat sink comprises: contacting at least a portion of a second surface of the first heat spreader with the semiconductor chip, wherein the second surface of the first heat spreader has a surface roughness greater than a surface roughness of the first surface of the first heat spreader,
wherein the side walls of the first heat spreader are aligned with the side walls of the semiconductor chip, the second surface of the first heat spreader includes an uneven surface and the uneven surface of the first heat spreader is bonded to the semiconductor chip by an adhesive film,
wherein a first portion of the second surface of the heat sink is an uneven surface and a second portion of the second surface of the heat sink is a flat surface,
wherein a second portion of the second surface of the heat spreader is in direct contact with the semiconductor chip and a portion of the first portion of the second surface of the heat spreader is in direct contact with the semiconductor chip.
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