TWI523174B - 覆晶、面上及面下之打線接合結合封裝件 - Google Patents

覆晶、面上及面下之打線接合結合封裝件 Download PDF

Info

Publication number
TWI523174B
TWI523174B TW101112514A TW101112514A TWI523174B TW I523174 B TWI523174 B TW I523174B TW 101112514 A TW101112514 A TW 101112514A TW 101112514 A TW101112514 A TW 101112514A TW I523174 B TWI523174 B TW I523174B
Authority
TW
Taiwan
Prior art keywords
microelectronic
component
assembly
contacts
substrate
Prior art date
Application number
TW101112514A
Other languages
English (en)
Other versions
TW201248809A (en
Inventor
貝勒卡塞姆 哈巴
理查 狄威特 柯斯伯
華爾 柔伊
Original Assignee
泰斯拉公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 泰斯拉公司 filed Critical 泰斯拉公司
Publication of TW201248809A publication Critical patent/TW201248809A/zh
Application granted granted Critical
Publication of TWI523174B publication Critical patent/TWI523174B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

覆晶、面上及面下之打線接合結合封裝件
本發明係關於堆疊式微電子總成及製造此等總成之方法，且係關於在此等總成中有用的組件。
本發明主張2011年4月21日申請之美國臨時專利申請案第61/477,883號之申請日期的權利，其揭示在此以引用之方式併入本文中。以下共同擁有之申請案以引用之方式併入本文中：美國臨時專利申請案第61/477,820號、第61/477,877號、及第61/477,967號，均於2011年4月21日申請。
半導體晶片通常提供為個別、預封裝單元。標準晶片具有平坦、矩形本體，其具有擁有連接至該晶片之內部電路之接觸件的較大前面。每一個別晶片通常安裝於一封裝中，其繼而安裝於一電路面板上，諸如印刷電路板，且其將該晶片之接觸件連接至該電路面板之導體。在許多習知設計中，該晶片封裝佔據電路面板之一面積，其比該晶片本身之面積大很多。如在本揭示中參考具有前面的平坦晶片而使用，「晶片之面積」應理解為指該前面之面積。在「覆晶」設計中，該晶片之前面面對一封裝基板(即，晶片載體)之面，且該晶片上的接觸件藉由焊接球或其他連接元件而直接接合至該晶片載體之接觸件。繼而，該晶片載體可經該晶片之前面上的終端而接合至一電路面板。該「覆晶」設計提供相對緊密之配置，每一晶片佔據該電路 面板之一面積，其等於或略大於該晶片之前面的面積，諸如在共同讓渡之美國專利第5,148,265號、第5,148,266號及第5,679,977號之某些實施例中所揭示，其等之全部揭示以引用之方式併入本文中。
某些創新安裝技術提供接近或等於習知覆晶接合的緊密性。可在等於或略大於該晶片本身之面積之電路面板之一面積中容納一單一晶片的封裝通常稱為「晶片大小的封裝」。
除將由微電子總成佔據之電路面板之平面面積最小化之外，亦期望生產一晶片封裝，其展現垂直於該電路面板之平面的較低整體高度或尺寸。此等較薄微電子封裝允許其內安裝有封裝的一電路面板緊密接近於鄰近結構而佈置，因此產生併入該電路面板之產品的整體大小。已推動多種建議以在一單一封裝或模組中提供複數個晶片。在習知「多晶片模組」中，該等晶片並排安裝於一單一封裝基板上，其繼而可安裝至該電路面板。此途徑僅提供由晶片佔據之該電路面板之總面積上的有限減小。該總面積仍然大於該模組中個別晶片之總表面積。
亦已提出以「堆疊」配置封裝複數個晶片，即，其中複數個晶片一者置於另一者頂部上之配置。在一堆疊式配置中，若干晶片可安裝於小於該等晶片之總面積的電路面板之一面積中。某些堆疊式晶片配置例如揭示於前文提及之美國專利第5,679,977號、第5,148,265號及美國專利第5,347,159號之某些實施例中，其等之全部揭示以引用之方 式併入本文中。亦以引用之方式併入本文中的美國專利第4,941,033號揭示晶片堆疊於另一者頂部上，且由與該等晶片相關之所謂「配線膜」上的導體而彼此互連之配置。
儘管本技術中的這些努力成果，但是在大體上於晶片之中央區域中設置接觸件的晶片的多重晶片封裝之情況中期望進一步改良。某些半導體晶片，諸如一些記憶體晶片，通常製造為在一列或兩列中的接觸件大體上沿著晶片之一中央軸設置。
根據本發明之一態樣，一微電子總成可包含一基板，其具有對置面對的第一及第二表面，及在該等第一與第二表面之間延伸的至少一孔隙，該基板具有在該第一表面處的基板接觸件及在該第二表面處的終端。該微電子總成亦可包含具有面對該第一表面的一前表面的一第一微電子元件，具有面對該第一微電子元件之一前表面的一第二微電子元件，及將該第二微電子元件之接觸件與該等終端電連接的引線。該第一微電子元件可具有遠離該前表面的一後表面，及在該等前表面與後表面之間延伸的一邊緣。該第一微電子元件可具有在該前表面處的複數個接觸件，該複數個接觸件面對且連結至基板接觸件之對應者。該第二微電子元件可具有超過該第一微電子元件之邊緣而暴露於其前表面的複數個接觸件。該第二微電子元件可體現更大量主動裝置，以提供除任何其他功能之外的記憶體儲存陣列功能。引線可具有與至少一孔隙對準的部分。該第一微電 子元件可經組態以重新產生由微電子總成在終端處接收的至少一些信號，且將該等信號傳輸至該第二微電子元件。
在一例示性實施例中，該第一微電子元件可經組態以控制該微電子總成外部之一組件與該第二微電子元件之間的資料傳輸。在一實施例中，該第一微電子元件可經組態以在該外部組件與該第二微電子元件之間緩衝信號。在一特定實施例中，該第一微電子元件可經組態以主要執行一邏輯功能。
在一實施例中，該總成亦可包含至少部分在該第二微電子元件上的一第三微電子元件。該第三微電子元件可具有超過該第二微電子元件之一邊緣而暴露於其前表面且電連接至至少一些基板接觸件的複數個接觸件。該總成亦可包含第二引線，其等將該第三微電子元件之接觸件與終端電連接，該等第二引線具有與至少一孔隙對準的部分。在一實施例中，該等第二及第三微電子元件可各包含非揮發性快閃記憶體。在一特定實施例中，該第一微電子元件可具有除提供一記憶體儲存陣列之外的主要功能。在一特定實施例中，該第二微電子元件之接觸件可設置鄰近該第二微電子元件之邊緣，且該第三微電子元件之接觸件可設置鄰近該第三微電子元件之一邊緣。
在一特定實施例中，該第二微電子元件之接觸件可安置於其前表面之一中央區域內。該中央區域可從該第二微電子元件之第一及第二對置的邊緣間隔開。在一實施例中，該基板可包含具有定義第一及第二基板表面的第一及第二 表面的一介電元件。沿著該介電元件之第一或第二表面之至少一者且超過該至少一孔隙之一邊緣而延伸的引線可接合至該第二微電子元件之接觸件。在一例示性實施例中，該基板可具有小於每℃百萬分之7的熱膨脹係數。在一特定實施例中，該等引線可包含經該至少一孔隙延伸至該基板之第二表面處的接合接觸件的打線接合。
在一實施例中，該總成亦可包含從該基板或該第一微電子元件之至少一者延伸的大體上剛硬的導電柱。在一實施例中，該總成亦可包含在該第二微電子元件之前表面與該基板之第一表面之間的一間隔元件。在一例示性實施例中，該總成亦可包含具有一前表面及遠離該前表面之一後表面的一第三微電子元件，該後表面面對該第一微電子元件之後表面。該第三微電子元件可具有暴露於其前表面的複數個接觸件，及將該第三微電子元件之接觸件與至少一些基板接觸件電連接的複數個引線。
在一例示性實施例中，可將該第三微電子元件之接觸件連接至至少一些基板接觸件的該等引線包含打線接合。在一特定實施例中，將該第三微電子元件之接觸件連接至至少一些基板接觸件的引線可包含超過該第三微電子元件之邊緣而延伸之引線接合。該第三微電子元件之邊緣可在該第三微電子元件之前表面與後表面之間延伸。在一實施例中，該總成亦可包含具有面對該介電元件之一前表面及遠離該前表面之一後表面的一第四微電子元件。該第四微電子元件可具有暴露於其前表面且電連接至至少一些第一導 電元件的複數個接觸件。該第二微電子元件可至少部分在該第四微電子元件上。
在一特定實施例中，該總成亦可包含具有面對該基板之一前表面及遠離該前表面之一後表面的一第三微電子元件。該第三微電子元件可具有暴露於其前表面及電連接至至少一些基板接觸件的複數個接觸件。該第二微電子元件可至少部分在該第三微電子元件上。在一例示性實施例中，該第三微電子元件可包含經組態以主要執行一邏輯功能的一晶片。
根據本發明之另一態樣，一微電子總成可包含一基板，其具有對置面對的第一及第二表面及在該等第一與第二表面之間延伸的一第一孔隙，該基板進一步具有在其上之複數個導電元件。該總成亦可包含具有面對該基板之第一表面之一表面的一第一微電子元件；具有面對該第一微電子元件的一前表面的一第二微電子元件；連接至該第二微電子元件且經該第一孔隙延伸至該基板上之至少一些導電元件的信號引線；及至少一功率調節組件，其具有安置於該基板之第一表面與該第二微電子元件之前表面之間之主動電路元件。該第一微電子元件可具有遠離該前表面的另一表面，及在其表面之間延伸的一邊緣。該第二微電子元件可具有暴露於其前表面的複數個接觸件。該第二微電子元件可超過該第一微電子元件之邊緣而突出。
在一實例中，該基板可包含在該等第一與第二表面之間延伸的一第二孔隙。該微電子總成可進一步包含將該第一 微電子元件與基板上之導電元件電連接的額外信號引線。該等額外信號引線可具有與該第二孔隙對準的部分。在一特定實施例中，該至少一功率調節組件可包含一接通/斷開開關。本發明之進一步態樣可提供併入與電連接至其之其他電子組件協力之根據本發明之前述態樣之微電子總成的系統。例如，系統可安置於一單一外殼中及/或安裝至一單一外殼，其可為一可攜式外殼。根據本發明之此態樣中之較佳實施例的系統可比可比較的習知系統更小型。
本發明之多種實施例現將參考附圖而描述。應瞭解，此等圖式僅描繪本發明之一些實施例，且因此不應視作限制其範圍。
參考圖1及圖2，根據本發明之一實施例之一堆疊式微電子總成10包含在一面下或覆晶位置的一第一微電子元件12及在一面下位置的一第二微電子元件14。在一些實施例中，該第一微電子元件12及該第二微電子元件14可為一半導體晶片，或包含一半導體晶片的一元件，其具有在其前表面16處的接觸件。該半導體晶片可為半導體材料(諸如矽或砷化鎵)之薄片，且可提供為個別、預封裝單元。該半導體晶片可體現主動電路元件(例如電晶體、二極體以及其他)、或被動電路元件(諸如電阻器、電容器或電感器以及其他)、或主動及被動電路元件之組合。在「主動」半導體晶片中，每一微電子元件中之主動電路元件通常在一個或多個「積體電路」中電連接至一起。該等第一及第 二微電子元件兩者可電連接至一基板30，如下文中詳細討論。繼而，在一實施例中，該基板30可電連接至一電路面板，諸如一印刷電路板。在一特定實施例中，該微電子總成10可為一微電子「封裝」，其具有經組態以與電路面板(諸如印刷電路板以及其他)之一面上的對應接觸件電連接的終端。
在特定實施例中，該基板可為多種類型之諸如聚合材料或無機材料(諸如陶瓷或玻璃)之構造的介電元件，該基板上具有諸如終端之導電元件，及諸如跡線、基板接觸件之導電元件或與終端電連接的其他導電元件。在另一實例中，該基板可基本上由一半導體材料組成，諸如矽，或者包含一層半導體材料及其一個或多個介電層。此基板可具有小於每℃百萬分之7(七)(ppm/℃)的熱膨脹係數。在又另一實施例中，該基板可為具有引線指狀物的引線框，其中該等終端可為引線指狀物之部分，諸如引線指狀物之末端部分。
該第一微電子元件12可包含經組態以主要執行一邏輯功能的一半導體晶片，諸如一微處理器、特殊應用積體電路(ASIC)、場可程式化閘陣列(FPGA)或其他邏輯晶片以及其他。在其他實例中，該第一微電子元件12可包含或為一記憶體晶片，諸如快閃(NOR或NAND)記憶體晶片、動態隨機存取記憶體(DRAM)晶片或靜態隨機存取記憶體(SRAM)晶片，或經組態以主要執行一些其他功能。在一實例中，該第一微電子元件12可體現更大量主動裝置，以提供除任 何其他功能之外的記憶體儲存陣列功能。該第一微電子元件12具有一前表面16、遠離該前表面之一後表面18及在該等前表面與後表面之間延伸的第一邊緣27及第二邊緣29。
在一特定實施例中，該第一微電子元件12可具有除提供一記憶體儲存陣列之外的主要功能。在一實例中，該第一微電子元件12可經組態以控制在該微電子總成之外部之一組件與該第二微電子元件之間之資料傳輸。在一例示性實施例中，該第一微電子元件12可經組態以在一外部組件與該堆疊式微電子總成10中之其他微電子元件之間緩衝信號，其他微電子元件諸如第二微電子元件14或複數個第二微電子元件(例如，圖7中展示之第二微電子元件714)。在一實例中，該第一微電子元件12可經組態以重新產生由該微電子總成10在終端36接收的至少一些信號，且將該等信號傳輸至該第二微電子元件14。此一第一微電子元件12可經組態以幫助提供該第二微電子元件14關於該微電子總成10之外部的組件的阻抗隔離。
在另一實例中，該微電子總成10可經組態以運作為一固態記憶體磁碟。在此一實例中，該第一微電子元件12可包含經組態以主要執行一邏輯功能的一半導體晶片，諸如一固態磁碟控制器，且該第二微電子元件14可包含記憶體儲存元件，諸如非揮發性快閃記憶體。該第一微電子元件12可包含一特殊用途的處理器，其經組態以支援一系統(諸如系統1100，圖8)之一中央處理單元將資料傳輸至記憶體儲存元件及從記憶體儲存元件傳輸資料的管理，該等記憶 體儲存元件包含於該第二微電子元件14中。包含一固態磁碟控制器之此一第一微電子元件12可提供至一系統(諸如系統1100)之母板(例如，圖8中展示之電路面板1102)上之一資料匯流排的直接記憶體存取，及從該資料匯流排的直接記憶體存取。
電接觸件20暴露於該第一微電子元件12之前表面16處。如本揭示中所使用，一導電元件「暴露於」一結構之一表面處的陳述指示該導電元件可用於與從該結構外部在垂直於該表面的一方向上朝該表面移動的一理論點接觸。因此，暴露於一結構之一表面處的一終端或其他導電元件可從此表面突出、可與此表面齊平、或可相對於此表面而凹進、及經該結構中之孔或凹陷而暴露。電接觸件20可包含接合墊片或其他導電結構，諸如凸塊、柱等等。該等接合墊片可包含一個或多個金屬，諸如銅、鎳、金或鋁，且可為約0.5 μm厚。該等接合墊片之大小可隨裝置類型變化，但通常將在一側上量測為幾十至幾百微米。
該第二微電子元件14具有一前表面22、遠離該前表面之一後表面24、在該等前表面與後表面之間延伸的第一邊緣35及第二邊緣37及暴露於該前表面22的接觸件26。如圖1中所見，該第一微電子元件12及該第二微電子元件14相對於彼此而堆疊，使得該第二微電子元件14之至少一部分在該第一微電子元件12之至少一部分上，且該第二微電子元件14之接觸件26超過該第一微電子元件12之第二邊緣29而安置。
在一特定實施例中，諸如圖1中所展示，該第二微電子元件14之前表面22包含第一末端區域21及第二末端區域23，及在該第一末端區域21與該第二末端區域23之間延伸的一中央區域19。該第一末端區域21在該中央區域19與第一邊緣35之間延伸，且該第二末端區域23在該中央區域19與該第二邊緣37之間延伸。該中央區域可延伸在該第二微電子元件14之第一邊緣35與第二邊緣37之間之距離的三分之一，且該等第一及第二末端區域可各延伸在該等邊緣35、37之間之距離的三分之一。電接觸件26暴露於該第二微電子元件14之前表面22處。例如，接觸件26可鄰近第一表面22之中央而以一個或兩個平行的列配置。該第二微電子元件14可包含或為一DRAM晶片。在一實例中，該第二微電子元件14可體現更大量主動裝置，以提供除任何其他功能之外的記憶體儲存陣列功能。該第二微電子元件14之中央區域19之至少一部分超過該第一微電子元件12之第二邊緣29而突出，使得該第二微電子元件14之接觸件26超過該第一微電子元件12之第二邊緣29而暴露。
如上文所討論，在一實施例中，該基板30可包含具有對置面對的第一表面34及第二表面32的一介電元件。一個或多個導電元件或終端36暴露於該介電元件30之第二表面32處。在一特定實施例中，一些或所有終端36可相對於該第一微電子元件12及/或該第二微電子元件14而可移動。
該基板進一步包含在其第一與第二對置的表面之間(諸如在一介電元件30之對置面對的第一與第二表面之間)延 伸的一個或多個孔隙。在圖1中描繪的實施例中，該基板包含一孔隙39，且至少一些接觸件26與該介電元件之孔隙39對準。複數個引線將該第二微電子元件之接觸件26與該微電子總成之終端36電連接。該等引線具有與該孔隙39對準的部分。例如，該等引線可包含接合至該等基板接觸件的打線接合50，該基板接觸件繼而經該等引線(諸如沿著一半導體元件或介電元件30而延伸的金屬跡線)之其他部分而連接至終端36，或若該基板包含一引線框，則該等引線可包含其引線指狀物之部分。
如圖1中所見，該基板30可超過該第一微電子元件12之第一邊緣27及該第二微電子元件14之第一邊緣35而延伸。在一實例中，包含一介電材料的基板可稱為「介電元件」30，無論是否部分或全部由任何適宜介電材料製成。例如，該介電元件30可包括一層可撓性材料，諸如一層聚醯亞胺、BT樹脂或常用於製造捲帶自動接合(TAB)捲帶的其他介電材料。或者，該介電元件30可包括一相對剛硬的板狀材料，諸如一層較厚的強化纖維環氧樹脂，諸如Fr-4或Fr-5板。無論所利用的材料為何，該介電元件30可包含單層或多層介電材料。
該介電元件30之第一表面34可與第一微電子元件12之前表面16並置。如圖1及圖2中所見，該介電元件30亦可包含暴露於該第二表面32上的導電元件40及導電跡線25。該等導電跡線25將該等導電元件40電耦接至終端36。該等跡線及導電元件40可使用共同讓渡之美國專利公開案第 2005/0181544號中繪示之方法而建立，其之全部揭示以引用之方式併入本文中。該介電元件30可進一步包含暴露於該第一表面34上的導電元件48。
回到圖1，一間隔或支撐元件31可定位於該第二微電子元件14之第一末端區域21與該介電元件30之一部分之間。該間隔元件31可幫助將該第二微電子元件支撐於該基板30上方。此一間隔元件31可例如由一介電材料(諸如二氧化矽或其他材料)、一半導體材料(諸如矽)、或一層或多層黏合劑或其他聚合材料製成。在一特定實施例中，該間隔元件可包含金屬或由金屬製成。若該間隔元件包含黏合劑，則黏合劑可將該第二微電子元件14連接至基板30。在一實施例中，該間隔元件31可在大體上垂直於該基板之第一表面34的一垂直方向上具有與第一微電子元件12在其前表面與後表面16、18之間的厚度大體上相同的厚度。如圖1中所展示，若間隔元件31包含一黏合劑，則黏合劑可將該第二微電子元件14連接至介電元件30。如圖1中所展示，該第二微電子元件14之第二末端區域23可用一接合材料60(諸如黏合劑60，其可為導熱的)接合至該第一微電子元件12之第二末端區域17。同樣地，一黏合劑(視需要為導熱的)可將該第二微電子元件之第一末端區域與該間隔元件31接合。類似地，間隔元件61可包含用於將該第二微電子元件14與該間隔元件31接合的黏合劑。在一特定實施例中，該等接合材料60、61或兩者可部分或完全由一晶粒附接黏合劑製成，且在一特定實例中可包括一低彈性模數材 料，諸如聚矽氧彈性體。然而，若該等微電子元件12及14係由相同材料形成之習知半導體晶片，則該等接合材料60、61或兩者可完全或部分由高彈性模數黏合劑或焊料製成，因為該等微電子元件將趨向於回應於溫度變化而一致地膨脹及收縮。無論所利用之材料為何，間隔元件31及60之各者可包含單層或多層。
參考圖1，該微電子總成可包含打線接合50，其將該第二微電子元件14之接觸件26電連接至該基板之終端36。在一實施例中，該等引線可包含接合元件50，諸如經孔隙39而延伸且接合至該微電子元件及基板之接觸件26、40之打線接合。接合元件50與該介電元件30之孔隙39至少部分對準。該等打線接合50可包含將第二微電子元件14之一些接觸件與導電元件40電連接的多個打線接合52、54。打線接合52、54經孔隙39而延伸。該等打線接合52及54之各者將一接觸件26電耦接至該介電元件30之一對應導電元件40。該等打線接合50可包含如描述於2010年10月19日申請且題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」的美國專利申請案第12/907,522號中的多重打線接合結構，其全部揭示以引用之方式併入本文中。如圖1中所見，另外或或者，諸如引線接合49的引線可如所展示般沿著該介電元件30之第一表面34或沿著該第二表面延伸，且進入孔隙39，以電連接至接觸件26。引線接合49並非必定經介電元件30之孔隙39延伸，但至少部分與該孔隙對準。
該微電子總成10可進一步包含遮蓋至少該第一微電子元件12及該第二微電子元件14之一外模製件或囊封件11。如圖1中所見，該外模製件11亦可遮蓋超過該第一微電子元件12之第一邊緣27及該第二微電子元件14之第一邊緣35而延伸的介電材料30之部分。因而，該外模製件11可接觸該第一微電子元件12之至少第一邊緣27、該第二微電子元件14之第一邊緣35、及該介電元件30之第一表面34。該外模製件11可由任何適宜材料製成，包含環氧樹脂及類似物。
該微電子總成10可額外地包含附接至該等第一或第二微電子元件12及14之一者或多者之後表面的一散熱片或散熱器，如描述於2010年10月19日申請且題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」的美國專利申請案第12/907,522號中，其全部揭示在此以引用之方式併入本文中。在一些實施例中，該微電子總成10包含一散熱片，其熱耦接至第一微電子元件12及/或第二微電子元件14，但並不包含一外模製件11。
再者，該微電子總成10可進一步包含附接至該介電元件30之第二表面32上之終端36的連結單元81。該等連結單元81可為焊接球或其他接合及金屬塊，例如，錫、銦或其組合，且經調適以將該微電子總成10連結及電耦接至一電路面板，諸如一印刷電路板。
參考圖2及圖3A，該介電元件30在其第一表面34上亦包含導電元件41(諸如接觸墊片)及導電跡線25。該等導電元 件41可在該介電元件30之內部延伸。因此，如本揭示中所使用，一第一特徵部安置於一第二特徵部「上」的陳述不應理解為要求該第一特徵部位於該第二特徵部之一表面上。
繼續參考圖3A，一覆晶互連43將該第一微電子元件12之前表面16上電接觸件20電連接至該介電元件30之第一表面34上的導電元件41。在一例示性實施例中，在該第一微電子12之前表面16的複數個電接觸件20可面對且可連結至介電元件30之導電元件41之對應者。一覆晶互連係用於將該半導體晶片上的接合墊片導電地連接至基板上之接觸墊片的常用方案。在覆晶互連中，金屬之凸塊通常置於每一接合墊片上。該微電子元件接著翻轉，故金屬凸塊提供在該微電子元件之接觸件(例如，接合墊片)與介電元件之間之電通路以及該微電子元件至該介電元件之機械附接兩者。覆晶程序具有許多變動，但一常見組態係對於金屬凸塊使用焊料，及使用焊料熔解作為將金屬凸塊緊固至接合墊片及基板之方法。當焊料熔化時，其可流動以形成截頂的球體。
與經由打線接合而連接至該介電元件的其他微電子元件對比，該覆晶互連對該第一微電子元件12提供更大量(輸入/輸出)I/O。再者，該覆晶互連將該第二微電子元件14與該介電元件30之間的打線接合通路最小化，藉此減小該等打線接合之阻抗。
在圖3A中描繪之實施例中，該覆晶互連43可包含複數個 固體金屬凸塊45，諸如安置於該第一微電子元件12與該介電元件30之間的焊接球。每一固體金屬凸塊45可安置於該第一微電子元件12之電接觸件20與該介電材料30之導電元件41之間(且與電接觸件20及導電元件41接觸)，藉此在該電接觸件20與導電元件41之間提供電連接。金屬凸塊45可基本上由連結金屬或任何其他適宜材料組成。
底部填膠47可圍繞固體金屬凸塊45，以將該第一微電子元件12黏合至該介電元件30。該底部填膠47可明確安置於該第一微電子元件12之前表面16與該介電元件30之第一表面34之間，以將該第一微電子元件12耦接至該介電元件30。該底部填膠47可使用任何適宜黏合劑。例如，該底部填膠47可完全或部分由一聚合黏合劑製成，諸如環氧樹脂。然而在一些實施例中，該底部填膠47被完全省略。
參考圖4A及圖4B，在根據本發明之一實施例之變動中，該覆晶互連43'可包含複數個大體上剛硬的導電圓柱106，其等將該第一微電子元件12與該介電元件30連接，如2008年9月26日申請之美國專利申請公開案第2009/0146303號中詳細描述，其全部揭示在此以引用之方式併入本文中。該等導電圓柱106包含從該介電元件30之第一表面34朝該第一微電子元件12突出的導電凸塊或柱108。每一柱108大體上與從該第一微電子元件12之前表面朝該介電元件30突出的一導電凸塊或柱110對準。藉由增加微電子元件12與介電元件30之間的間距或垂直距離，而同時允許導電圓柱106之間之中央至中央的水平距離或節 距P減小，導電圓柱106對基板上晶片的封裝提供增加的高度。增加該介電元件30與該微電子元件12之間之距離的能力可幫助減小導電圓柱處的應力，可幫助容易地施加底部填膠47，且允許使用更多種底部填膠。在一特定實施例中，該等圓柱106延伸在該微電子元件12之前表面16與該介電元件30之第一表面34之間的分離距離的至少40%。此40%分離距離可幫助減小導電圓柱106處的應力，可幫助容易地施加底部填膠47，且允許使用更多種底部填膠。
固體金屬凸塊或導電柱108從該介電元件30之第一表面34延伸以形成導電圓柱106的第一部分。該等導電柱108具有頂表面116，及以實質角度離開該介電材料30之頂表面而延伸的邊緣表面113，使得在該等邊緣表面113與該介電元件30之第一表面34相遇之處建立一不同角度。例如，在所展示之實施例中，大於90度的角度建立於該介電元件30之第一表面34與該等導電柱108之邊緣表面113之間。該角度將基於導電柱108之形狀而不同。例如，圓柱形的柱在該介電元件30之第一表面34與該導電柱108之間可具有90度的角度。例示性程序及柱描述於題為Chip Capacitor Embedded PWB的美國專利申請公開案第2010/0071944號；題為Multilayer Substrate with Interconnection Vias and Method of Manufacturing the Same的美國專利申請公開案第2009/0071707號；題為Interconnection Element with Posts Formed by Plating的美國專利申請公開案第2009/0145645號中；其等所有之全部揭示以引用之方式併 入本文中。例如，該等導電柱108可藉由蝕刻程序形成，如在本文中更詳細描述。或者，導電柱108可由電鍍形成，其中柱108藉由將金屬經一介電層(諸如光阻層)中圖案化的開口電鍍於一基部金屬層上而形成。
導電柱108之尺寸可在一相當大的範圍上變化，但從介電元件30之第一表面34延伸的每一導電柱108之高度H1最通常係至少50微米，且可延伸多達300微米。此等導電柱108可具有大於其直徑或寬度W1的高度H1。然而，該高度H1亦可小於寬度W1，諸如寬度W1之尺寸的至少一半。
導電柱108可由任何導電材料製成，諸如銅、銅合金、金及其組合。導電柱108可包含可由焊料濕潤的至少一暴露金屬層。例如，該等柱可包括銅，該等柱之表面具有一層金。再者，該等導電柱108可包含至少一層金屬，其具有大於其所將連結之焊料之熔化溫度的熔化溫度。例如，此等導電柱108將包含一層銅或完全由銅形成。
導電柱108亦可採用許多不同形狀，包含截頭圓錐體。每一導電柱108之基部114及頂表面116可為大體上圓形或具有一不同形狀，例如，橢圓形。導電柱108的基部114通常在直徑上係約50 μm至300 μm，而頂表面116通常在直徑上係約25 μm至200 μm。每一導電柱108可具有鄰近介電基板30的一基部114及遠離該介電元件的一頂表面116。再者，該等導電柱從該介電元件30(排除任何焊料遮罩118)之第一表面34的高度H1通常範圍從小至30 μm至多達200 μm。如圖4B中所展示，一焊料遮罩118可安置於該介電元 件30上且鄰近該等導電柱108。該焊料遮罩118幫助防止在回流階段期間在鄰近圓柱106之間的焊料溢流及架橋。
如上文所討論，該覆晶互連43'亦可包含從該第一微電子元件12之前表面13延伸的導電柱110。例示性導電柱及製造能夠從一微電子元件或類似物延伸之導電柱的方法描述於美國專利第6,681,982號、第6,592,109號及第6,578,754號中，其等讓渡予Advanpak，且其等全部揭示以引用之方式併入本文中。例如，該等導電柱110可由蝕刻程序形成。或者，導電柱110可由電鍍而形成，其中柱110藉由經一光阻層中圖案化之開口將一金屬電鍍於一基部金屬層上而形成。如同從介電元件30延伸的導電柱108，從微電子元件12延伸的柱110可具有頂表面128及以實質角度離開該微電子元件之前表面16而延伸的邊緣表面117，使得在該微電子元件與該等導電柱之間建立一不同角度。
為在該等導電柱110與該微電子元件12之間提供一金屬接觸件，可在該微電子元件12之前表面16上提供一凸塊下金屬化層120。該凸塊下金屬化層120通常由包含鈦、鈦-鎢、鉻的材料組成。該凸塊下金屬化層120操作為該等導電圓柱106的導電金屬接觸件。一鈍化層119亦可使用本技術中已知的方法提供於該微電子元件12與該凸塊下金屬化層120之間的微電子元件12之前表面16上。
從該微電子元件12延伸的導電柱110之尺寸亦可在一相當大的範圍上變化，但每一導電柱110之高度H2最通常不小於50微米。該等導電柱110可具有大於其寬度W2的一高 度H2。然而，該高度亦可小於寬度W2，諸如寬度大小的至少一半。
該等導電柱110可由銅或銅合金製成，但亦可包含其他導電材料，諸如金或金及銅之組合。再者，該等導電柱110可包含具有大於其所將連結之焊料之熔化溫度的熔化溫度的至少一層金屬。例如，此等導電柱將包含一層銅或完全由銅形成。
在一特定實施例中，該等導電柱110可為圓柱形，使得柱之基部126及柱之頂表面128的直徑大體上相同。在一實施例中，導電柱之該等基部126及頂表面128在直徑上可為約30 μm至150 μm。每一導電柱110可具有鄰近該微電子元件12之一基部126，及遠離該微電子元件12的一頂表面128。或者，該等導電柱110可採用多種形狀，諸如截頭圓錐體、矩形或條形。
焊料之塗層或帽(未作圖式)可附接至該等導電柱110之頂表面128、或該等導電柱未附接至該微電子元件12之部分。焊料之帽可具有導電柱110的相同直徑或寬度W2，使得其變為導電柱110之延伸。在一實例中，焊料之帽可具有範圍從約25 μm至80 μm之高度H3。
應瞭解，從該微電子元件12之前表面16延伸之該等導電柱110的高度H2可等於從該介電元件30之第一表面34延伸之導電柱108之高度H1。然而，該等高度可或者不同，使得導電柱110之高度H2可小於或大於導電柱108之高度H1。在一特定例證性實例中，從該微電子元件12延伸之導 電柱110可具有長50 μm的高度H2，而從該微電子元件30延伸之導電柱108可具有55 μm的高度H1。
為將微電子元件12及介電元件30導電連接至一起，該微電子元件12上之導電柱110必須連接至介電元件30上之導電柱108。該微電子元件12經翻轉，使得該微電子元件12之導電柱110及該介電元件30之導電柱108彼此對準且緊密接近。該微電子元件12上之焊料之帽經回流以允許焊料濕潤該微電子元件12上之導電柱110及介電元件30上之導電柱108之表面。該焊料將濕潤導電柱之暴露的表面，且建立從該微電子元件12延伸至該介電元件30之導電圓柱106。微電子元件12及介電元件30上為焊料所連結之導電柱108、110之增加的表面積可幫助減小焊接介面處的電流密度。電流密度上的此減小可幫助減少電子遷移，且提供更大的耐久性。
導電圓柱106包含導電互連該等導電柱的焊料。在從該微電子元件延伸之導電柱之基部與從基板延伸之基部之暴露部分之間延伸的導電圓柱之間距或高度H在一實例中範圍在80 μm至100 μm。
導電圓柱106之壁132可為凸面形狀或桶形，其中導電圓柱之中點區域M1(即，在該微電子元件之導電柱110與該介電元件30之導電柱108之間)具有大於分別鄰近該介電元件30之前表面34及該微電子元件12之前表面16之導電圓柱106之部分的寬度W1、W2的寬度W。
如圖4A中進一步展示，離開該介電元件30延伸的下方柱 108以及下方接觸墊片117可藉由分開的蝕刻步驟形成，諸如國際申請案PCT第WO 2008/076428號中所揭示，其在2008年6月28日公開，且其全部揭示以引用之方式併入本文中。例如，可利用三金屬基板，其具有頂部及底部金屬層123及中間蝕刻停止層或內部金屬層121，以建立導電柱108及導電墊片41。在一個此程序中，三層或更多層金屬結構之一暴露金屬層根據微影技術圖案化光阻層而蝕刻，以形成導電柱108，該蝕刻程序在該結構之一內部金屬層121上停止。該內部金屬層121包含不同於頂部及底部金屬層123之金屬的一個或多個金屬，該內部金屬層為此組合物，使得其不附接用於蝕刻頂部金屬層123之蝕刻劑。例如，從中蝕刻導電柱108的頂部金屬層123基本上由銅組成，該底部金屬層123亦可基本上由銅組成，且該內部金屬層121基本上由鎳組成。鎳提供相對於銅的較好選擇性，以避免與該金屬層附接之鎳層經蝕刻以形成導電柱108。為形成接觸墊片41，可根據另一微影技術圖案化光阻層而進行另一蝕刻步驟。柱108可進一步與其他導電特徵部互連，諸如一導通體115，其繼而進一步互連至其他導電特徵部(未作圖式)。
該微電子總成10可或者包含其他種類之覆晶互連。其他類型的覆晶互連描述於2008年9月26日申請的美國專利申請公開案第2009/0146303號；及申請於2010年7月8日且題為「Microelectronic Packages with Dual or Multiple-etched Flip Connectors」的美國專利申請案第12/832,376號中， 其等所有之全部揭示以引用之方式併入本文中。
圖5描繪圖1中展示之微電子總成10之變動。圖5中展示之微電子總成10'類似於圖1中展示之微電子總成10。在此變動中，代替圖1中描繪之間隔元件31，一第三微電子元件62安置於該第二微電子元件14之第一末端區域21與該介電元件30之一部分之間。該第三微電子元件62超過該第二微電子元件14之第一邊緣35而延伸，且可為具有一邏輯功能的晶片，諸如一微處理器，或一記憶體晶片，諸如一快閃(NOR或NAND)記憶體晶片、DRAM或SRAM陣列。此外，該第三微電子元件62具有一前表面66、遠離該前表面之一後表面68及在該等前表面與後表面之間延伸的第一邊緣67及第二邊緣69。電接觸件63暴露於該第三微電子元件62之前表面66處。上文描述之任何覆晶互連，諸如互連43，將第三微電子元件62之前表面66上的電接觸件63電連接至該介電元件30之第一表面34上之導電元件41。
一接合材料61(諸如上文描述之接合材料，圖1)可安置於該第二微電子元件14與該第三微電子元件62之後表面68之間。
該微電子總成10'可或者或另外包含在面上位置且安置於該第一微電子元件12之頂部上的另一微電子元件72。此微電子元件72可為經組態以主要執行一邏輯功能之一晶片，諸如一微處理器、協同處理器、圖形處理器或信號處理器、特殊應用積體電路晶片(ASIC)或場可程式化閘(FPGA)晶片以及其他實例。或者，此微電子元件72可為一 記憶體晶片，諸如一快閃(NOR或NAND)記憶體陣列、DRAM或SRAM陣列以及許多可行的類型。微電子元件72具有一後表面76、遠離該後表面之一前表面78及在該等前表面與後表面之間延伸的第一邊緣87及第二邊緣79。第四微電子元件72之前表面78可包含第一末端區域75及第二末端區域77及位於該第一末端區域75與該第二末端區域77之間的一中央區域73。該第一末端區域75在該中央區域73與第一邊緣87之間延伸，且該第二末端區域77在該中央區域73與該第二邊緣79之間延伸。電接觸件80(諸如接合墊片)暴露於微電子元件72之前表面78處。該等電接觸件80可安置於前表面78之該第一末端區域75、第二末端區域77及/或中央區域73內。在所展示之實施例中，該等電接觸件80安置於該前表面78之第一末端區域75內。該微電子元件72之第一邊緣87可與該第一微電子元件12之第一邊緣27對準。
第二微電子元件14之前表面可由一黏合劑60而附接至第一微電子元件12之後表面。微電子元件72之後表面亦可由該黏合劑而附接至微電子元件12之後表面。一黏合層定位於該第二微電子元件14之第二末端區域23與該第一微電子元件12之第二末端區域17之間，及該第一微電子元件12之第一末端區域15與該第四微電子元件72之間。因此，該間隔元件60超過該第二微電子元件14之第二邊緣37而延伸，且可在該第四微電子元件72之第一邊緣87處終止。若間隔元件60包含一黏合劑，則黏合劑可將該第一微電子元件12 連接至該第四微電子元件72。
一個或多個電連接或引線90將該第四微電子元件72之前表面78上的接觸件80電連接至該介電元件30之第一表面34上之一些導電元件41。電連接90可包含一個或多個打線接合92，其等將第四微電子元件72之一些接觸件與該介電元件30之第一表面34上的導電元件41電連接。或者或另外，電連接90可包含引線接合。打線接合92可繞該第四微電子元件72之第一邊緣87及該第一微電子元件12之第一邊緣27而延伸。打線接合92之各者將一接觸件80電連接至暴露於該介電元件30之第一表面34處的一對應導電元件48。電連接90可包含多重打線接合結構，如描述於2010年10月19日申請且題為「Enhanced Stacked Microelectronic Assemblies with Central Contacts and Improved Thermal Characteristics」的美國專利申請案第12/907,522號中，其全部揭示以引用之方式併入本文中。
該微電子總成10'或本文中描述之任何其他微電子總成可經由連結單元81連接至一電路面板300(諸如一印刷電路板)，如圖6中展示。
該微電子總成10"可進一步包含安置於該第二微電子元件14之第一末端區域21與介電元件30"之一部分之間的一個或多個功率調節組件及/或微電子機械系統(MEMS)200，其等可額外地用於將微電子元件14之前表面在基板之表面34"上方間隔期望的距離。功率調節組件具有主動電路元件，且可增加微電子總成10"(尤其在諸如行動裝置的功率 敏感應用中)的效能，且可為一個或多個接通/斷開開關，諸如電晶體或適宜於調節源自電源的功率的其他組件。例如，在一些實施例中，功率調節組件200可為能夠控制供應至第一或第二微電子元件12"及14之電力的功率管理積體電路晶片或微控制器。該等功率調節組件200可例如經常允許電力供應至第一微電子元件12"，但當使用高功率應用時僅開啟第二微電子元件14。在此實施例中，當使用低功率應用時，電力可僅供應至該第一微電子元件12"。
圖1中展示之微電子總成10之間隔元件31可由一個或多個功率調節組件及/或MEMS 200取代。類似地，圖5中展示之微電子總成10'之第三微電子元件62可由一個或多個功率調節組件及/或MEMS 200取代。該MEMS 200可包含一個或多個壓力感測器及/或加速度感測器。
圖7繪示圖1之微電子總成10具有一替代組態之變動。圖7中展示之微電子總成710與上文描述之微電子總成10相同，只是該微電子總成710包含在該第一微電子元件712上之第二微電子總成714之一堆疊。
類似於圖1中展示之實施例，該第一微電子元件712可用一覆晶互連743而覆晶接合至該介電元件730，該覆晶互連743將第一微電子元件712之前表面716上的電接觸件720電連接至介電元件之第一表面734上的導電元件741。
在所展示之實例中，一第二微電子元件714a之第一邊緣735可超過第一微電子元件712之第二邊緣729而延伸，使得暴露於該第二微電子元件714a之前表面722的一個或多 個導電接觸件726超過該第一微電子元件之第二邊緣729而安置。同樣地，第二微電子元件714b、714c及714d之各者之第一邊緣735可超過鄰近其前表面而安置之第二微電子元件之第一邊緣而延伸，使得暴露於該等第二微電子元件714b、714c及714d之各者之前表面722處的一個或多個導電接觸件726超過第二微電子元件鄰近其前表面而安置之第一邊緣而安置。
複數個引線可將每一第二微電子元件之接觸件726與該微電子總成710之終端736電連接。該等引線可具有與經該介電元件730而延伸之至少一孔隙739對準之部分。例如，該等引線可包含在每一第二微電子元件714之接觸件726之間延伸至暴露於該介電元件730之第二表面732處的導電接觸件740的打線接合750，其等繼而可經引線(諸如沿著介電元件730而延長之金屬跡線)之其他部分連接至終端736。
儘管圖7中展示之微電子總成710具有經該介電元件730而延伸之至少一孔隙739，但是在一替代實例中，可在沒有孔隙739之下提供一介電元件。在此一實施例中，該介電元件730可包含一單一區域730a，且區域730b可省略。在此實例中，在該等第二微電子元件714之接觸件726與該介電元件730之接觸件740之間延伸的引線部分(例如，打線接合750)可繞該介電元件之一邊緣730c而延伸，若省略區域730b，則邊緣730c可為介電元件之一週邊邊緣。
該微電子總成710可包含附接至暴露於該介電元件730之 第二表面732處的終端736的連結單元781(例如，焊接球)。此等連結單元781可經調適以將微電子總成710連結及電耦接至一外部組件，例如一電路面板，諸如一印刷電路板。
在一例示性實施例中，該微電子總成710可經組態以運作為一固態記憶體磁碟。在此一實例中，該第一微電子元件712可包含經組態以主要執行一邏輯功能之一半導體晶片，諸如一固態磁碟控制器，且該等第二微電子元件714可各包含記憶體儲存元件，諸如非揮發性快閃記憶體。該第一微電子元件712可包含一特殊用途處理器，其經組態以支援一系統(諸如系統1100，圖8)之一中央處理單元將資料傳輸至記憶體儲存元件及從記憶體儲存元件傳輸資料的管理，該等記憶體儲存元件包含於該等第二微電子元件714中。包含一固態磁碟控制器的此一第一微電子元件712可提供往返一系統(諸如系統1100)之母板(例如，圖8中展示之電路面板1102)上之一資料匯流排的直接記憶體存取。
在一特定實施例中，該第一微電子元件712可具有一緩衝功能。此一第一微電子元件712可經組態以幫助提供該第二微電子元件714之各者關於該微電子總成710之外部的組件的阻抗隔離。
上文描述之該等微電子總成可利用於各種電子系統之構造中，如圖8中所展示。例如，根據本發明之一進一步實施例之一系統1100包含如上文描述之與其他電子組件1108及1110協力之微電子總成1106。在所描繪之實例中，該組件1108係一半導體晶片，而組件1110係一顯示螢幕，但可 使用任何其他組件。當然，儘管為清楚繪示起見，在圖8中僅描繪兩個額外組件，但是該系統可包含任何數目之此等組件。該微電子總成1106可為上文描述之任何總成。在一進一步變體中，可使用任何數目之此等微電子總成。該微電子總成1106及該等組件1108及1110安裝於一共同外殼1101中，其示意性地以虛線描繪，且在必要時彼此電互連以形成期望電路。在所展示之例示性系統中，該系統包含一電路面板1102，諸如一可撓性印刷電路板，且該電路面板包含許多導體1104，圖8中描繪其等之僅一者，其使組件彼此互連。然而，此僅為例示性的；可使用進行電連接之任何適宜結構。該外殼1101描繪為可例如使用於一蜂巢式電話或個人數位助理中之類型的可攜式外殼，且螢幕1110暴露於該外殼之表面處。在結構1106包含一光敏感元件(諸如一成像晶片)之處，亦可提供一透鏡1111或其他光學裝置，以將光投送至該結構。再一次強調，圖8中展示之簡化的系統僅為例示性的；可使用上文討論之結構而製造其他系統，包含一般視作固定結構的系統，諸如桌上型電腦、路由器及類似物。
儘管本文中之本發明已參考特定實施例而描述，但是應理解，此等實施例僅例證本發明之原理及應用。因此應理解，可對例證性實施例作出許多修改，且在未脫離由隨附申請專利範圍定義之本發明之精神及範圍之下可設計其他配置。
應瞭解，不同附屬請求項及其中所提特徵可以與初始請 求項中提出的不同方式組合。亦應瞭解，與個別實施例結合描述之特徵可與所描述之實施例之其他特徵共用。
10‧‧‧微電子總成
10'‧‧‧微電子總成
10"‧‧‧微電子總成
11‧‧‧外模製件/囊封件
12‧‧‧第一微電子元件
12"‧‧‧第一微電子元件
13‧‧‧前表面
14‧‧‧第二微電子元件
15‧‧‧第一末端區域
16‧‧‧前表面
17‧‧‧第二末端區域
18‧‧‧後表面
19‧‧‧中央區域
20‧‧‧電接觸件
21‧‧‧第一末端區域
22‧‧‧前表面
23‧‧‧第二末端區域
24‧‧‧後表面
25‧‧‧導電跡線
26‧‧‧接觸件
27‧‧‧第一邊緣
29‧‧‧第二邊緣
30‧‧‧基板/介電元件/介電材料
30"‧‧‧介電元件
31‧‧‧間隔元件
32‧‧‧第二表面
34‧‧‧第一表面
34"‧‧‧基板之表面
35‧‧‧第一邊緣
36‧‧‧終端
37‧‧‧第二邊緣
39‧‧‧孔隙
40‧‧‧導電元件
41‧‧‧導電元件
43‧‧‧覆晶互連
43'‧‧‧覆晶互連
45‧‧‧固體金屬凸塊
47‧‧‧底部填膠
48‧‧‧導電元件
49‧‧‧引線接合
50‧‧‧打線接合/接合元件
52‧‧‧打線接合
54‧‧‧打線接合
60‧‧‧黏合劑
61‧‧‧接合材料
62‧‧‧第三微電子元件
63‧‧‧電接觸件
66‧‧‧前表面
67‧‧‧第一邊緣
68‧‧‧後表面
69‧‧‧第二邊緣
72‧‧‧第四微電子元件
73‧‧‧中央區域
75‧‧‧第一末端區域
76‧‧‧後表面
77‧‧‧第二末端區域
78‧‧‧前表面
79‧‧‧第二邊緣
80‧‧‧接觸件
81‧‧‧連結單元
87‧‧‧第一邊緣
90‧‧‧電連接
92‧‧‧打線接合
106‧‧‧導電圓柱
108‧‧‧導電柱
110‧‧‧導電柱
113‧‧‧邊緣表面
114‧‧‧基部
115‧‧‧導通體
116‧‧‧頂表面
117‧‧‧邊緣表面
118‧‧‧焊料遮罩
119‧‧‧鈍化層
120‧‧‧凸塊下金屬層
121‧‧‧中間蝕刻停止層/內部金屬層
123‧‧‧頂部及底部金屬層
126‧‧‧基部
128‧‧‧頂表面
132‧‧‧壁
200‧‧‧微電子機械系統
300‧‧‧電路面板
710‧‧‧微電子總成
712‧‧‧第一微電子元件
714‧‧‧第二微電子元件
714a‧‧‧第二微電子元件
714b‧‧‧第二微電子元件
714c‧‧‧第二微電子元件
714d‧‧‧第二微電子元件
716‧‧‧前表面
720‧‧‧電接觸件
722‧‧‧前表面
726‧‧‧接觸件
729‧‧‧第一微電子元件的第二邊緣
730‧‧‧介電元件
730a‧‧‧單一區域
730b‧‧‧區域
730c‧‧‧介電元件的邊緣
732‧‧‧介電元件的第二表面
734‧‧‧第一表面
735‧‧‧第二微電子元件的第一邊緣
736‧‧‧終端
739‧‧‧孔隙
740‧‧‧導電接觸件
741‧‧‧導電元件
743‧‧‧覆晶互連
750‧‧‧打線接合
781‧‧‧連結單元
1100‧‧‧系統
1101‧‧‧外殼
1102‧‧‧電路面板
1104‧‧‧導體
1106‧‧‧微電子總成
1108‧‧‧電子組件
1110‧‧‧螢幕/電子組件
1111‧‧‧透鏡
H‧‧‧間距或高度
H1‧‧‧高度
H2‧‧‧高度
H3‧‧‧高度
M1‧‧‧中點區域
P‧‧‧水平距離或節距
W‧‧‧寬度
W1‧‧‧直徑或寬度
W2‧‧‧寬度
圖1係根據本發明之一實施例之一堆疊式微電子總成之一圖解截視立面圖；圖2係圖1中展示之微電子總成之平面圖；圖3A係繪示圖1中展示之堆疊式微電子總成之一部分的截面圖；圖3B係繪示圖3A之一部分的分解截面圖；圖4A係繪示根據圖1中展示之實施例之變動的堆疊式微電子總成之一部分的截面圖；圖4B係繪示圖4A之一部分的一截面圖；圖5係根據本發明之一實施例之一堆疊式微電子總成之一圖解截視立面圖；圖6係根據本發明之另一實施例之一堆疊式微電子總成之一圖解截視立面圖；圖7係根據本發明之另一實施例之一堆疊式微電子總成之一圖解截視立面圖；及圖8係根據本發明之一實施例之一系統的示意性描繪。
10‧‧‧微電子總成
11‧‧‧外模製件/囊封件
12‧‧‧第一微電子元件
13‧‧‧前表面
14‧‧‧第二微電子元件
15‧‧‧第一末端區域
16‧‧‧前表面
17‧‧‧第二末端區域
18‧‧‧後表面
19‧‧‧中央區域
21‧‧‧第一末端區域
22‧‧‧前表面
23‧‧‧第二末端區域
24‧‧‧後表面
26‧‧‧接觸件
27‧‧‧第一邊緣
29‧‧‧第二邊緣
30‧‧‧基板/介電元件/介電材料
31‧‧‧間隔元件
32‧‧‧第二表面
34‧‧‧第一表面
35‧‧‧第一邊緣
36‧‧‧終端
37‧‧‧第二邊緣
39‧‧‧孔隙
40‧‧‧導電元件
43‧‧‧覆晶互連
49‧‧‧引線接合
50‧‧‧打線接合/接合元件
52‧‧‧打線接合
54‧‧‧打線接合
60‧‧‧黏合劑
61‧‧‧接合材料
81‧‧‧連結單元

Claims (27)

  1. 一種微電子總成，其包括：一基板，其具有對置面對的第一及第二表面，及在該等第一與第二表面之間延伸的至少一孔隙，該基板具有在該第一表面的基板接觸件及在該第二表面的終端；一第一微電子元件，其具有面對該第一表面的一前表面，遠離該前表面之一後表面，及在該等前表面與後表面之間延伸的一邊緣，該第一微電子元件具有在該前表面處的複數個接觸件，其等面對且連結至該等基板接觸件之對應者；一第二微電子元件，其具有面對該第一微電子元件之一前表面，該第二微電子元件具有超過該第一微電子元件之該邊緣而暴露於其前表面的複數個接觸件，該第二微電子元件具有記憶體儲存陣列功能；及將該第二微電子元件之該等接觸件與該等終端電連接的引線，該等引線具有與該至少一孔隙對準之部分，其中該第一微電子元件經組態以重新產生由該微電子總成在該等終端處接收之至少一些信號，且將該等信號傳輸至該第二微電子元件。
  2. 如請求項1之微電子總成，其中該第一微電子元件經組態以控制在該微電子總成之外部之一組件與該第二微電子元件之間的資料傳輸。
  3. 如請求項2之微電子總成，其中該第一微電子元件經組態以在該外部組件與該第二微電子元件之間緩衝信號。
  4. 如請求項1之微電子總成，其中該第一微電子元件經組態以主要執行一邏輯功能。
  5. 如請求項1之微電子總成，其進一步包括：一第三微電子元件，其至少部分在該第二微電子元件上，該第三微電子元件具有超過該第二微電子元件之一邊緣而暴露於其前表面且電連接至至少一些該等基板接觸件的複數個接觸件；及第二引線，其等將該第三微電子元件之該等接觸件與該等終端電連接，該等第二引線具有與該至少一孔隙對準之部分。
  6. 如請求項5之微電子總成，其中該等第二及第三微電子元件各包含非揮發性快閃記憶體。
  7. 如請求項5之微電子總成，其中該第一微電子元件經組態以主要執行一邏輯功能。
  8. 如請求項5之微電子總成，其中該第二微電子元件之該等接觸件設置鄰近該第二微電子元件之該邊緣，且該第三微電子元件之該等接觸件設置鄰近該第三微電子元件之一邊緣。
  9. 如請求項1之微電子總成，其中該第二微電子元件之該等接觸件安置於其前表面之一中央區域內，該中央區域從該第二微電子元件之第一及第二對置的邊緣間隔開。
  10. 如請求項1之微電子總成，其中該基板包含一介電元件，其具有定義該等第一及第二基板表面的第一及第二表面，且其中沿著該介電元件之該等第一或第二表面之 至少一者且超過該至少一孔隙之一邊緣而延伸的該等引線接合至該第二微電子元件之該等接觸件。
  11. 如請求項1之微電子總成，其中該基板具有小於每℃百萬分之7之一熱膨脹係數。
  12. 如請求項1之微電子總成，其中該等引線包含經該至少一孔隙而延伸至該基板之該第二表面處的接合接觸件的打線接合。
  13. 如請求項1之微電子總成，其進一步包括從該基板或該第一微電子元件之至少一者延伸的大體上剛硬的導電柱。
  14. 如請求項1之微電子總成，其進一步包括在該第二微電子元件之該前表面與該基板之該第一表面之間的一間隔元件。
  15. 如請求項1之微電子總成，其進一步包括一第三微電子元件，其具有一前表面及遠離該前表面之一後表面，該後表面面對該第一微電子元件之該後表面，該第三微電子元件具有暴露於其前表面的複數個接觸件，及將該第三微電子元件之該等接觸件與至少一些該等基板接觸件電連接之複數個引線。
  16. 如請求項15之微電子總成，其中將該第三微電子元件之該等接觸件連接至至少一些該等基板接觸件的該等引線包含打線接合。
  17. 如請求項15之微電子總成，其中將該第三微電子元件之該等接觸件連接至至少一些該等基板接觸件的引線包含 超過該第三微電子元件之一邊緣而延伸的引線接合，該第三微電子元件之該邊緣在該第三微電子元件之該等前表面與後表面之間延伸。
  18. 如請求項15之微電子總成，其進一步包括一第四微電子元件，其具有面對該介電元件之一前表面，及遠離該前表面之一後表面，該第四微電子元件具有暴露於其前表面且電連接至至少一些第一導電元件的複數個接觸件，該第二微電子元件至少部分在該第四微電子元件上。
  19. 如請求項1之微電子總成，其進一步包括一第三微電子元件，其具有面對該基板的一前表面及遠離該前表面之一後表面，該第三微電子元件具有暴露於其前表面且電連接至至少一些該等基板接觸件的複數個接觸件，該第二微電子元件至少部分在該第三微電子元件上。
  20. 如請求項19之微電子總成，其中該第三微電子元件包含一晶片，其經組態以主要執行一邏輯功能。
  21. 一種微電子系統，其包括一如請求項1之總成，及電連接至該總成之一個或多個其他電子組件。
  22. 如請求項21之系統，其進一步包括一外殼，該總成及該等其他電子組件安裝至該外殼。
  23. 一種微電子總成，其包括：一基板，其具有對置面對的第一及第二表面，及在該等第一及第二表面之間延伸的一第一孔隙，該基板進一步具有在其上的複數個導電元件；一第一微電子元件，其具有面對該基板之該第一表面 的一表面，遠離該表面之另一表面，及在其表面之間延伸的一邊緣；一第二微電子元件，其具有面對該第一微電子元件之一前表面，該第二微電子元件具有暴露於其前表面的複數個接觸件，該第二微電子元件超過該第一微電子元件之該邊緣而突出；信號引線，其等連接至該第二微電子元件，且經該第一孔隙延伸至該基板上的至少一些該等導電元件；及至少一功率調節組件，其具有在其內安置於該基板之該第一表面與該第二微電子元件之該前表面之間的主動電路元件。
  24. 如請求項23之微電子總成，其中該基板包含在該等第一與第二表面之間延伸的一第二孔隙，且該微電子總成進一步包含將該第一微電子元件與該基板上之該等導電元件電連接的額外信號引線，該等額外信號引線具有與該第二孔隙對準之部分。
  25. 如請求項23之微電子總成，其中該至少一功率調節組件包含一接通/斷開開關。
  26. 一種微電子系統，其包括一如請求項23之總成，及電連接至該總成之一個或多個其他電子組件。
  27. 如請求項26之系統，其進一步包括一外殼，該總成及該等其他電子組件安裝至該外殼。
TW101112514A 2011-04-21 2012-04-09 覆晶、面上及面下之打線接合結合封裝件 TWI523174B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161477883P 2011-04-21 2011-04-21
US13/306,182 US8304881B1 (en) 2011-04-21 2011-11-29 Flip-chip, face-up and face-down wirebond combination package

Publications (2)

Publication Number Publication Date
TW201248809A TW201248809A (en) 2012-12-01
TWI523174B true TWI523174B (zh) 2016-02-21

Family

ID=47020673

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101112514A TWI523174B (zh) 2011-04-21 2012-04-09 覆晶、面上及面下之打線接合結合封裝件

Country Status (7)

Country Link
US (3) US8304881B1 (zh)
EP (1) EP2700097A1 (zh)
JP (1) JP2014514766A (zh)
KR (1) KR20140028015A (zh)
CN (1) CN103620774B (zh)
TW (1) TWI523174B (zh)
WO (1) WO2012145114A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763200B (zh) * 2020-06-29 2022-05-01 日商鎧俠股份有限公司 記憶體系統

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5667381B2 (ja) * 2010-06-01 2015-02-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
US8836101B2 (en) * 2010-09-24 2014-09-16 Infineon Technologies Ag Multi-chip semiconductor packages and assembly thereof
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8304881B1 (en) * 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8569884B2 (en) * 2011-08-15 2013-10-29 Tessera, Inc. Multiple die in a face down package
US8629545B2 (en) 2011-10-03 2014-01-14 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
EP2764543A2 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
TWI501254B (zh) 2011-10-03 2015-09-21 Invensas Corp 用於具有正交窗之多晶粒導線結合總成之短線最小化
US8436477B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
TWI515864B (zh) * 2011-10-03 2016-01-01 英帆薩斯公司 具有自封裝中心偏移之端子格柵之短線最小化
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
TWI508238B (zh) 2012-12-17 2015-11-11 Princo Corp 晶片散熱系統
US8907500B2 (en) 2013-02-04 2014-12-09 Invensas Corporation Multi-die wirebond packages with elongated windows
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
WO2016073414A1 (en) * 2014-11-06 2016-05-12 Robert Bosch Gmbh Lead frame-based chip carrier used in the fabrication oe mems transducer packages
US9799628B2 (en) 2015-03-31 2017-10-24 Qualcomm Incorporated Stacked package configurations and methods of making the same
WO2017019025A1 (en) 2015-07-27 2017-02-02 Hewlett Packard Enterprise Development Lp Socket to support boards in a spaced relation
WO2017023257A1 (en) * 2015-07-31 2017-02-09 Hewlett Packard Enterprise Development Lp Multi-chip module
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US10121766B2 (en) 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
US10068879B2 (en) * 2016-09-19 2018-09-04 General Electric Company Three-dimensional stacked integrated circuit devices and methods of assembling the same
US9953904B1 (en) 2016-10-25 2018-04-24 Nxp Usa, Inc. Electronic component package with heatsink and multiple electronic components
KR102592640B1 (ko) 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN110720125B (zh) 2017-06-02 2021-02-05 超极存储器股份有限公司 半导体模块
TWI642158B (zh) * 2017-07-21 2018-11-21 致伸科技股份有限公司 指紋感測晶片封裝結構
TWI710075B (zh) * 2019-08-14 2020-11-11 力成科技股份有限公司 半導體封裝結構及其製造方法
US11527480B2 (en) * 2020-04-30 2022-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Family Cites Families (170)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62107391A (ja) 1985-11-06 1987-05-18 Nippon Texas Instr Kk 情報記憶媒体
JPH02174255A (ja) 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5369552A (en) 1992-07-14 1994-11-29 Ncr Corporation Multi-chip module with multiple compartments
US5998864A (en) 1995-05-26 1999-12-07 Formfactor, Inc. Stacking semiconductor devices, particularly memory chips
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5892660A (en) 1996-08-29 1999-04-06 Micron Technology, Inc. Single in line memory module adapter
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6742098B1 (en) 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US6021048A (en) 1998-02-17 2000-02-01 Smith; Gary W. High speed memory module
US6150724A (en) 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device
US6353539B1 (en) 1998-07-21 2002-03-05 Intel Corporation Method and apparatus for matched length routing of back-to-back package placement
US6121576A (en) 1998-09-02 2000-09-19 Micron Technology, Inc. Method and process of contact to a heat softened solder ball array
US6201695B1 (en) 1998-10-26 2001-03-13 Micron Technology, Inc. Heat sink for chip stacking applications
US6815251B1 (en) 1999-02-01 2004-11-09 Micron Technology, Inc. High density modularity for IC's
SE519108C2 (sv) 1999-05-06 2003-01-14 Sandvik Ab Belagt skärverktyg för bearbetning av grått gjutjärn
TW409377B (en) 1999-05-21 2000-10-21 Siliconware Precision Industries Co Ltd Small scale ball grid array package
KR100393095B1 (ko) 1999-06-12 2003-07-31 앰코 테크놀로지 코리아 주식회사 반도체패키지와 그 제조방법
JP3360655B2 (ja) 1999-07-08 2002-12-24 日本電気株式会社 半導体装置
US6199743B1 (en) * 1999-08-19 2001-03-13 Micron Technology, Inc. Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6414396B1 (en) 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP3768761B2 (ja) 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
JP2001223324A (ja) 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6731009B1 (en) 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592109B2 (en) 2000-07-31 2003-07-15 Toyo Tire & Rubber Co., Ltd. Liquid sealing type body mount
JP2002076252A (ja) 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
JP3462166B2 (ja) 2000-09-08 2003-11-05 富士通カンタムデバイス株式会社 化合物半導体装置
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
SG95637A1 (en) 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
SG106054A1 (en) 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
JP2002353398A (ja) 2001-05-25 2002-12-06 Nec Kyushu Ltd 半導体装置
US6472741B1 (en) 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
US6385049B1 (en) 2001-07-05 2002-05-07 Walsin Advanced Electronics Ltd Multi-board BGA package
JP2003101207A (ja) 2001-09-27 2003-04-04 Nec Kyushu Ltd 半田ボールおよびそれを用いた部品接続構造
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
SG118103A1 (en) 2001-12-12 2006-01-27 Micron Technology Inc BOC BGA package for die with I-shaped bond pad layout
KR100480909B1 (ko) 2001-12-29 2005-04-07 주식회사 하이닉스반도체 적층 칩 패키지의 제조 방법
TW523890B (en) 2002-02-07 2003-03-11 Macronix Int Co Ltd Stacked semiconductor packaging device
US7196415B2 (en) 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
DE10215654A1 (de) 2002-04-09 2003-11-06 Infineon Technologies Ag Elektronisches Bauteil mit mindestens einem Halbleiterchip und Flip-Chip-Kontakten sowie Verfahren zu seiner Herstellung
AU2003234812A1 (en) 2002-06-05 2003-12-22 Hitachi Ulsi Systems Co., Ltd. Semiconductor device
JP2004063767A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
US6762942B1 (en) 2002-09-05 2004-07-13 Gary W. Smith Break away, high speed, folded, jumperless electronic assembly
TW557556B (en) 2002-09-10 2003-10-11 Siliconware Precision Industries Co Ltd Window-type multi-chip semiconductor package
WO2004038798A2 (en) 2002-10-22 2004-05-06 Unitive International Limited Stacked electronic structures including offset substrates
US7268425B2 (en) 2003-03-05 2007-09-11 Intel Corporation Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
TW200419752A (en) 2003-03-18 2004-10-01 United Test Ct Inc Semiconductor package with heat sink
US7528421B2 (en) 2003-05-05 2009-05-05 Lamina Lighting, Inc. Surface mountable light emitting diode assemblies packaged for high temperature operation
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
SG148877A1 (en) 2003-07-22 2009-01-29 Micron Technology Inc Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7061121B2 (en) 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
US7095104B2 (en) 2003-11-21 2006-08-22 International Business Machines Corporation Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
JP2005251957A (ja) 2004-03-04 2005-09-15 Renesas Technology Corp 半導体装置
US7489517B2 (en) 2004-04-05 2009-02-10 Thomas Joel Massingill Die down semiconductor package
US7078808B2 (en) 2004-05-20 2006-07-18 Texas Instruments Incorporated Double density method for wirebond interconnect
WO2005114728A1 (ja) 2004-05-21 2005-12-01 Nec Corporation 半導体装置並びに配線基板及びその製造方法
KR20050119414A (ko) 2004-06-16 2005-12-21 삼성전자주식회사 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법
KR20060004298A (ko) 2004-07-09 2006-01-12 삼성테크윈 주식회사 무선 전자 라벨
US7381593B2 (en) 2004-08-05 2008-06-03 St Assembly Test Services Ltd. Method and apparatus for stacked die packaging
JP4445351B2 (ja) 2004-08-31 2010-04-07 株式会社東芝 半導体モジュール
JP4601365B2 (ja) * 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
US20060097400A1 (en) 2004-11-03 2006-05-11 Texas Instruments Incorporated Substrate via pad structure providing reliable connectivity in array package devices
US7786567B2 (en) 2004-11-10 2010-08-31 Chung-Cheng Wang Substrate for electrical device and methods for making the same
US7217994B2 (en) 2004-12-01 2007-05-15 Kyocera Wireless Corp. Stack package for high density integrated circuits
TWI256092B (en) 2004-12-02 2006-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
JP2006172122A (ja) 2004-12-15 2006-06-29 Toshiba Corp カード状記憶装置
WO2006068643A1 (en) 2004-12-20 2006-06-29 Semiconductor Components Industries, L.L.C. Semiconductor package structure having enhanced thermal dissipation characteristics
JP4086068B2 (ja) 2004-12-27 2008-05-14 日本電気株式会社 半導体装置
KR20060080424A (ko) 2005-01-05 2006-07-10 삼성전자주식회사 멀티 칩 패키지를 장착하는 메모리 카드
US7205656B2 (en) * 2005-02-22 2007-04-17 Micron Technology, Inc. Stacked device package for peripheral and center device pad layout device
US7196427B2 (en) 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
US7250675B2 (en) 2005-05-05 2007-07-31 International Business Machines Corporation Method and apparatus for forming stacked die and substrate structures for increased packing density
KR101070913B1 (ko) 2005-05-19 2011-10-06 삼성테크윈 주식회사 반도체 칩 적층 패키지
US7402911B2 (en) 2005-06-28 2008-07-22 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
SG130066A1 (en) * 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP4108701B2 (ja) 2005-09-12 2008-06-25 株式会社ルネサステクノロジ Ｉｃカードの製造方法
US7602054B2 (en) 2005-10-05 2009-10-13 Semiconductor Components Industries, L.L.C. Method of forming a molded array package device having an exposed tab and structure
US20070152310A1 (en) 2005-12-29 2007-07-05 Tessera, Inc. Electrical ground method for ball stack package
KR100673965B1 (ko) * 2006-01-11 2007-01-24 삼성테크윈 주식회사 인쇄회로기판 및 반도체 패키지 제조방법
JP2007188916A (ja) 2006-01-11 2007-07-26 Renesas Technology Corp 半導体装置
KR100690247B1 (ko) 2006-01-16 2007-03-12 삼성전자주식회사 이중 봉합된 반도체 패키지 및 그의 제조 방법
US20070176297A1 (en) 2006-01-31 2007-08-02 Tessera, Inc. Reworkable stacked chip assembly
CN101375299B (zh) 2006-02-02 2012-08-08 松下电器产业株式会社 存储卡及存储卡的制造方法
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
KR20070088177A (ko) 2006-02-24 2007-08-29 삼성테크윈 주식회사 반도체 패키지 및 그 제조 방법
US20080002460A1 (en) 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
US7514780B2 (en) 2006-03-15 2009-04-07 Hitachi, Ltd. Power semiconductor device
US7368319B2 (en) 2006-03-17 2008-05-06 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
CN100511588C (zh) 2006-04-14 2009-07-08 泰特科技股份有限公司 导线架型芯片级封装方法
SG136822A1 (en) * 2006-04-19 2007-11-29 Micron Technology Inc Integrated circuit devices with stacked package interposers
TW200743190A (en) 2006-05-10 2007-11-16 Chung-Cheng Wang A heat spreader for electrical device
JP5026736B2 (ja) 2006-05-15 2012-09-19 パナソニックヘルスケア株式会社 冷凍装置
EP2041792A2 (en) 2006-06-20 2009-04-01 Nxp B.V. Integrated circuit and assembly therewith
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
TWI306658B (en) 2006-08-07 2009-02-21 Chipmos Technologies Inc Leadframe on offset stacked chips package
US7638868B2 (en) 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US7906844B2 (en) 2006-09-26 2011-03-15 Compass Technology Co. Ltd. Multiple integrated circuit die package with thermal performance
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
KR100825784B1 (ko) 2006-10-18 2008-04-28 삼성전자주식회사 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법
JP4389228B2 (ja) * 2006-11-29 2009-12-24 エルピーダメモリ株式会社 メモリモジュール
US7772683B2 (en) 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
WO2008076790A2 (en) * 2006-12-14 2008-06-26 Rambus Inc. Multi-die memory device
US20100071944A1 (en) 2006-12-19 2010-03-25 Tessera Interconnect Materials, Inc. Chip capacitor embedded pwb
JP2008177241A (ja) 2007-01-16 2008-07-31 Toshiba Corp 半導体パッケージ
JP5120266B6 (ja) 2007-01-31 2018-06-27 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5285224B2 (ja) * 2007-01-31 2013-09-11 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置
JP2008198841A (ja) 2007-02-14 2008-08-28 Elpida Memory Inc 半導体装置
JP2008235576A (ja) 2007-03-20 2008-10-02 Fujitsu Ltd 電子部品の放熱構造及び半導体装置
US7872356B2 (en) 2007-05-16 2011-01-18 Qualcomm Incorporated Die stacking system and method
US20080296717A1 (en) 2007-06-01 2008-12-04 Tessera, Inc. Packages and assemblies including lidded chips
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US7830000B2 (en) 2007-06-25 2010-11-09 Epic Technologies, Inc. Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR101341566B1 (ko) 2007-07-10 2013-12-16 삼성전자주식회사 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법
US20090071707A1 (en) 2007-08-15 2009-03-19 Tessera, Inc. Multilayer substrate with interconnection vias and method of manufacturing the same
JP2010537403A (ja) 2007-08-15 2010-12-02 テッセラ，インコーポレイテッド メッキによって形成されたポストを有する相互接続要素
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US7442045B1 (en) 2007-08-17 2008-10-28 Centipede Systems, Inc. Miniature electrical ball and tube socket with self-capturing multiple-contact-point coupling
US20090051043A1 (en) 2007-08-21 2009-02-26 Spansion Llc Die stacking in multi-die stacks using die support mechanisms
US7872340B2 (en) 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
US7880310B2 (en) * 2007-09-28 2011-02-01 Intel Corporation Direct device attachment on dual-mode wirebond die
WO2009045371A2 (en) 2007-09-28 2009-04-09 Tessera, Inc. Flip chip interconnection with double post
US7851267B2 (en) 2007-10-18 2010-12-14 Infineon Technologies Ag Power semiconductor module method
US20090168374A1 (en) 2008-01-02 2009-07-02 Clayton James E Thin multi-chip flex module
JP5207868B2 (ja) 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
US8138610B2 (en) 2008-02-08 2012-03-20 Qimonda Ag Multi-chip package with interconnected stacked chips
US8354742B2 (en) 2008-03-31 2013-01-15 Stats Chippac, Ltd. Method and apparatus for a package having multiple stacked die
US8159052B2 (en) 2008-04-10 2012-04-17 Semtech Corporation Apparatus and method for a chip assembly including a frequency extending device
US7928562B2 (en) 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US8253231B2 (en) * 2008-09-23 2012-08-28 Marvell International Ltd. Stacked integrated circuit package using a window substrate
KR101479461B1 (ko) 2008-10-14 2015-01-06 삼성전자주식회사 적층 패키지 및 이의 제조 방법
JP5056718B2 (ja) 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
US8049339B2 (en) 2008-11-24 2011-11-01 Powertech Technology Inc. Semiconductor package having isolated inner lead
US7951643B2 (en) 2008-11-29 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system with lead frame and method of manufacture thereof
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US20100193930A1 (en) 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
KR101566407B1 (ko) * 2009-03-25 2015-11-05 삼성전자주식회사 적층 메모리 소자
TWI401785B (zh) 2009-03-27 2013-07-11 Chipmos Technologies Inc 多晶片堆疊封裝
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
KR101601847B1 (ko) 2009-05-21 2016-03-09 삼성전자주식회사 반도체 패키지
KR20100134354A (ko) 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
TWM370767U (en) 2009-06-19 2009-12-11 fu-zhi Huang Modulized computer
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US20110085304A1 (en) 2009-10-14 2011-04-14 Irvine Sensors Corporation Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias
US10128206B2 (en) 2010-10-14 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8378478B2 (en) 2010-11-24 2013-02-19 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts
KR101061531B1 (ko) 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8304881B1 (en) * 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8723327B2 (en) 2011-10-20 2014-05-13 Invensas Corporation Microelectronic package with stacked microelectronic units and method for manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI763200B (zh) * 2020-06-29 2022-05-01 日商鎧俠股份有限公司 記憶體系統

Also Published As

Publication number Publication date
WO2012145114A1 (en) 2012-10-26
US9093291B2 (en) 2015-07-28
US20130056870A1 (en) 2013-03-07
JP2014514766A (ja) 2014-06-19
CN103620774A (zh) 2014-03-05
US8304881B1 (en) 2012-11-06
CN103620774B (zh) 2016-10-05
US20140042644A1 (en) 2014-02-13
US20120267797A1 (en) 2012-10-25
TW201248809A (en) 2012-12-01
EP2700097A1 (en) 2014-02-26
KR20140028015A (ko) 2014-03-07
US8436458B2 (en) 2013-05-07

Similar Documents

Publication Publication Date Title
TWI523174B (zh) 覆晶、面上及面下之打線接合結合封裝件
TWI505420B (zh) 覆晶、面向上型及面向下型中心接合記憶體導線接合總成
TWI545722B (zh) 具有堆疊面下連接晶粒之多晶片模組
TWI479630B (zh) 具中心接觸件之增強堆疊微電子總成以及其之系統、模組及配置
TWI524440B (zh) 具有貫穿之半導體通孔之積體電路封裝系統及其製造方法
US9312239B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US20130082394A1 (en) Stub minimization for multi-die wirebond assemblies with parallel windows
KR20170098586A (ko) 반도체 패키지
US11869829B2 (en) Semiconductor device with through-mold via
US9165906B2 (en) High performance package on package
US9543277B1 (en) Wafer level packages with mechanically decoupled fan-in and fan-out areas
TWI395319B (zh) 避免封裝堆疊接點斷裂之半導體組合構造
TW201729369A (zh) 用於偏移接合通孔陣列之經加固的導線
TW201316485A (zh) 半導體封裝件及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees