TW201729369A - 用於偏移接合通孔陣列之經加固的導線 - Google Patents

用於偏移接合通孔陣列之經加固的導線 Download PDF

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Publication number
TW201729369A
TW201729369A TW105137430A TW105137430A TW201729369A TW 201729369 A TW201729369 A TW 201729369A TW 105137430 A TW105137430 A TW 105137430A TW 105137430 A TW105137430 A TW 105137430A TW 201729369 A TW201729369 A TW 201729369A
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Taiwan
Prior art keywords
dielectric layer
wire
microelectronic
wire bond
wire bonds
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TW105137430A
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English (en)
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拉傑許 卡特卡爾
阿修克Ｓ 普拉布
葛蘭特 維拉維森席歐
相日 李
羅西安 阿拉托勒
賈維爾Ａ 迪拉克魯茲
史考特 麥克葛拉斯
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英帆薩斯公司
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Publication of TW201729369A publication Critical patent/TW201729369A/zh

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Abstract

一種構件，其可包括大致上平坦元件、覆於所述大致上平坦元件上的強化的介電層、覆於所述強化的介電層上的囊封以及多個導線接合。每一個導線接合在所述囊封的主要表面處皆具有端部。所述導線接合可具有在所述強化的介電層內延伸的第一部分。所述導線接合的至少一些的所述第一部分可具有可改變各自所述導線接合的延伸方向的彎曲部。所述強化的介電層可具有圍繞所述導線接合的各自導線接合的突出區域，與所述突出區域的相鄰突出區域之間的所述強化的介電層的部分相比，所述突出區域延伸至從所述大致上平坦元件的所述第一表面算起還要高的尖峰高度。所述突出區域的所述尖峰高度可與所述強化的介電層和個別導線接合之間的接觸點重合。

Description

用於偏移接合通孔陣列之經加固的導線
本發明在此處的實施例是有關於可被使用在堆疊式封裝組件(package on package assembly)中的各種結構和製造微電子封裝的方式，並且更具體地說，是有關於結合了導線接合的這類結構以作為堆疊式封裝連接(package-on-package connection)的一部分。
相關申請案的交互參照
本申請案請求於2015年11月18日提交的美國臨時專利申請案第62/257,223號的申請日的權益，其揭示內容藉此以引用的方式被併入於此處。
微電子裝置(諸如半導體晶片)通常需要許多輸入以及輸出連接至其它電子構件。半導體晶片或其它可類似裝置的輸入與輸出接點一般是以實質上覆蓋裝置表面的類格柵圖樣(通常被稱為「區域陣列(area array)」)被設置，或是以可延伸平行於且相鄰於裝置前表面的每一個邊緣的細長列被設置，或是被設置在前表面的中央。一般來說，裝置(諸如晶片)必須被實體安裝在基板(諸如印刷電路板)上，並且裝置的接點必須被電性連接至電路板的電性傳導特徵。
半導體晶片通常是以封裝的方式被提供，封裝有助於在製造 期間以及安裝晶片於外部基板(諸如電路板或是其它電路面板)上的期間對晶片進行處理。舉例而言，許多半導體晶片以適用於表面安裝的封裝方式被提供。已經有眾多屬於此一般類型的封裝被提出用於各種應用中。最常見的是，此些封裝包括介電元件，其通常被稱為「晶片載體」，而在介電質上有被形成作為鍍覆或蝕刻金屬結構的端子。這些端子通常藉由特徵結構(諸如沿著晶片載體本身延伸的細跡線)以及藉由延伸在晶片的接點與端子或跡線之間的精細引線或導線被連接至晶片本身的接點。於表面安裝操作中，封裝是被放置在電路板上，以使得封裝上的每一個端子對齊電路板上的對應接觸墊。焊料或是其它接合材料是被提供在端子與接觸墊之間。封裝可藉由加熱組件以熔化或「回焊」焊料或是以其他方式活化接合材料而永久地被接合在原位。
許多封裝包括處於焊料球的形式的焊料塊體，其直徑通常約0.1mm以及約0.8mm(5以及30mils)，其會被附接至封裝的端子。具有從其底部表面處突出的焊料球陣列的封裝通常稱為球柵陣列(ball grid array)或「BGA」封裝。稱為平面格柵陣列(land grid array)或「LGA」封裝的其它封裝是藉由自焊料所形成的薄層或平面被固定至基板。屬於此類型的封裝可以是相當小型的。一般稱為「晶片級封裝」的特定封裝佔據電路板的面積會等於或僅略大於併入於封裝中的裝置面積。此優點在於它會縮減組件的總尺寸並且允許在基板上的各種裝置間使用短互連件，因而限定裝置間的訊號傳遞時間且因此有助於組件的高速操作。
經封裝的半導體晶片經常以「堆疊」排列的方式來提供，其中一封裝被提供(舉例而言)在電路板上，並且另一封裝被安裝在第一個 封裝的頂部上。這些排列可以讓數個不同晶片被安裝在電路板上的單一覆蓋區內，並且可以藉由在封裝間提供短互連件而進一步有助於高速運作。經常，此互連距離僅是略大於晶片本身的厚度。為了在晶片封裝的堆疊內達成互連，必須在每一個封裝的兩側(除最頂端的封裝之外)上提供用於機械與電性連接的結構。這已經(舉例而言)藉由在安裝了晶片的基板的兩側上提供接觸墊或平面而達成，墊會藉由傳導通孔或類似物通過基板而連接。焊料球或類似物已經被用來橋接下方基板的頂部上的接點至下一個較高基板的底部上的接點之間的間隙。焊料球必須高於晶片的高度，以便連接接點。堆疊晶片排列與互連結構的範例被提供在美國專利申請公開案第2010/0232129號(亦即，'129公開案)中，在此處以引用的方式將其揭示內容完整併入。
處於細長柱或接腳形式的微接點元件可以被用來連接微電子封裝至電路板並且用於微電子封裝中的其它連接。在一些實例中，微接點是已經藉由蝕刻金屬結構而形成，金屬結構包括用以形成微接點的一或多個金屬層。蝕刻製程會限制微接點的尺寸。習知蝕刻製程通常無法形成具有大的高度與最大寬度之比值(在此處稱為「深寬比(aspect ratio)」)的微接點。一直是困難的或者不可能的是，形成具有顯著高度且相鄰微接點間有超小間距或間隔的微接點陣列。再者，藉由習知蝕刻製程所形成的微接點的配置亦會受到限制。上面的所有描述雖然在本領域中已有進步，但是仍希望在製造與測試微電子封裝中作進一步改善。
根據本發明的態樣，一種構件可包括：大致上平坦元件，其 具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面；強化的介電層，其覆於所述大致上平坦元件的所述第一表面上；囊封，其覆於所述強化的介電層上；以及多個導線接合。所述大致上平坦元件可在所述第一表面處具有多個接點。所述囊封可具有背對所述大致上平坦元件的所述第一表面的主要表面。每一個導線接合皆可具有與所述多個接點的其中一個接點連結的基底以及遠離於所述基底在所述囊封的所述主要表面處的端部。
所述導線接合可具有在所述強化的介電層的至少一部分內延伸的第一部分和在所述囊封內延伸的第二部分。所述導線接合的至少一些的所述第一部分可具有在所述第一方向和所述第二方向中的至少一者改變各自所述導線接合的延伸方向的彎曲部。所述強化的介電層可具有圍繞所述多個導線接合的各自導線接合的突出區域，與所述強化的介電層在所述突出區域的相鄰突出區域之間的部分從所述大致上平坦元件的所述第一表面延伸相比，所述突出區域延伸至還要高的尖峰高度。所述突出區域的所述尖峰高度可與所述強化的介電層和所述導線接合的個別導線接合之間的接觸點重合。
在一實施例中，所述構件可包括微電子封裝。所述微電子封裝亦可包括具有相反面對的頂部表面和底部表面的微電子元件。所述底部表面可面對所述大致上平坦元件的所述第一表面並且可與其機械耦合。所述囊封的所述主要表面可覆於所述微電子元件的所述頂部表面上。在特定範例中，所述導線接合的所述至少一些的子集合的所述端部覆於所述微電子元件的所述頂部表面上。在示範性實施例中，所述導線接合的所述基底 在所述基底的相鄰基底之間界定第一最小間距，並且所述導線接合的所述端部在所述端部的相鄰端部之間界定第二最小間距，所述第二最小間距大於所述第一最小間距。在一範例中，所述介電層可覆於所述微電子元件的所述頂部表面上。
在特定實施例中，所述強化的介電層可包括覆於所述大致上平坦元件的所述第一表面上的第一強化的介電層以及覆於所述第一強化的介電層上且界定所述強化的介電層的上表面的第二強化的介電層。在一實施例中，所述導線接合的所述第一部分的所述彎曲部可以是第一彎曲部，並且所述導線接合的所述至少一些各自包括在所述第一方向和所述第二方向中的至少一者改變各自所述導線接合的所述延伸方向的第二彎曲部。在特定範例中，所述導線接合的所述第二彎曲部的至少一些可以是被設置在所述強化的介電層內。在示範性實施例中，所述強化的介電層可被配置以在當在垂直於所述第一方向和所述第二方向的第三方向上對於所述導線接合的所述端部施加力時，在所述第三方向上保持所述導線接合的所述端部的位置。
在一範例中，上面描述的所述微電子封裝亦可包括與所述導線接合的對應導線接合連結的多個上方端子。所述上方端子可以是在所述囊封的所述主要表面處並且可以被配置以與所述微電子封裝外部的構件的傳導元件電性連接。在特定實施例中，微電子組件可包括如上面描述的所述微電子封裝。所述微電子組件亦可包括具有端子的第二構件，所述導線接合的所述端部電性連接至所述端子。在一實施例中，一種系統可包括如上面描述的所述微電子封裝和電性連接至所述微電子封裝的一或多個其他 電子構件。在特定範例中，所述系統亦可包括外殼，所述微電子封裝和所述一或多個其他電子構件與所述外殼組裝。
根據本發明的另一態樣，一種微電子封裝可包括：大致上平坦元件，其具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面；強化的介電層，其覆於所述大致上平坦元件的所述第一表面上；囊封，其覆於所述強化的介電層上；微電子元件，其具有相反面對的頂部表面和底部表面；以及多個導線接合。所述大致上平坦元件可在所述第一表面處具有多個接點。所述囊封可具有背對所述大致上平坦元件的所述第一表面的主要表面。所述微電子元件的所述底部表面可面對所述大致上平坦元件的所述第一表面並且可與其機械耦合。所述囊封的所述主要表面可覆於所述微電子元件的所述頂部表面上。
每一個導線接合皆可具有與所述多個接點的其中一個接點連結的基底以及遠離於所述基底在所述囊封的所述主要表面處的端部。所述導線接合可具有在所述強化的介電層的至少一部分內延伸的第一部分和在所述囊封內延伸的第二部分。所述導線接合的至少一些的所述第一部分可具有在所述第一方向和所述第二方向中的至少一者改變各自所述導線接合的延伸方向的彎曲部。與所述微電子元件從所述大致上平坦元件的所述第一表面延伸相比，所述強化的介電層可延伸至還要高的尖峰高度。在示範性實施例中，所述導線接合的所述至少一些的子集合的所述端部可覆於所述微電子元件的所述頂部表面上。在一範例中，所述導線接合的所述第一部分的所述彎曲部可以是第一彎曲部，並且所述導線接合的所述至少一些各自可包括在所述第一方向和所述第二方向中的至少一者改變各自所述 導線接合的所述延伸方向的第二彎曲部。
根據本發明的又另一態樣，一種形成構件的方法可包括：提供大致上平坦元件，其具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面；形成多個導線接合；形成強化的介電層，其覆於所述大致上平坦元件上的所述第一表面上；使囊封模流(flowing)在所述強化的介電層和模製膜的下表面之間，所述導線接合的端部延伸至所述模製模中；以及從所述囊封移除所述模製膜。所述大致上平坦元件可在所述第一表面處具有多個接點。每一個導線接合皆可具有與所述多個接點的其中一個接點連結的基底以及遠離所述基底的端部。所述導線接合的至少一些的第一部分可具有在所述第一方向和所述第二方向中的至少一者改變各自所述導線接合的延伸方向的彎曲部。
所述導線接合的所述第一部分可在所述強化的介電層的至少一部分內延伸。所述強化的介電層可具有圍繞所述多個導線接合的各自導線接合的突出區域。與所述強化的介電層在所述突出區域的相鄰突出區域之間的部分從所述大致上平坦元件的所述第一表面延伸相比，所述突出區域可延伸至還要高的尖峰高度。所述突出區域的所述尖峰高度可與所述強化的介電層和所述導線接合的個別導線接合之間的接觸點重合。所述囊封可具有背對所述大致上平坦元件的所述第一表面的主要表面。所述導線接合可具有在所述囊封內延伸的第二部分。所述導線接合的所述端部可以是在所述囊封的所述主要表面處。
在特定實施例中，所述構件可包括如上面描述的微電子封裝。所述微電子封裝亦可包括具有相反面對的頂部表面和底部表面的微電 子元件。所述微電子元件的所述底部表面可面對所述大致上平坦元件的所述第一表面並且可與其機械耦合。所述囊封的所述主要表面可覆於所述微電子元件的所述頂部表面上。在一實施例中，在所述囊封的所述模流之前，所述突出區域可向上芯吸(wick up)所述導線接合並且可達到它們各自的尖峰高度。在特定範例中，所述突出區的所述尖峰高度可以未達到所述導線接合的所述端部。在示範性實施例中，所述方法亦可包括：在所述囊封的所述模流之前，沉積所述模製膜而覆於所述強化的介電層上。所述導線接合的所述端部可延伸至所述模製膜中。
10‧‧‧微電子封裝
20‧‧‧導線接合
20a‧‧‧導線接合
20b‧‧‧位置
21‧‧‧端部
21a‧‧‧端部
21b‧‧‧位置
22‧‧‧基底
23‧‧‧邊緣表面
24‧‧‧未囊封部分
30‧‧‧微電子元件
31‧‧‧底部表面
32‧‧‧頂部表面
33‧‧‧側邊表面
40‧‧‧基板
41‧‧‧第一表面
42‧‧‧第二表面
43‧‧‧接點
44‧‧‧端子
45‧‧‧通孔
50‧‧‧囊封
51‧‧‧主要表面
60‧‧‧模製膜
61‧‧‧下表面
200‧‧‧微電子組件
201‧‧‧第二基板
202‧‧‧第一表面
203‧‧‧第二表面
204‧‧‧第一端子
205‧‧‧第二端子
206‧‧‧通孔
210‧‧‧微電子封裝
220‧‧‧導線接合
220’‧‧‧導線接合
220a‧‧‧導線接合
220b‧‧‧位置
221‧‧‧端部
221a‧‧‧端部
221b‧‧‧位置
222‧‧‧基底
223‧‧‧邊緣表面
225‧‧‧第一部分
226‧‧‧第二部分
227‧‧‧第一彎曲部
228‧‧‧第二彎曲部
229‧‧‧子集合
230‧‧‧微電子元件
231‧‧‧底部表面
232‧‧‧頂部表面
233‧‧‧側邊表面
240‧‧‧基板
241‧‧‧第一表面
243‧‧‧接點
250‧‧‧囊封
251‧‧‧主要表面
270‧‧‧強化的介電層
271‧‧‧主要表面
272‧‧‧下方區域
273‧‧‧突出區域
300‧‧‧微電子組件
301‧‧‧第二基板
310‧‧‧微電子封裝
320‧‧‧導線接合
320a‧‧‧導線接合
320b‧‧‧導線接合
321‧‧‧端部
322‧‧‧基底
325‧‧‧第一部分
326‧‧‧第二部分
327‧‧‧第一彎曲部
328‧‧‧第二彎曲部
330‧‧‧微電子元件
332‧‧‧頂部表面
340‧‧‧基板
341‧‧‧第一表面
350‧‧‧囊封
370‧‧‧強化的介電層
404‧‧‧上方端子
410‧‧‧微電子封裝
443‧‧‧接點
480‧‧‧虛線
500‧‧‧系統
501‧‧‧外殼
502‧‧‧面板
504‧‧‧導體
506‧‧‧模組或構件
508‧‧‧模組或構件
510‧‧‧模組或構件
511‧‧‧構件
圖1說明根據本發明的實施例的微電子封裝的側邊截面圖，微電子封裝包括延伸通過在基板和模製膜之間的囊封物的導線接合。
圖2說明根據圖1的微電子封裝的變化例的微電子封裝的側邊截面圖，微電子封裝包括延伸通過在第一和第二基板之間的加固層和囊封物的導線接合。
圖3說明圖2的微電子封裝的變化例的微電子封裝的側邊截面圖。
圖4說明圖2或圖3的囊封物以及頂部和底部接點的一可能圖解俯視圖。
圖5是根據本發明的一實施例的系統的示意圖。
如圖1中所示，根據本揭示的實施例，處於製程中(in-process)微電子封裝10的形式的構件可以藉由將多個導線接合20和微 電子元件30連結並且電性連接至處於基板40的形式的大致上平坦元件所製成，基板40具有第一表面41和與第一表面相對的第二表面42。電性傳導接點43和電性傳導端子44(其處於接點或墊的形式)可被各別配置在第一表面41和第二表面42處。製程中微電子封裝10可包括囊封50，其形成以延伸在個別導線接合20之間並且覆於微電子元件30和基板40上。模製膜60可被放置在導線接合20的端部21上方，以在形成囊封50時固定導線接合的位置。
如本揭示中所使用的，用語諸如“上(upper)”、“下(lower)”、“頂部(top)”、“底部(bottom)”、“上面(above)”、“下面(below)”以及指示方向的類似用語，參考的是構件自身的參考坐標系，而不是重力參考坐標系。在部件以圖式所示的方向沿重力參考坐標系定向的情況下，在重力參考坐標系中圖式中的頂部在上且圖式中的底部在下時，確實微電子元件的頂部表面在重力參考坐標系中是位於微電子元件的底部表面上面。然而，當部件被翻轉時，在重力參考坐標系中圖式中的頂部面向下時，微電子元件的頂部表面在重力參考坐標系中是位於微電子元件的底部表面下面。
如本揭示中參考一構件(例如，中介件、微電子元件、電路板、基板等等)所使用的，電性傳導元件是“在”構件的表面“處”的聲明所表示的是，當構件未與任何其他元件組裝時，電性傳導元件是可用於與在垂直於構件的表面的方向上從構件外部朝向構件的表面移動的理論點接觸。因此，在基板的表面處的端子或其他傳導元件可從此表面突出；可與此表面齊平；或可相對於此表面在基板中的孔或凹陷中凹入。如在此處 所使用的，用語“約”和“近似”相對於給定數值意指的是，實際值是落在給定數值的相關領域中習知此技術者所知的典型製造公差內。
多個導線接合20可以與至少一些接點43電性連結。導線接合20的每一者可以在其基底22處接合(諸如，球型接合或楔形接合)至各自接點43。導線接合20的每一者可以延伸至遠離此導線接合的基底22和遠離基板20的端部21，並且可以包括從端部21延伸至基底22的邊緣表面23。在特定範例中，導線接合20可具有2密耳(~51微米)、小於2密耳、1.5密耳(~38微米)、小於1.5密耳、1密耳(~25微米)或小於1密耳的直徑。
導線接合20的端部21可以用於電性連接(無論是直接地或間接地如通過焊料球、電性傳導接點或在此處所討論的其他特徵)至微電子封裝10外部的傳導元件。可根據被使用以形成導線接合的材料類型、導線接合和接點43之間所要的連接強度或被使用以形成導線接合的特定製程，改變導線接合20的基底22的特定尺寸和形狀。導線接合20可具有一種構造並且可以用任何合適的方式被形成在基板40上而從接點43延伸，諸如在2012年2月24日所提申的美國專利申請公開案第2013/0093087號中所描述的，其藉以在此處通過引用併入。
微電子元件30可被機械耦合至基板40的第一表面41(例如藉由黏著劑材料)，而微電子元件的底部表面31面對基板的第一表面。微電子元件30可具有與底部表面31相對的頂部表面32。微電子元件可在底部表面31或頂部表面32的任一者或兩者處具有元件接點(未示出)。如在此處所描述的，微電子元件30的元件接點亦可被稱為“晶片接點”。在 一範例中，微電子元件30的元件接點可以是在其中心區域內在底部表面31或頂部表面32的一者處。舉例而言，元件接點可以一或兩個平行的列來配置而鄰近於底部表面31或頂部表面32的中央。
雖然未在圖示中例示微電子元件30和基板40之間的特定電性連接，但是本發明欲涵蓋微電子元件和基板之間各種類型的電性連接，包括(舉例而言)“覆晶”配置，其中在微電子元件30的底部表面31處的元件接點(未示出)可被連接至在基板40的第一表面41處的傳導元件，諸如藉由被定位在微電子元件下方的傳導連結元件(未示出)。在一些實施例中，此些傳導連結元件可以是(舉例而言)接合金屬的塊體(諸如焊料、錫、銦、共晶組成(eutectic composition)或它們的組合)，或是另一連結材料(諸如導電膏、導電性黏著劑或導電基質材料)，或是任何或所有此些接合金屬或導電材料的組合。
在一範例中，藉由延伸通過基板中的孔隙的傳導結構(例如導線接合或引線接合)，在微電子元件30的底部表面31處的元件接點可以與在基板40的第二表面42處的接點電性連接。在另一範例中，藉由延伸在微電子元件的頂部表面上面的傳導結構(例如導線接合)，在微電子元件30的底部表面32處的元件接點可以與在基板40的第一表面41處的接點電性連接。
在一些實施例中，微電子元件30可以各自是半導體晶片、晶圓或類似者。舉例而言，微電子元件30可以各自包括記憶體儲存元件，其諸如動態隨機存取記憶體(DRAM)儲存陣列，或是其被配置以主要作用為DRAM儲存陣列(例如DRAM積體電路晶片)。如在此處所使用的，“記 憶體儲存元件”意指以列來配置的多個記憶體單元，連同可用以從其儲存和擷取資料的電路，諸如用以傳輸資料以通過電子介面。在一範例中，微電子元件30可具有記憶體儲存陣列的功能。在特定實施例中，微電子元件30為提供記憶體儲存陣列功能而體現的主動裝置的數量可大於任何其它功能。
微電子元件30可體現多個主動裝置(例如電晶體、二極體等等)、多個被動裝置(例如電阻器、電容器、電感器等等)或主動裝置和被動裝置兩者。在特定實施例中，微電子元件30可以被配置以具有如邏輯晶片的主要功能(例如，可程式化的通用或專用處理器、微處理器、現場可程式化閘極陣列(FPGA)裝置、特殊應用積體電路(ASIC)、數位訊號處理器等等)，或是除了如邏輯晶片之外諸如記憶體的主要功能(舉例而言，揮發性記憶體儲存區域(動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM))、非揮發性記憶體儲存陣例(諸如快閃記憶體或磁性隨機存取記憶體(MRAM)))。如此，圖1的實施例是處於製程中經封裝微電子元件的形式，諸如被使用在電腦或其他電子應用中的半導體晶片組件。
雖然在圖式中例示的是在微電子封裝10中(以及在此處的其他微電子封裝中)的單一個微電子元件30，但是本揭示中的每一個微電子封裝可包括多個微電子元件，其是以沿著基板40的第一表面41而彼此相鄰的方式、以覆於基板的第一表面上的垂直堆疊的方式或是以在該領域中已知的其他配置的方式被配置。
基板40可包括介電元件，其在一些情況下可基本上由聚合性材料所組成，例如樹脂或聚酰亞胺等等，並且其可以是大致上平坦的。 介電元件可以是薄片狀並且可以是薄的。替代而言，基板40可包括具有複合結構的介電元件，諸如玻璃強化的環氧樹脂(例如由BT樹脂或FR-4結構所組成)。在特定實施例中，介電元件可包括一或多層有機介電材料或複合介電材料，諸如(但不限於)：聚酰亞胺，聚四氟乙烯(PTFE)，環氧樹脂，環氧玻璃(epoxy-glass)，FR-4，BT樹脂，熱塑性或熱固性塑料材料。在另一範例中，基板可包括具有由小於每攝氏度百萬分(ppm/℃)之12的熱膨脹係數(CTE)的材料所製成的支撐元件，而接點41、端子42和其他傳導結構可以被設置在其上。舉例而言，此低CTE的元件可基本上由玻璃、陶瓷、半導體材料、或液晶聚合物材料、或此些材料的組合所組成。替代而言，基板40可以是電路面板或電路板。在其一範例中，基板可以是雙直列記憶體模組(DIMM)的模組板。在一範例中，基板可包括由具有小於30ppm/℃的CTE的材料所製成的支撐元件。
第一表面41和第二表面42可以大致上彼此平行並且隔開一段與界定基板的厚度T的該些表面垂直的距離。基板40的厚度可以是對本申請案而言在大致上可接受的厚度範圍內。在一實施例中，第一表面41和第二表面42之間的距離是在約10~500μm之間。為了討論的目的，第一表面41可以被描述為被定位於與第二表面42相對或遠離第二表面42。此描述以及任何其他在此處所使用的元件的相對位置的描述(其指出此些元件的垂直或水平位置)僅是用於說明的目的，以對應圖式中的元件位置，並且是非限制性的。
接點43和端子44可以是平坦、薄電性傳導元件。接點43和端子44可以是固體金屬材料，諸如銅、金、鎳、鈀，或是對於比應用而 言可接受的其他材料，包括含有銅、金、鎳、鈀或它們的組合中的一或多種的各種合金。至少一些接點43可以被互連到相應端子44。此互連可以利用形成在基板40中而可被內襯或填充有傳導金屬的通孔45來完成，傳導金屬可以是由與接點43和端子44相同的材料所形成。選擇性而言，接點43和端子44可以藉由基板40上的跡線(未示出)進一步彼此互連。端子44可以被配置用於與外部構件(諸如，另一微電子封裝或是如電路板的電路面板)電性互連。
與基板40的第一表面41平行的橫向的第一方向D1和第二方向D2(例示於圖4中)在此處被稱為“水平的”或“側向的”方向，而與第一表面垂直的方向(例如，D3)在此處被稱為向上或向下的方向且在此處亦被稱為“垂直的”方向。在此處所提到的方向是在所提到的結構的參考坐標系中。因此，這些方向可位於相對於重力參考坐標系中的一般“上”或“下”方向而言任何指向上。
一特徵是被設置在“一表面上面”與另一特徵相比較高的位置處的聲明所意指的是，一特徵是位於一在相同正交方向上與其他特徵相比離該表面較遠的距離處。相反地，一特徵是被設置在“一表面上面”與另一特徵相比較低的位置處的聲明所意指的是，一特徵是位於一在相同正交方向上與其他特徵相比離該表面較近的距離處。
囊封50可以被形成以延伸在個別導線接合20之間並且覆於微電子元件30的頂部表面32和基板40的第一表面41上。囊封50可以由介電材料所形成，諸如在該領域中已知為被典型地用於囊封或包覆成型(overmold)的那些材料。在圖1的實施例中，囊封50可(舉例而言)藉 由膜輔助模製(film-assisting molding)或類似技術而形成在基板40的第一表面41的未另外被微電子元件30或接點43所覆蓋或佔據的部分上方。
囊封50(理想地是一整體、連續的介電層)可用以保護在微電子封裝10內的傳導元件，特別是導線接合20。囊封50亦可大致上覆蓋微電子元件30、導線接合20(包括基底22)和其邊緣表面23的至少一部分。此外，囊封50可被形成在微電子元件30的延伸在底部表面31和頂部表面32之間的側邊表面33上方。囊封50可以保護微電子元件50，以避免在導線接合20之間電性短路，並且有助於避免由於導線接合和微電子元件之間非故意的電性接觸所造成的故障或可能的損壞。
囊封50可允許更堅固的結構，而較不容易由於其之測試或在運輸或與其他微電子結構的組裝期間受到損壞。囊封50可以是由具有絕緣特性的介電材料所形成，諸如在美國專利申請公開案第2010/0232129號中所描述的，其藉以在此處通過引用併入。
在一些實施例中，導線接合20的部分可以保持未被囊封50所覆蓋，其亦可以被稱為未囊封部分24，藉此使導線接合可用於電性連接至位於囊封50外部的傳導特徵或元件。在一些實施例中，至少導線接合20的端部21和選擇性而言邊緣表面23的部分可保持未被囊封50所覆蓋，諸如在美國專利申請公開案第2013/0093087號中所描述的，其藉以在此處通過引用併入。換句話說，囊封50可以從第一表面41以上覆蓋整個微電子封裝30，除了導線接合20的一部分之外，諸如端部21、邊緣表面23的部分或它們的組合。
導線接合20的端部21可以在形成囊封50時延伸至模製膜 60中。舉例而言，模製膜60可以被提供在模板的內部表面上。在囊封50被形成在含有製程中微電子封裝10和模製膜的模具內之後，模製膜可以從囊封移除，諸如藉由施加合適的化學物質以脫離或溶解模製膜。在一實施例中，模製膜60可以由水溶性的塑膠材料所製成，以使得它可以藉由暴露於水而移除，而不影響製程中單元或微電子封裝10中的其他構件。在另一實施例中，模製膜60可以在暴露於紫外光之後從囊封50移除。在移除模製膜60之後，導線接合20的端部21可以保持未覆蓋，並且因而可用於與其他構件電性連接，諸如另一微電子組件或微電子封裝的跡線、墊或端子。
在圖1的實施例中，導線接合20的端部21可在形成囊封50之前接觸模製膜60，並且導線接合的端部的至少一些會在方向D3上向下偏轉(亦即，朝基板40的第一表面41)。導線接合20的端部21的至少一些的此向下偏轉會妨礙受影響的端部在囊封50的主要表面51處與其他傳導元件電性互連。此外，導線接合20的端部21的至少一些的此向下偏轉會導致在導線接合之間電性短路，和/或由於導線接合和微電子元件30之間非故意的電性接觸所造成的故障或可能的損壞。
舉例而言，如圖1中所示，其中一個導線接合20a的其中一個端部21a會被模製膜60在方向D3上向下偏轉一距離D，以使得端部21a向下移動至位置21b，並且導線接合向下偏轉至位置20b。導線接合20a的此向下偏轉會導致導線接合和微電子元件30之間非故意的電性接觸，和/或在導線接合之間電性短路。
導線接合20的端部21的此向下偏轉對於包括具有約1密耳或更小(約25微米或更小)的直徑的導線接合的BVA和BGA互連而言會 是一個重要的問題。導線接合20的端部21的此向下偏轉對於包括具有大於1密耳的直徑的導線接合的BVA和BGA互連而言亦會是一個重要的問題。在此處所描述的結構可在BVA和BGA互連介面處導致較少的應力。此類結構亦允許微電子結構的連結且具有較小的連結單元尺寸，而可減少經連結的微電子結構的擴散動能(diffusion kinetics)和厚度。
圖2說明包括處於微電子封裝210的形式的構件的微電子組件200，微電子封裝210是圖1的微電子封裝10的變化例。以下未描述的微電子封裝210的元件應被理解為是與上面參照例示於圖1中的微電子封裝10所描述的對應元件相同。
微電子組件200可包括微電子封裝210，其以如下面所描述的方式被連結且電性連接至第二基板201。微電子封裝210可包括多個導線接合220和微電子元件230，其被連結且電性連接至處於基板240的形式的大致上平坦元件。導線接合220的至少一些可包括鄰近於導線接合的基底222的第一部分225與鄰近於導線接合的端部221的第二部分226。
微電子封裝210可包括囊封250，其被形成以延伸在個別導線接合220的第二部分226之間，以及強化的介電層270，其被形成以延伸在個別導線接合220的第一部分225之間且覆於微電子元件230的頂部表面232與基板240的第一表面241上。囊封250的主要表面251可覆於微電子元件230的頂部表面232上。導線接合220的至少一些的端部221可以在囊封250的主要表面251處暴露。
強化的介電層270可在形成囊封250之前形成。強化的介電層270可以與微電子元件230和基板240的第一表面241兩者機械耦合。囊 封250可覆於強化的介電層270的上表面271上，並且可具有覆於強化的介電層和微電子元件230的頂部表面232上的主要表面251。
強化的介電層270可以被形成以延伸在個別導線接合220之間並且覆於微電子元件230的頂部表面232和基板240的第一表面241上。在圖2的實施例中，強化的介電層270可被形成在基板240的第一表面241的未被微電子元件230或接點243所另外覆蓋或佔據的部分上方。強化的介電層270可以是由介電材料所形成之一整體、連續的層。強化的介電層270可界定出背對基板240的第一表面241的上表面271。
強化的介電層270亦可大致上覆蓋微電子元件230、導線接合220的第一部分220(包括基底222)和其邊緣表面223的至少一部分。此外，強化的介電層270可被形成在微電子元件230延伸在底部表面231和頂部表面232之間的側邊表面233上方。強化的介電層270可以保護微電子元件230，以避免在導線接合220間電性短路，並且有助於避免由於導線接合和微電子元件之間非故意的電性接觸所造成的故障或可能的損壞。在一範例中，強化的介電層270的上表面271可覆於微電子元件230的頂部表面231上。
強化的介電層270可被配置以為導線接合220的第一部分225提供加固功能。導線接合220的第一部分225可在強化的介電層270的至少一部分內延伸。強化的介電層270可被配置以在當在垂直於第一方向和第二方向(圖4的D1和D2)的第三方向上對於導線接合的端部施加力時，在所述第三方向D3上保持導線接合220的端部221的位置。
在特定範例中，強化的介電層270可具有比囊封的楊氏模數 還高的楊氏模數。然而，一旦提出所需加固功能，強化的介電層的楊氏模數也可以是任何合適的數值。在一範例中，強化的介電層270可以是由環氧樹脂所製成，並且可具有在5~50Gpa之間的楊氏模數，並且囊封250的楊氏模數的數值和強化的介電層的楊氏模數的數值相比可以較低、較高或相同。
強化的介電層270的上表面271可具有下方區域272和圍繞導線接合220的個別者的突出區域273。下方區域272可延伸在突出區域273的相鄰突出區域273之間。下方區域272可延伸至從基板240的第一表面241算起的第一尖峰高度A1，並且突出區域可延伸至從基板的第一表面算起的第二尖峰高度A2。與強化的介電層270在相鄰突出區域之間的部分272從基板240的第一表面241延伸的尖峰高度A1相比，突出區域273可延伸至更大的尖峰高度A2。突出區域273從基板240的第一表面241算起的尖峰高度A2可與在強化的介電層270和導線接合220的個別導線接合220之間的接觸點重合。在此處所示的範例中，突出區域273的第二尖峰高度A2並未達到囊封250的主要表面251，並且突出區域的第二尖峰高度A2並未達到導線接合220的端部221。
雖然強化的介電層270的上表面271的下方區域272在圖2及圖3中是被示為延伸至從基板240的第一表面241算起的均一第一尖峰高度A1，但不必是這種情況。在一些範例中，強化的介電層270的上表面271的下方區域272的不同部分可延伸至從基板240的第一表面241算起的各種第一尖峰高度A1。在一些範例中，強化的介電層270的上表面271的突出區域273中的個別者可各自延伸至從基板240的第一表面241算起的不同第 二尖峰高度A2。每一個突出區域273可圍繞導線接合270中的一或多個個別導線接合270。每一個突出區域273自己可具有在基板240的第一表面241上面的第二尖峰高度A2而與導線接合270的個別導線接合270中的一者的接觸點重合。
強化的介電層270可以是由具有絕緣特性的介電材料所形成，諸如環氧樹脂或另一合適的聚合性材料。強化的介電層270可以是由相對黏稠(例如，比囊封物250的材料更黏稠)的介電材料所形成。強化的介電層270可以是由介電材料所形成，該介電材料濕潤導線接合220的邊緣表面223，並且可在形成期間芯吸(wick up)邊緣表面向上至從基板240的第一表面241算起的第二尖峰高度A2。在一範例中，在形成囊封物材料250之前，強化的介電層270的上表面271的突出區域273可向上芯吸導線接合220並且達到它們各自的第二尖峰高度A2。在此處所示的範例中，突出區域273的第二尖峰高度A2並未達到導線接合220的端部221。
導線接合220可各自具有連結到接點243中的對應一者的基底222和遠離基底的端部221。導線接合220的至少一些可具有在強化的介電層270的至少一部分內延伸的第一部分225和在囊封250內延伸的第二部分226。導線接合220中的至少一些的第一部分225(其在強化的介電層270內延伸)可各自包括在第一方向D1和第二方向D2中的至少一者改變各自導線接合的延伸方向E1的第一彎曲部227。在一實施例中，導線接合220的第一部分225的第一彎曲部227中的至少一些可以是被設置在強化的介電層270內。
在一些範例中，導線接合220中的至少一些的第二部分226 (其在囊封250內延伸)可各自包括在第一方向D1和第二方向D2中的至少一者改變各自導線接合的延伸方向E1的第二彎曲部228。在一實施例中，導線接合220的第二彎曲部228中的至少一些可以是被設置在強化的介電層270內。在一範例中，導線接合220的第一彎曲部227和第二彎曲部228中的至少一些可以是被設置在強化的介電層270內。如圖2中所示，可不需要讓所有的導線接合220皆具有第一彎曲部227和/或第二彎曲部228。舉例而言，導線接合220’不具有第一彎曲部227或第二彎曲部228。
在特定範例中，導線接合220的第一彎曲部227中的至少一些可以是被設置在強化的介電層270內，而導線接合220的第二彎曲部228中的至少一些可以是被設置在囊封250內。在一些實施例中，導線接合的第一彎曲部227和第二彎曲部228可允許導線接合的子集合229中的端部221覆於微電子元件230的頂部表面232上。
位於基板240的第一表面241上面的各自突出區域273的第二尖峰高度A2可以是比各自導線接合220的第一彎曲部227的高度A3位於更遠的地方。位於基板240的第一表面241上面的各自導線接合220的第二彎曲部228的高度A4可以是比各自突出區域273的第二尖峰高度A2位於更遠的地方。
導線接合220的第一彎曲部227和第二彎曲部228可以在基板240的第一表面241和囊封250的主要表面251之間的導線接合提供間距改變的作用。如同可以在圖2的範例中見到的，導線接合220的基底222可在基底中的相鄰基底之間界定第一最小間距P1，並且導線接合的端部221在端部中的相鄰端部之間界定第二最小間距P2，第二最小間距大於第一最 小間距。在一範例中，第一最小間距P1可以是40~200微米，並且第二最小間距P2可以是150~300微米。
類似於圖1，此類似於模製模60的模製模可以被降低到從基板240的第一表面2414延伸的導線接合220的端部221上，以在形成囊封250時固定導線接合的位置。在形成強化的介電層270之後並且在形成囊封250之前，模製模可以被沉積在導線接合220的端部221上。
在圖2中所示的範例中，當形成強化的介電層270之後導線接合的端部221接觸模製膜時，強化的介電層可在當在第主方向上D3對導線接合的端部施加力時，在第三方向D3上保持導線接合220的端部221的位置。舉例而言，如圖2中所示，當模製模被施加至其中一個導線接合220a的其中一個端部221a時，強化的介電層270可加固導線接合，藉此阻止端部在方向D3上向下偏轉一距離D至位置221b，並且阻止導線接合向下偏轉至位置220b。
在一些實施例中，在囊封物材料250的模流(flowing)之前，模製膜可被沉積在導線接合220的端部221上，而端部延伸至模製膜中，模製模覆於強化的介電層270上。在導線接合220的端部221接觸模製膜之後，囊封物材料250可被模流在強化的介電層270的上表面271和導線接合的端部所延伸於其中的模製膜的下表面(例如，圖1中所示的下表面61)之間。在囊封250被形成在含有微電子封裝210和模製膜的模具內之後，膜製膜可藉由上面參考圖1所描述的任何移除方法從囊封移除，並且導線接合220的至少一些的端部221可在囊封250的主要表面271處暴露。
在一些實施例中，強化的介電層270可包括覆於基板240的 第一表面241上的第一強化的介電層，以及覆於第一強化的介電層上且界定強化的介電層的上表面271的第二強化的介電層。在此些實施例中，第一部分225可延伸通過第一和第二強化的介電層，強化的介電層270的上表面271的下方區域272和突出區域273可被形成在第二強化的介電層中。
如圖2中所示，微電子組件200亦可包括第二基板201。第二基板201可以是具有相對的第一表面202和第二表面203的構件。第二基板201可在第一表面202處具有第一端子204且在第二表面203處具有第二端子205。第一端子204中的至少一些可以被電性互連到第二端子205中的相應者。此互連可以利用形成在基板40中的通孔206來完成，舉例而言，通孔206可被內襯或填充有傳導金屬，傳導金屬可以是由與第一端子204和第二端子205相同的材料所形成。第二端子205可以被配置用於與外部構件(諸如，另一微電子封裝或是如電路板的電路面板)電性互連。在圖2中所示的範例中，導線接合220的端部221可以被電性連接至第二基板201的第一端子204。
在一實施例中，第一端子204可以是封裝210在囊封的主要表面251處的上方端子。在此實施例中，第一端子204可以被配置以與微電子封裝210外部的構件(諸如，第二基板201、另一微電子封裝或是如電路板的電路面板)的傳導元件電性連接。
圖3說明包括處於微電子封裝310的形式的構件的微電子組件300，微電子封裝300是圖2中的微電子封裝210的變化例。以下未描述的微電子封裝310的元件應被理解為是與上面參照例示於圖2中的微電子封裝210所描述的對應元件相同。
微電子組件300可包括微電子封裝310，其被連結且電性連接至第二基板301。微電子封裝310可包括多個導線接合320和微電子元件330，其被連結且電性連接至處於基板340的形式的大致上平坦元件。微電子封裝310可包括囊封350，其被形成以延伸在個別導線接合320的第二部分326之間，以及強化的介電層370，其被形成以延伸在個別導線接合320的第一部分325且覆於微電子元件330的頂部表面332與基板340的第一表面341上。
如可以在圖3中見到的，導線接合320a中的一些可具有第一彎曲部327和第二彎曲部328，其與其他導線接合320b的第一彎曲部和第二彎曲部相比以更大的角度改變導線接合的延伸方向E1。在此實施例中，導線接合320a的端部321和基底322與導線接合320b的端部和基底相比可以在第一方向D1和第二方向D2中的一者或兩者偏移一更大的距離。在側視圖中，導線接合320a的路徑將呈現與導線接合320b的路徑交叉，如圖3中所示。
在圖3中所示的實施例中，強化的介電層370對於導線接合320a的加固功能可以是特別有利的。假如導線接合320a具有第一彎曲部327和第二彎曲部328而使得導線接合的端部321和基底322在第一方向D1和第二方向D2中的一或兩者與圖2的導線接合相比偏離一更大的距離，則此些導線接合320a的端部與圖2的導線接合的端部相比可在第三方向D3上被更容易地移動。因此，與導線接合320b和圖2的導線接合220相比，強化的介電層370可以當在第三方向上對導線接合的端部施加力時，在第三方向D3上更有效地保持導線接合220a的端部321的位置。
在上面相對於圖2和圖3所描述的實施例的進一步變化例中，微電子元件230和330可被省略。在此些範例中，構件可舉例而言具有如同上面相對於圖2所述的結構，但是微電子元件被省略。在此範例中，構件可以在基板的接點243和端子204之間提供間距改變的作用。在特定範例中，微電子元件可以與此構件合併，舉例而言藉由在形成構件之後將微電子元件安裝至基板的第二表面。替代而言，構件的囊封可提供有開口，其被尺寸化以在製造構件之後的時間點在基板的第一表面上面容納微電子元件的置放。
在進一步變化例中，大致上平坦元件可被提供以替代如圖2中所示的基板240。在特定範例中，大致上平坦元件可以是微電子元件。參照圖1，在此變化例的特定形式中，大致上平坦元件可缺少在與平坦元件的第一表面41(導線接合在此處連結到接點43)相對的第二表面42處的端子44。
圖4說明處於微電子封裝410的形式的構件，微電子封裝410是圖2和圖3中的微電子封裝210和310的變化例。以下未描述的微電子封裝210和310的元件應被理解為是與上面參照例示於圖2和圖3中的微電子封裝210和310所描述的對應元件相同。
如同上面參考圖2所描述的，導線接合的第一彎曲部和第二彎曲部可以在基板的第一表面和囊封的主要表面之間的導線接合提供間距改變的作用。如同可以在圖4的範例中見到的，導線接合的基底可連結到的接點443可在其相鄰的中心之間界定第一最小間距P1，並且導線接合的端部可連結到的上方端子404可在其相鄰的中心之間界定第二最小間距 P2，第二最小間距大於第一最小間距。
此外，如同可以在圖4中見到的，上方端子404的數目可以少於接點443的數目。因此，可能需要的是上方端子404中的一或多個各自被連接到至少兩個接點443。此類對應是例示於圖4中，其中虛線480包圍由四個接點443所組成的示範性群組，其全部皆被短接在一起並且被電性連接至上方端子404中單一對應的一者。在一範例中，此些短接在一起的接點443群組可被配置以攜載電力或參考電壓(亦即，接地)。
上面參考圖1至圖4所描述的微電子封裝和微電子組件可被利用於各種電子系統(諸如圖5中所示的系統500)的建構。舉例而言，根據本發明的進一步實施例的系統500包括多個模組或組件506(諸如上面所描述的微電子封裝和微電子組件)而結合其他電子構件508、510和511。
在所示的示範性系統500中，系統可包括電路面板、主機板或豎式面板(riser panel)502(諸如，可撓性印刷電路板)，並且電路面板可包括將模組或構件506、508和510彼此互連的眾多導體504，在圖5中僅描繪導體504中之一者。此電路面板502可將信號輸送至系統500所包括的微電子封裝和/或微電子組件中之每一者並且自系統500所包括的微電子封裝和/或微電子組件中之每一者輸送信號。然而，此僅為示範性的；可使用在模組或構件506之間形成電性連接之任何合適結構。
在特定實施例中，系統500亦可包括處理器(諸如半導體晶片508)，以使得每一個模組或構件506皆可被配置以在一時脈循環內並行傳送N個資料位元，並且處理器可被配置以在一時脈循環內並行傳送M個資料位元，M大於或等於N。在圖5中描繪的範例中，構件508是半導體晶 片，並且構件510是顯示器螢幕，但任何其它構件皆可在系統500中被使用。當然，儘管為了說明清楚起見而在圖5中僅描繪兩個額外構件508和511，但系統500可包括任何數目的此類組件。
模組或構件506以及構件508及511可被安裝於以虛線示意性地描繪的共同外殼501中，且可在必要時彼此電性互連以形成所要電路。外殼501被描繪為可用於(舉例而言)行動電話或個人數位助理的類型的可攜式外殼，並且螢幕510可在外殼的表面處暴露。在結構506包括光敏感元件(諸如，成像晶片)的實施例中，透鏡511或其他光學裝置亦可被提供，以將光繞送至該結構。再者，圖5中所示的簡化系統僅僅是示範性的；可使用上面所討論的結構製造包括通常被視為固定結構的系統(諸如，桌上型電腦、路由器等等)的其他系統。
應當理解的是，本文中闡述的各種從屬申請專利範圍和特徵可以與初始申請專利範圍中所呈現的方式不同的方式組合。亦應當理解的是，結合個別實施例所描述的特徵可以與所描述實施例中的其他實施例共享。
儘管本發明在此處已經參考特定實施例來加以描述，但將理解的是這些實施例僅僅是說明本發明的原理及應用而已。因此應該理解的是，可對說明的實施例做出許多修改，並且可設計出其它配置，而不脫離如同所附的申請專利範圍所界定的本發明的精神與範疇。
200‧‧‧微電子組件
201‧‧‧第二基板
202‧‧‧第一表面
203‧‧‧第二表面
204‧‧‧第一端子
205‧‧‧第二端子
206‧‧‧通孔
210‧‧‧微電子封裝
220‧‧‧導線接合
220’‧‧‧導線接合
220a‧‧‧導線接合
220b‧‧‧位置
221‧‧‧端部
221a‧‧‧端部
221b‧‧‧位置
222‧‧‧基底
223‧‧‧邊緣表面
225‧‧‧第一部分
226‧‧‧第二部分
227‧‧‧第一彎曲部
228‧‧‧第二彎曲部
229‧‧‧子集合
230‧‧‧微電子元件
231‧‧‧底部表面
232‧‧‧頂部表面
233‧‧‧側邊表面
240‧‧‧基板
241‧‧‧第一表面
243‧‧‧接點
250‧‧‧囊封
251‧‧‧主要表面
270‧‧‧強化的介電層
271‧‧‧主要表面
272‧‧‧下方區域
273‧‧‧突出區域

Claims (21)

  1. 一種構件，其包括：大致上平坦元件，其具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面，所述大致上平坦元件在所述第一表面處具有多個接點；強化的介電層，其覆於所述大致上平坦元件的所述第一表面上；囊封，其覆於所述強化的介電層上，所述囊封具有背對所述大致上平坦元件的所述第一表面的主要表面；以及多個導線接合，每一個導線接合皆具有與所述多個接點的其中一個接點連結的基底以及在所述囊封的所述主要表面處之遠離所述基底的端部，所述導線接合具有在所述強化的介電層的至少一部分內延伸的第一部分和在所述囊封內延伸的第二部分，所述導線接合中的至少一些的所述第一部分具有以所述第一方向和所述第二方向中的至少一者改變各自導線接合的延伸方向的彎曲部，其中所述強化的介電層具有圍繞所述多個導線接合的各自導線接合的突出區域，與所述強化的介電層在所述突出區域的鄰近突出區域之間的部分從所述大致上平坦元件的所述第一表面延伸相比，所述突出區域延伸至還要高的尖峰高度，所述突出區域的所述尖峰高度與在所述強化的介電層和所述導線接合的個別導線接合之間的接觸點重合。
  2. 如申請專利範圍第1項所述的構件，其中所述構件包括微電子封裝，所述微電子封裝進一步包括具有相反面對的頂部表面和底部表面的微電子元件，所述底部表面面對所述大致上平坦元件的所述第一表面並與其 機械耦合，並且其中所述囊封的所述主要表面覆於所述微電子元件的所述頂部表面上。
  3. 如申請專利範圍第2項所述的構件，其中所述導線接合中的所述至少一些的子集合的所述端部覆於所述微電子元件的所述頂部表面上。
  4. 如申請專利範圍第1項所述的構件，其中所述導線接合的所述基底在其相鄰基底之間界定第一最小間距，並且所述導線接合的所述端部在其相鄰端部之間界定第二最小間距，所述第二最小間距大於所述第一最小間距。
  5. 如申請專利範圍第2項所述的構件，其中所述強化的介電層覆於所述微電子元件的所述頂部表面上。
  6. 如申請專利範圍第1項所述的構件，其中所述強化的介電層包括覆於所述大致上平坦元件的所述第一表面上的第一強化的介電層以及覆於所述第一強化的介電層上且界定所述強化的介電層的上表面的第二強化的介電層。
  7. 如申請專利範圍第1項所述的構件，其中所述導線接合的所述第一部分的所述彎曲部是第一彎曲部，並且所述導線接合中的所述至少一些皆包括以所述第一方向和所述第二方向中的至少一者改變各自導線接合的所述延伸方向的第二彎曲部。
  8. 如申請專利範圍第7項所述的構件，其中所述導線接合的所述第二彎曲部中的至少一些是被設置在所述強化的介電層內。
  9. 如申請專利範圍第1項所述的構件，其中所述強化的介電層是被配置以在垂直於所述第一方向和所述第二方向的第三方向上對所述導線接合 的所述端部施加力時，在所述第三方向上保持所述導線接合的所述端部的位置。
  10. 如申請專利範圍第2項所述的構件，進一步包括與所述導線接合的對應導線接合連結的多個上方端子，所述上方端子在所述囊封的所述主要表面處並且被配置以與所述微電子封裝外部的構件的傳導元件電性連接。
  11. 一種微電子組件，其包括如申請專利範圍第2項所述的構件，所述微電子組件進一步包括具有端子的第二構件，所述導線接合的所述端部電性連接至所述端子。
  12. 一種系統，其包括如申請專利範圍第2項所述的構件和電性連接至所述微電子封裝的一或多個其他電子構件。
  13. 如申請專利範圍第12項所述的系統，進一步包括外殼，所述微電子封裝和所述一或多個其他電子構件與所述外殼組裝。
  14. 一種微電子封裝，其包括：大致上平坦元件，其具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面，所述大致上平坦元件在所述第一表面處具有多個接點；強化的介電層，其覆於所述大致上平坦元件的所述第一表面上；囊封，其覆於所述強化的介電層上，所述囊封具有背對所述大致上平坦元件的所述第一表面的主要表面；微電子元件，其具有相反面對的頂部表面和底部表面，所述底部表面面對所述大致上平坦元件的所述第一表面並與其機械耦合，所述囊封的所述主要表面覆於所述微電子元件的所述頂部表面上；以及 多個導線接合，每一個導線接合皆具有與所述多個接點的其中一個接點連結的基底以及在所述囊封的所述主要表面處之遠離所述基底的端部，所述導線接合具有在所述強化的介電層的至少一部分內延伸的第一部分和在所述囊封內延伸的第二部分，所述導線接合中的至少一些的所述第一部分具有以所述第一方向和所述第二方向中的至少一者改變各自導線接合的延伸方向的彎曲部，其中，與所述微電子元件從所述大致上平坦元件的所述第一表面延伸相比，所述強化的介電層延伸至還要高的尖峰高度。
  15. 如申請專利範圍第14項所述的微電子封裝，其中所述導線接合中的所述至少一些的子集合的所述端部覆於所述微電子元件的所述頂部表面上。
  16. 如申請專利範圍第14項所述的微電子封裝，其中所述導線接合的所述第一部分的所述彎曲部是第一彎曲部，並且所述導線接合中的所述至少一些皆包括以所述第一方向和所述第二方向中的至少一者改變各自導線接合的所述延伸方向的第二彎曲部。
  17. 一種形成構件的方法，其包括：提供大致上平坦元件，其具有在橫向的第一方向和第二方向上延伸的相反面對的第一表面和第二表面，所述大致上平坦元件在所述第一表面處具有多個接點；形成多個導線接合，每一個導線接合皆具有與所述多個接點的其中一個接點連結的基底以及遠離於所述基底的端部，所述導線接合中的至少一些的第一部分具有以所述第一方向和所述第二方向中的至少一者改變各自 導線接合的延伸方向的彎曲部；形成強化的介電層，其覆於所述大致上平坦元件的所述第一表面上，所述導線接合的所述第一部分在所述強化的介電層的至少一部分內延伸，所述強化的介電層具有圍繞所述多個導線接合的各自導線接合的突出區域，與所述強化的介電層在所述突出區域的鄰近突出區域之間的部分從所述大致上平坦元件的所述第一表面延伸相比，所述突出區域延伸至還要高的尖峰高度，所述突出區域的所述尖峰高度與在所述強化的介電層和所述導線接合的個別導線接合之間的接觸點重合；使囊封模流(flowing)在所述強化的介電層和模製膜的下表面之間，所述導線接合的端部延伸至所述模製膜中，所述囊封具有的主要表面背對所述大致上平坦元件的所述第一表面，所述導線接合具有的第二部分在所述囊封內延伸；以及從所述囊封移除所述模製膜，所述導線接合的所述端部是在所述囊封的所述主要表面處。
  18. 如申請專利範圍第17項所述的方法，其中所述構件包括微電子封裝，所述微電子封裝進一步包括具有相反面對的頂部表面和底部表面的微電子元件，所述底部表面面對所述大致上平坦元件的所述第一表面並與其機械耦合，並且其中所述囊封的所述主要表面覆於所述微電子元件的所述頂部表面上。
  19. 如申請專利範圍第17項所述的方法，其中在所述囊封的所述模流之前，所述突出區域向上芯吸(wick up)所述導線接合並且達到它們各自的尖峰高度。
  20. 如申請專利範圍第19項所述的方法，其中所述突出區域的所述尖峰高度並未達到所述導線接合的所述端部。
  21. 如申請專利範圍第17項所述的方法，其進一步包括在所述囊封的所述模流之前，沉積所述模製膜而覆於所述強化的介電層上，所述導線接合的所述端部延伸至所述模製膜中。
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