TW201733062A - 具有多列引線框互連的覆晶堆疊 - Google Patents

具有多列引線框互連的覆晶堆疊 Download PDF

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Publication number
TW201733062A
TW201733062A TW105138398A TW105138398A TW201733062A TW 201733062 A TW201733062 A TW 201733062A TW 105138398 A TW105138398 A TW 105138398A TW 105138398 A TW105138398 A TW 105138398A TW 201733062 A TW201733062 A TW 201733062A
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package
microelectronic
contacts
stacked
component
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TW105138398A
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English (en)
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賈維爾Ａ 迪拉克魯茲
貝爾格森 哈巴
圖三 于
拉傑許 卡特卡爾
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英帆薩斯公司
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Publication of TW201733062A publication Critical patent/TW201733062A/zh

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Abstract

堆疊式微電子封裝包括多個微電子元件，每一個微電子元件皆具有一承載接點的前表面以及延伸遠離該前表面的多個邊緣表面，以及一接觸一邊緣表面的介電囊封區。該囊封定義該封裝的第一主要表面與第二主要表面以及一介於該些主要表面之間的遠端表面。位在該遠端表面處的封裝接點包含一第一組接點以及一第二組接點，該第一組接點位在比該第二組接點靠近該第一主要表面的位置處，該第二組接點則為在比較靠近該第二主要表面的位置處。該些封裝被配置成用以使得每一個封裝的主要表面被配向在不平行於一基板之主要表面的方向中，該些封裝接點被電氣耦接至該基板表面處的對應接點。該封裝堆疊與配向能夠提供增加的封裝密度。

Description

具有多列引線框互連的覆晶堆疊
本申請案的主要標的和微電子封裝與組件有關，其中，複數個半導體晶片會被相互堆疊於彼此的上方並且利用一支撐元件(例如，一封裝元件或是其它電路平板)而被電氣互連。
半導體晶粒或晶片為扁平的主體，有多個接點被設置在前表面上，它們會被連接至該晶片本身的內部電氣電路系統。半導體晶片通常利用基板來封裝，用以形成具有被電氣連接至該些晶片接點之終端的微電子封裝。該封裝接著可以被連接至測試設備，用以判斷該經封裝的裝置是否符合所希望的效能標準。經過測試之後，該封裝便可以被連接至一較大型的電路，舉例來說，一電子產品(例如，電腦，舉例來說，伺服器以及其它類似物)之中的電路。
微電子封裝會被製造成包含被鑲嵌在引線框上的多個半導體晶片。此些封裝能夠被併入於一較大型的組件之中，通常會變成被耦接至一電路平板的表面鑲嵌裝置。為節省空間，特定的習知設計會在一封裝裡面具有堆疊的多個微電子元件或是半導體晶片。這雖然可以讓該封裝在一基板上所佔用的表面積小於該堆疊之中的該些晶片的總表面積；然而， 習知的堆疊封裝卻具有複雜性、成本、厚度、以及可測試性等方面的缺點。
除了上面的進步之外，本技術領域仍需要改良堆疊封裝，尤其是，併入用於特定類型記憶體(舉例來說，快閃記憶體)之多個晶片的堆疊晶片封裝。此些封裝必須非常可靠、很薄、具有可測試性、並且製造成本低廉。
根據本發明的一項觀點，一種堆疊式微電子組件會包括複數個堆疊式囊封微電子封裝。每一個囊封微電子封裝可以包括一微電子元件，其具有一定義一平面的前表面以及延伸遠離該前表面之該平面的複數個邊緣表面，該微電子元件在該前表面具有複數個晶片接點。每一個封裝皆具有複數個遠端表面以及一囊封區，該囊封區會接觸該微電子元件的至少一邊緣表面並且在第一方向中延伸遠離該至少一邊緣表面抵達該些遠端表面中的一對應的遠端表面。該囊封區具有一主要表面，其實質上平行於該微電子元件的平面。複數個導電封裝接點會被設置成相鄰於由該第一主要表面所定義的第一平面以及複數個第二導電封裝接點會被設置成相鄰於一第二平面，該第二平面平行於該第一平面並且與其移位。該些第一封裝接點以及該些第二封裝接點被設置在該些遠端表面中的單一遠端表面處，並且該些晶片接點會電氣耦接該些封裝接點。該複數個微電子封裝會在該堆疊式組件之中被相互堆疊於彼此的上方，俾使得在該複數個微電子封裝中的每一個微電子封裝之中的微電子元件的平面會彼此平行。
根據一或更多項特定觀點，在該堆疊式組件之中的每一個封裝的該些第一封裝接點以及該些第二封裝接點面向並且電氣耦接位於該堆 疊式組件的每一個封裝的囊封區外面的一基板的一主要表面處的一組對應的基板接點，其中，該基板的該主要表面被配向成不平行於(舉例來說，垂直於或是傾斜於)該堆疊式組件之中的該些微電子元件的該些平面。
該些封裝被堆疊成使得每一個次高封裝的該第一主要表面會面向與其相鄰的次低封裝的第二主要表面。根據一特定實施例，複數對第一封裝接點以及第二封裝接點彼此對齊並且電氣耦接，每一對皆包括每一個次高封裝的該第一封裝接點以及與其對齊並且電氣耦接的次低封裝的第二封裝接點。
於另一範例中，該些基板接點包括複數組基板接點，並且每一組皆包括複數個第一基板接點，它們透過一導電的黏接材料接合該些微電子封裝中的唯一一個微電子封裝的第一封裝接點。複數個第二基板接點則會透過一導電的黏接材料接合該唯一一個微電子封裝的第二封裝接點。
於一實施例中，每一個封裝中的該些第一封裝接點以及該些第二封裝接點中的每一個封裝接點分別為一共同引線框的一第一引線框元件的一部分或是一第二引線框元件的一部分。該些第二引線框元件有多個第一部分交錯於相鄰的多個第一引線框元件之間，其中，該些第二封裝接點遠離該些第一部分並且遠離該些第一引線框元件。該些封裝中的至少其中一者的第二引線框元件可以在該些第一部分與該些第二封裝接點之間有彎折。於一實施例中，該些封裝中的至少其中一者的該共同引線框進一步包括一晶粒附接墊，其中，該微電子元件有一面被黏接至該晶粒附接墊。
於一實施例中，該些封裝中的至少其中一者包含一第一微電子元件，該第一微電子元件的該面被黏接至該晶粒附接墊的一第一表面； 並且包含一第二微電子元件，該第二微電子元件的該面被黏接至該晶粒附接墊中和該第一表面反向的第二表面。
於一實施例中，至少一個封裝包含複數個第一堆疊式微電子元件，其包含該第一微電子元件，每一個第一堆疊式微電子元件疊置在該第一表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點；並且包含複數個第二堆疊式微電子元件，其包含該第二微電子元件，每一個第二堆疊式微電子元件疊置在該第二表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點。
於一實施例中，該堆疊式微電子組件可以進一步包括第三封裝接點，其中，該些第一封裝接點、第二封裝接點、以及第三封裝接點分別為第一引線框元件的一部分、第二引線框元件的一部分、以及第三引線框元件的一部分，其中，緊密相鄰的封裝接點在正交於該封裝的主要表面的方向中彼此分隔，並且該些第一封裝接點在該正交方向中與該些第三封裝接點分隔的距離會比與該些第二封裝接點分隔的距離更遠。
於一實施例中，該些微電子封裝中的每一個微電子封裝皆有由該些第一封裝接點與該些第二封裝接點所組成的相同排列，其中，該些封裝包括：多個第一封裝，每一個第一封裝皆有第一配向；以及多個第二封裝，其具有和該第一配向反向的第二配向，其中，該些第一封裝中的至少一部分於該些堆疊式封裝中被堆疊成緊密相鄰於該些第二封裝中的至少一部分。
根據本發明的一項觀點，一種囊封微電子封裝包括一微電子元件，其具有一定義一平面的前表面、延伸遠離該前表面之該平面的複數 個邊緣表面、以及位於該前表面的複數個晶片接點。該封裝可以有複數個遠端表面以及一囊封區，該囊封區會接觸該微電子元件的至少一邊緣表面並且延伸遠離該至少一邊緣表面抵達該些遠端表面中的一對應的遠端表面，並且該囊封區具有反向相向的第一主要表面與第二主要表面，每一個主要表面至少實質上平行於該微電子元件的該平面。複數個第一導電封裝接點可以被設置成相鄰於由該第一主要表面所定義的第一平面以及複數個第二導電封裝接點被設置成相鄰於一由該第二主要表面所定義的平面，該些第一封裝接點以及該些第二封裝接點被設置在該些遠端表面中的單一遠端表面處，該些晶片接點電氣耦接該些封裝接點。
於一實施例中，每一個封裝中的該些第一封裝接點以及該些第二封裝接點中的每一個封裝接點分別為一共同引線框的一第一引線框元件的一部分或是一第二引線框元件的一部分，該些第二引線框元件有多個第一部分交錯於相鄰的多個第一引線框元件之間，該些第二封裝接點遠離該些第一部分並且遠離該些第一引線框元件。
於一實施例中，該些封裝中的至少其中一者的第二引線框元件可以在該些第一部分與該些第二封裝接點之間有彎折。於一實施例中，該共同引線框可以進一步包括一晶粒附接墊，其中，該微電子元件有一面被黏接至該晶粒附接墊。
於一實施例中，該微電子元件係一第一微電子元件，該第一微電子元件的該面面向該晶粒附接墊的一第一表面，該封裝進一步包括一第二微電子元件，該第二微電子元件的該面面向該晶粒附接墊中與該第一表面反向的第二表面。
於一實施例中，該微電子元件可以包括第一微電子元件以及第二微電子元件，該些第一微電子元件以及第二微電子元件的該些面疊置在該晶粒附接墊的一第一表面上方並且機械性耦接該第一表面。
於一實施例中，該微電子元件可以包括複數個該些第一微電子元件，它們被堆疊並且疊置在該第一表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點；並且包括複數個該些第二微電子元件，它們被堆疊並且疊置在該第二表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點。
於一實施例中，該微電子封裝會有第三封裝接點，其中，該些第一封裝接點、第二封裝接點、以及第三封裝接點分別為第一引線框元件的末端部分、第二引線框元件的末端部分、以及第三引線框元件的末端部分，其中，緊密相鄰的末端部分在正交於該封裝的主要表面的方向中彼此分隔，並且該些第一封裝接點在該正交方向中與該些第三封裝接點分隔的距離會比與該些第二封裝接點分隔的距離更遠。
於一實施例中，該複數個第一堆疊式微電子元件會被堆疊成使得每一個第一堆疊式微電子元件的一邊緣表面在正交於該邊緣表面的方向中偏離緊密位於此第一堆疊式微電子元件下方的每一個第一堆疊式微電子元件的邊緣表面，以及該複數個第一堆疊式微電子元件會透過焊線電氣耦接該些第一封裝接點以及該些第二封裝接點。
於一實施例中，該些第一封裝接點以及該些第二封裝接點延伸超越該囊封區的一表面不超過25微米，該封裝在靠近該囊封的該遠端表面的位置處進一步包括一被設置在第一引線框元件以及至少一部分的該些 第二引線框元件之間的順從材料。
於一實施例中，該些第二引線框元件突出超越該囊封區的一表面超過50微米。
100‧‧‧微電子組件
108‧‧‧堆疊式微電子子組件或是微電子封裝
108B‧‧‧堆疊式微電子子組件或是微電子封裝
108-1‧‧‧堆疊式微電子子組件或是微電子封裝
108-2‧‧‧堆疊式微電子子組件或是微電子封裝
109‧‧‧分隔體
110‧‧‧封裝堆疊
110A‧‧‧封裝堆疊
110B‧‧‧封裝堆疊
112‧‧‧微電子元件
114‧‧‧前表面
116-1‧‧‧平面
116-2‧‧‧平面
116-X‧‧‧平面
118‧‧‧接點
120‧‧‧邊緣表面
122‧‧‧後表面
126-1‧‧‧平面
126-2‧‧‧平面
127‧‧‧第一封裝接點
128‧‧‧焊線
129‧‧‧第二封裝接點
130‧‧‧遠端表面
132‧‧‧第一主要表面
134‧‧‧第二主要表面
135‧‧‧介電區
136‧‧‧平面
137‧‧‧引線框元件
138‧‧‧基板
140‧‧‧基板接點
142‧‧‧主要表面
144‧‧‧導電質塊
146‧‧‧黏著劑
148‧‧‧銳角
152‧‧‧晶粒附接墊
154‧‧‧固鎖特徵元件
156‧‧‧固鎖特徵元件
200‧‧‧微電子組件
208‧‧‧封裝
212‧‧‧高度
227‧‧‧第一封裝接點
229‧‧‧第二封裝接點
247‧‧‧互連平面
248‧‧‧銳角
329‧‧‧引線框元件
350‧‧‧微電子組件
356‧‧‧平面
358‧‧‧封裝
360‧‧‧邊緣表面
367‧‧‧第一封裝接點
369‧‧‧第二封裝接點
408‧‧‧封裝
411‧‧‧第一微電子元件堆疊
421‧‧‧第二微電子元件堆疊
427‧‧‧第一封裝接點
429‧‧‧第二封裝接點
431‧‧‧第三封裝接點
510‧‧‧封裝堆疊
518‧‧‧空間
520‧‧‧構件
600‧‧‧微電子組件
608‧‧‧封裝
627‧‧‧第一封裝接點
629‧‧‧第二封裝接點
630‧‧‧遠端表面
637-1‧‧‧第一引線框元件
637-2‧‧‧第二引線框元件
640‧‧‧順從特徵元件
圖1所示的係根據本發明一實施例的一微電子組件的俯視立體圖以及邊緣表面。
圖2所示的係根據本發明一實施例的一微電子組件的仰視立體圖以及邊緣表面。
圖3所示的係根據本發明一實施例的一微電子組件的側視圖。
圖4所示的係根據本發明一實施例的一微電子封裝的部分放大側視圖。
圖5所示的係根據本發明一實施例的一處理中結構(in-process structure)的俯視平面圖。
圖6A所示的係根據本發明一實施例的一微電子組件的仰視圖。
圖6B所示的係根據在圖6A中所看見之實施例的變化例的一微電子組件的仰視圖。
圖6C所示的係根據在圖6B中所看見之變化例的微電子組件的對應側視圖。
圖6D所示的係根據在圖6A中所看見之實施例的另一變化例的一微電子組件的仰視圖。
圖7所示的係根據本發明一實施例的一微電子組件的仰視圖。
圖8所示的係根據本發明一實施例的一微電子組件的側視圖。
圖9所示的係根據本發明一實施例的一微電子封裝的側視圖。
圖10所示的係根據本發明一實施例的一微電子封裝的側視圖。
圖11所示的係根據本發明一實施例的一微電子組件的仰視圖。
圖12所示的係根據本發明一實施例的一微電子封裝的側視圖。
圖13所示的係一微電子組件的仰視圖，其併入如圖12中所示之根據本發明一實施例的複數個封裝。
圖14所示的係根據本發明一實施例的一微電子組件的側視圖。
圖15所示的係根據本發明一實施例的一微電子封裝的側視圖。
圖16所示的係根據本發明一實施例的一微電子組件的側視圖。
如本揭示內容之中參考一介電區或是一構件(舉例來說，電路結構、中介片、微電子元件、電容器、電壓調節器、電路平板、基板等)的一介電結構的用法，一導電元件「位於該介電區或是構件的一表面」係表示當該表面沒有被任何其它元件覆蓋或是與任何其它元件組裝時，該導電元件可以接觸一在垂直於該介電區之表面的方向中從該介電區或是構件外面移動的理論點。因此，一位於一介電區的一表面的終端或是其它導體元件可以從此表面處突出；可以與此表面齊平；或者，可以相對於此表面凹陷於該介電區之中的一孔洞或是凹部之中。
如圖1至2的立體圖以及圖3的對應側視圖之中所示，一微電子組件100包含一封裝堆疊110，而該封裝堆疊110包含複數個堆疊式微電子子組件或是微電子封裝108，每一個微電子封裝皆包含一或更多個微電子元件112，至少其中一個微電子元件112為一半導體晶片。本文中所揭示 或是引用的微電子組件100以及其它微電子組件能夠提供增強的儲存密度，其特別有利於使用在資料中心的系統之中，其中，該些系統包含企業用系統、政府用系統、託管系統(hosted system)、搜尋引擎系統、雲端儲存體、或是其它大型資料中心。
參考根據在圖4中所看見之實施例的微電子封裝108，舉例來說，每一個微電子元件112能夠被排列在一由多個雷同微電子元件所組成的堆疊之中。於一範例中，該些微電子元件之中的每一者可以包含一具有一或更多個記憶體儲存陣列的半導體晶片，其可以包含一特定的記憶體類型，例如，非揮發性記憶體。非揮發性記憶體能夠以各式各樣的技術來施行，某些技術包含併入浮動閘(floating gate)的記憶體胞體，例如，快閃記憶體；而其它技術則包含以磁極為基礎來操作的記憶體胞體。快閃記憶體晶片目前普遍用來當作固態儲存體，用以充當計算裝置與行動裝置的磁性固定式碟片機(fixed disk drive)的替代例。快閃記憶體晶片同樣經常使用在可攜並且可輕易替換的記憶碟或記憶卡，例如，通用串列匯流排(Universal Serial Bus，USB)記憶碟以及記憶卡(例如，安全數位(Secure Digital，SD)卡、microSD卡(SD-3C的商標或註冊商標)、小型快閃(Compact Flash，CF)卡、以及類似物)。在快閃記憶體晶片之中通常具有NAND或NOR快閃類型裝置，NAND類型裝置比較常見。半導體晶片的其它範例為一或更多個DRAM、NOR、微處理器、控制器晶粒等，或是它們的組合。每一個半導體晶片皆可以各種半導體材料中的其中一種來施行，例如，矽、鍺、砷化鎵、或是一或更多種其它III-V族半導體化合物或是II-VI族半導體化合物等。在一或更多個微電子封裝108之中以及在一或更多個封裝堆疊110之中的微電子元 件112可以為如上面所述的不同晶片功能的組合以及為如上面所述的各種半導體材料的組合。於一實施例中，一微電子元件可以以比任何其它功能更多數量的主動式裝置來提供記憶體儲存陣列功能。於一實施例中，由玻璃、矽、或是其它適當材料所製成的虛擬分隔體會被定位成相鄰於一微電子封裝或子組件之中的微電子元件或是被定位在該些微電子元件之間。
每一個微電子元件皆能夠為一半導體晶片，其具有一前表面114，用以定義複數個平面116-1、116-2、…等中的一個別平面116-x。每一個半導體晶片112在其前表面有複數個接點118以及一延伸遠離此晶片之前表面的邊緣表面120。每一個晶片還具有一與其前表面114反向的後表面122。在一封裝裡面的相鄰微電子元件的前表面與後表面可以利用一黏著劑(圖中並未顯示)被黏接在一起。於一實施例中，該黏著劑可以為或是包含一或更多層環氧樹脂、彈性體、聚醯亞胺、或是其它聚合材料。於某些情況中，作為該些微電子元件中的一或更多者上方的保形介電塗層的材料亦可以充當一黏著劑。於一實施例中，此保形介電塗層能夠為一聚亞二甲苯(polyxylylene)材料，例如，通常稱為「聚對二甲苯(parylene)」。聚對二甲苯亦能夠作為相鄰微電子元件之間的晶粒附接黏著劑。於一實施例中，一或更多個微電子元件可以被封裝成一扇出型(fan-out)晶圓級封裝。
位於該封裝108之中的一或更多個微電子元件112上的晶片接點118電氣耦接被設置在該封裝周圍的封裝接點。每一個封裝108的封裝接點包含第一封裝接點127以及第二封裝接點129。複數個第一封裝接點127被設置成相鄰於由該封裝的一第一主要表面132所定義的一平面126-1，其實質上平行於該一或更多個微電子元件112的平面116-x。同一個封裝108 的複數個第二封裝接點129被設置成相鄰於由該封裝的一第二主要表面134所定義的一平面126-2，其實質上平行於該一或更多個微電子元件112的平面116-x。
於圖4中所示的實施例中，該些封裝接點127、129中的每一者被設置在個別封裝108的單一遠端表面130處，並且該單一遠端表面係由每一個封裝接點127、129之終止位置所在(落在一製造公差內)的一垂直配向的平面所定義。或者，封裝接點127可以在一平行於平面126-1的方向中延伸至比封裝接點129更遠的地方；或者，封裝接點129可以在一平行於平面126-1的方向中延伸至比封裝接點127更遠的地方。舉例來說，該些封裝接點可以突出超越該遠端表面130至50微米或更大的距離。此些特徵元件中的一或更多者可以幫助在該封裝以及一電氣耦接該封裝的基板之間提供一種特定的互連排列，例如，下面參考圖8至9所述。
於一範例中，該些第一封裝接點127以及第二封裝接點129為從單一共同引線框中切斷出來的獨特的引線框元件的一部分。該些第一封裝接點能夠為延伸平行於該封裝的主要表面132的筆直引線框元件。該些第二封裝接點能夠為相對於該封裝的主要表面132為彎折的其它引線框元件的一部分，俾使得該引線框元件的至少一部分延伸在一和該封裝的該主要表面132形成某個角度的方向之中。於某些情況中，該些第二封裝接點為一扁平S形的引線框元件137的終止末端，如在圖4的側視圖中所見。該些引線框元件能夠在被用來將該封裝之中的微電子元件電氣耦接該些引線框元件的其它製程之前或之後被形成。每一個封裝之中的該些一或更多個微電子元件能夠被支撐在一晶粒附接墊152上，提供該些封裝接點的同 一個引線框的一部分。舉例來說，在一堆疊的最下方微電子元件112的一後表面122會被附接至該引線框晶粒附接墊152的向內主要表面。
一介電區135可以疊置在該封裝的前表面與邊緣表面上方或是接觸該封裝的前表面與邊緣表面，並且具有一遠端表面130，該遠端表面130會和與該遠端表面最靠近的該微電子元件的邊緣表面120隔開。於特定的情況中，該介電區能夠從該微電子元件的二或更多個邊緣表面處延伸至與該些邊緣表面隔開的該封裝的對應遠端表面。每一個微電子元件皆可以有此介電區疊置在其邊緣表面的上方。於一範例中，該介電區135可以為或是包含一模鑄介電區。於一範例中，該介電區可以包括一聚合介電材料；或者，其中有填充物的聚合介電材料，該填充物的熱膨脹係數低於該聚合材料。於某些範例中，該填充物可以包含由一無機材料(例如，玻璃、石英、陶瓷、或是半導體材料、以及其它無機材料)製成的顆粒、薄片、或是網狀物或支架。
圖4進一步圖解固鎖特徵元件154、156，它們能夠為該晶粒附接墊152以及該些引線框元件137的蝕除部分，此些特徵元件用於避免來自該封裝外面作用在該晶粒附接墊152以及該些引線框元件137上的作用力鬆開、拉曳、或是拉開該些引線框元件137而脫離該囊封區。
同一個封裝的所有第一封裝接點以及第二封裝接點會位於該介電區135的相同遠端表面130處。該些封裝接點能夠為朝更靠近該封裝之中的該些微電子元件的邊緣表面120的位置向內延伸的引線框元件137的一部分。如在圖4至5中所見，每一個封裝接點會經由一焊線128電氣耦接位於一微電子元件的一前表面的晶片接點118。舉例來說，焊線能夠藉由 加熱從一毛細管焊接工具的外露尖端處突出的受擠壓電線的末端而形成，用以在該電線的該尖端處形成一熔融的金屬球，並且在熱與壓力的作用下將該球體焊接至該晶片接點。而後，該焊接工具的尖端接著會被移動至一引線框元件137之表面的一位置處，該焊接工具會於該處針焊該電線的一區段並且接著切斷該電線的已焊接端，以便完成該過程。於其中一變化例中會運用一種反向線焊技術，其中，該焊線會先被球焊至該引線框元件並且接著被針焊至該個別微電子元件的晶片接點。於某些情況中，相較於在該些微電子元件上有焊球的焊線128，反向線焊可以經過選擇，用以提供具有低迴圈高度的焊線。
參考圖4，一個以上的微電子元件會被提供在一獨特的微電子封裝108之中。在同一個封裝之中提供複數個微電子元件的優點係可以提高該些微電子元件以及一在其主要表面142有有限的互連面積的基板138之間的互連密度。在每一個封裝中併入兩個微電子元件的微電子封裝108能夠以被提供在介接該基板138的互連介面處的封裝接點127、129之中的互連間距的一半的有效間距來互連一基板138。於一特定的實施例中，當一封裝108之中的微電子元件為於其中具有記憶體儲存陣列的微電子元件時，位於該封裝之中的所有微電子元件上的對應晶片接點可以耦接該封裝的單一封裝接點。除了被指派為用於接收單獨被路由傳送至該些微電子元件中其中一者的訊號(舉例來說，晶片選擇輸入訊號)的晶片接點之外，這同樣能夠適用於每一個微電子元件的大部分或是所有晶片接點。這同樣適用於提供非揮發性記憶體儲存陣列功能的微電子元件，此非揮發性記憶體儲存陣列係由該微電子元件之中比該微電子元件中的任何其它功能更多數量 的主動式裝置來施行。
在每一個微電子封裝之中被相互堆疊於彼此上方的微電子元件的數量的範圍會從少量(例如，一個或兩個)至較大的數量(舉例來說，八個、十六個、或是更多個)。於圖3至4中所描繪的範例中，四個微電子元件會被堆疊在單一封裝裡面並且電氣耦接此封裝的該些封裝接點。於雷同於圖4中所示之範例的另一範例中(圖中並未顯示)，八個微電子元件會被堆疊在單一封裝裡面並且電氣耦接此封裝的封裝接點127、129。
於圖4中所示之結構的變化例中，其它方式會被提供用以電氣耦接該些微電子元件以及該些引線框元件。舉例來說，一保形導電材料會被沉積用以接觸該堆疊之中的一或更多個微電子元件的晶片接點118、前表面114、以及邊緣表面120，以便形成從該些晶片接點118處延伸至該些引線框元件137的線路。於一範例中，該導電材料能夠藉由電鍍來沉積。於一特定的範例中，該導電材料能夠為如美國專利案第8,178,978號之中所揭示的導電聚合材料或是導電油墨，本文以引用的方式將其揭示內容併入，並且該些導電材料線路能夠如該案之中所揭示般地被形成。
如在圖5中所看見的處理中結構之中的部分顯示，在每一個封裝108的製造期間，該些焊線128會在該些引線框元件為一引線框的不可分割部分時被形成，而後，一囊封劑會被塗敷至該處理中結構，並且該引線框會在虛線所示處被切斷，用以將該些獨特的引線框元件切成多個分離的引線框指狀部，在它們的末端處會有封裝接點。
再次參考圖4，封裝108之中的每一個該些微電子元件的所有前表面皆被配向於相同的方向中。於圖4中所示實施例的變化例中，該 封裝之中的一或更多個該些微電子元件的前表面能夠被配向於相反的方向中。於一特定的實施例中，舉例來說，如在圖12中所見，彼此相鄰的至少兩個該些微電子元件的前表面可以彼此相向或者彼此面向相反的方向。
如圖3中的進一步顯示，一堆疊式微電子組件100包括複數個封裝108，它們具有第一封裝接點127以及第二封裝接點129，該些第一封裝接點127以及第二封裝接點129經由由黏接材料所製成的導電質塊144被電氣耦接至一基板138的一表面142處的基板接點140。該基板138可以為一介電元件或是其它基板並且可以於其上有一或多層介電材料以及一或多個導電層。該基板138能夠由各種材料形成，其可以包含或不包含聚合組成物，並且可以包含或不包含無機組成物。或者，該基板可以完全為或者基本上為聚合物；或者，可以完全為或者基本上為無機物。於各種非限制性的範例中，該支撐元件能夠由一合成材料所形成，例如，玻璃強化的環氧樹脂(舉例來說，FR-4)、半導體材料(舉例來說，矽或砷化鎵)、或是玻璃或陶瓷材料。
該基板能夠為在背向該些微電子組件的下方表面上有接點的基板，該些接點被配置成用以透過平台格柵陣列(Lang Grid Array，LGA)、球柵陣列(Ball Grid Array，BGA)、或是其它技術表面鑲嵌至另一構件，該另一構件其能夠為一插卡、托盤、主機板等。於另一範例中，該基板能夠為一插卡構件，在其頂端表面和底部表面有滑動接點，例如，用以插入至一插座之中。於又一範例中，諸如通用串列匯流排(USB)控制器或是其它通訊控制器的另一構件會被鑲嵌至該基板並且電氣耦接該微電子組件，此構件會幫助或是控制該微電子組件與一系統之間的資訊流動。
如圖3中所示，該些平行的平面116-x可以被配向在正交於該基板主要表面之平面136的方向中，並且該基板的該主要表面142面向每一個晶片的的邊緣表面120。一黏著劑146(其可能為一底部填充膠)可以被塗敷包圍位於該些引線框互連與該些基板接點之間的電氣連接線，並且該黏著劑可以有機械性強化或勁化此些電氣連接線的功能並且可以幫助該些電氣連接線耐受因為該些晶片微電子元件112與該支撐元件138之間的差異熱膨脹而造成的應力。
於圖1至4中所示的微電子組件的變化例中，複數個該些封裝堆疊110會被鑲嵌並且被電氣連接至該些基板接點140，每一個封裝堆疊110皆包括複數個堆疊式微電子封裝，例如，在2015年10月15日提申的美國專利申請案第14/883,864號的圖2之中所示，本文以引用的方式將其揭示內容併入。在該正交方向中介於個別相鄰封裝堆疊108的主要表面之間的距離會定義一間隙，於某些情況中，該間隙可以為100微米，或者，大小範圍可以從100微米至200微米，或者，可以具有更大的數值。於某些情況中，此間隙可以大如1毫米。於此間隙內會提供一黏著劑及/或其它元件，於某些情況中，該些其它元件可以包含一如下面進一步說明的散熱片、或是被動式構件、硬體、或是其它構件，其可以電氣互連或是不電氣互連一或更多個該些封裝堆疊110。
如在圖6A中進一步看見，在朝封裝108的底部表面看去的一封裝堆疊110的視圖之中，該些底部表面被配置成用以耦接該些基板接點，在圖中會看見於一封裝堆疊110之中的微電子封裝108的第一封裝接點127相鄰於被配向在第一方向之中的一封裝第一主要表面132，而該些微電 子封裝108的第二封裝接點129則相鄰於被配向在和該第一方向反向的方向之中的一封裝第二主要表面134。在圖中看見該些第二封裝接點129對齊並且相鄰於該些第一封裝接點中的對應封裝接點，其中，緊密相鄰的封裝108中的對齊且相鄰的第一封裝接點與第二封裝接點可能會接觸或者可能非常接近於接觸。因此，該些封裝會被堆疊成使得每一個次高封裝的第一主要表面132會面向與其相鄰的次低封裝的第二主要表面134，其中，每一個次高封裝的第一封裝接點會對齊與其相鄰的次低封裝的第二封裝接點。
如在圖3中進一步看見，緊密相鄰的封裝108中的對齊且相鄰的第一封裝接點與第二封裝接點會電氣耦接同一個基板接點。明確地說，相同的導電質塊144可以接合位在基板主要表面142處的一獨特基板接點140以及其中一個封裝108的一第一封裝接點127以及與此封裝緊密相鄰的另一個封裝108的相鄰第二封裝接點129。
於圖6A的特定排列中，每一個封裝108雖然會與每一個其它封裝完全相同；但是，某些封裝108-1卻會與其它封裝108-2有不同的配向。於圖6A的範例中，每一個封裝108-1會以每一個封裝108-2的配向為基準旋轉180度。
如在圖6B至6C中看見，在上面所述實施例的一變化例中，在封裝堆疊110A中的每一個封裝108-1、108-2彼此會完全相同並且有相同的配向。依此方式，最靠近該封裝堆疊110A之中的相鄰封裝108-2的第一封裝接點127的其中一個封裝108-1的第二封裝接點129彼此不會對齊。此種排列能夠幫助在相鄰封裝108-1、108-2的第一封裝接點127與第二封裝接點129之間形成分離的電氣連接線連接至基板接點140，舉例來說，如在圖 6C中所見。視情況，如在圖6B至C中所見，一分隔體109會被定位在該封裝堆疊中的相鄰封裝108-1、108-2之間，以便在該些第一封裝接點127以及與其最靠近的第二封裝接點129之間提供足夠及/或視情況均勻的間隔。於一特定的實施例中，用以形成該些封裝接點的引線框元件會被彎折或是被放置成用以在相鄰的封裝之間保持該些封裝接點127、129的相對恆定間距。
於根據在圖6D中所見之另一變化例的封裝堆疊110B之中，該些第二封裝接點129會在遠離其中的每一個封裝108B的第二主要表面134的方向中移位。於一範例中，該些引線框元件會被彎折或是被放置成用以形成該些第二封裝接點129使其在高度中和每一個獨特封裝108B的第一封裝接點127有較小的分離距離。於另一範例中，介電區135(舉例來說，每一個封裝108B的囊封區)會被形成具有大於圖6A中所示之範例中的高度。根據圖6D的變化例還能夠藉由在圖6D中所見的相鄰封裝108B的第一封裝接點127與第二封裝接點129之間提供大分離距離而幫助在相鄰封裝108-1、108-2的第一封裝接點127與第二封裝接點129以及該些基板接點140之間形成分離的電氣連接線，舉例來說，如在圖6C中所見。
於在圖7中所見之另一變化例中，每一個封裝雖然和每一個其它封裝有相同的配向；然而，每一個封裝108-2卻會在平行於此封裝的一主要表面132的方向中偏離每一個封裝108-1。於此情況中，位於一給定封裝上的一部分該些第一封裝接點127可能不會對齊位於與其緊密相鄰的封裝上的一部分對應第二封裝接點129。
圖8所示的係根據一特定實施例的微電子組件200，其中， 由其中的每一個封裝208的主要表面134所定義的平面被配向成和由該基板主要表面所定義的平面136形成一銳角148。讓封裝208傾斜於該基板，可以容納和上面在圖1至5中所見的實施例之中相同或不同數量的封裝；但是，從該基板的主要表面142處算起的高度212會較短，其會隨著以角度148的正弦值為基礎的因子而改變。於一特定的範例中，當角度148為45度時，該高度會縮減以該角度的正弦值(sin 45°)為基礎的因子。因此，該高度會縮減至小於原始的高度並且更接近等於該角度的正弦值或是約原始高度的0.7倍的數值。於另一範例中，倘若角度148能夠縮減至30°的話，該高度會縮減以該角度的正弦值(sin 30°)為基礎的因子，縮減至更接近約原始高度的一半的數值。介於該封裝堆疊與該基板之間的額外強化材料(例如，底部填充膠146或是其它結構)可以被提供用以強化在圖8中所見的傾斜微電子組件的機械完整性。圖8雖然表示該些堆疊式微電子元件的前表面面向或是朝基板138的主要表面的平面136傾斜；不過，亦可以傾斜於反向的方向中。
參考圖9，於該傾斜微電子組件的一特定範例中，第一封裝接點227可以在一平行於該封裝主要表面134的方向中從該囊封處延伸至比第二封裝接點229更遠的地方。於此情況中，該些第一封裝接點227以及第二封裝接點229可以終止在和被設置成與該基板主要表面132形成銳角248的一互連平面247相交的多個位置處。於特定的實施例中，該角度248可以具有和角度148相同或不同的度量值。讓位在該封裝中其中一側的封裝接點長於位在該封裝中另一側的封裝接點，該些第一封裝接點以及該些第二封裝接點便能夠定義一平面式互聯介面，有利於互連在圖8中所見的傾斜 微電子組件之中的基板。於另一實施例中，第二封裝接點229可以在一平行於該封裝主要表面134的方向中從該囊封處延伸至比第一封裝接點227更遠的地方。
圖10所示的係引線框元件329的另一變化例，其形成會僅包含單一彎折的第二封裝接點，俾使得該引線框元件會形成一扁平L形，而非如上面所述範例之中的扁平S形。
圖11所示的係一微電子組件350的另一變化例，其中，位於其中每一個封裝358上的相鄰第一封裝接點367以及第二封裝接點369會和平行於該微電子組件的一邊緣表面360的同一平面356相交。在相鄰封裝358上彼此相鄰的封裝接點367、369可以藉由黏接材料144彼此電氣耦接，該黏接材料會將該些封裝接點電氣耦接至一對應的基板接點140，舉例來說，如在圖3中所見。或者，在相鄰封裝358上彼此相鄰的封裝接點367、369可以保持彼此電氣分離，因為分離的黏接質塊144能夠被用來將該些相鄰的封裝接點367、369電氣耦接至分離的基板接點，雷同於在圖8中所見，不同的係該些封裝能夠以垂直方式被配向或者被配向成和該基板的主要表面形成某個角度。
圖12所示的係又一變化例，其中，第一微電子元件堆疊411以及第二微電子元件堆疊421會被附接至位於其中的引線框晶粒附接墊的反向表面，並且微電子元件會電氣耦接第一封裝接點427、第二封裝接點429、以及第三封裝接點431。於此情況中，第一封裝接點427能夠被設置在相鄰於該些第二封裝接點429以及第三封裝接點431之設置位置的平面之間的封裝408的一中央位置處。於一特定的範例中，該些封裝接點會以如 在圖13中所見的方式被排列在該封裝408之面向底部的表面，此排列雷同於上面配合圖6A所述的排列，不同的係，該特定排列包含額外的第三封裝接點431並且該些第一封裝接點被置中設置。於另一實施例中則僅有第一封裝接點427以及第二封裝接點429或第三封裝接點431中的任一者會被形成。
於圖14中所見的一特定變化例中，由一個以上的微電子封裝所組成的獨特堆疊510能夠藉由空間518彼此分離，該空間容納其它元件，例如：散熱片、其它微電子封裝或封裝結構、其它整合式或離散式構件(例如，電阻器、電容器、電感器、或是其它被動式或主動式電子構件)。另一種此類構件520可以疊置在該組件上方並且以電氣方式、機械方式、及/或熱方式被耦接至位於相鄰封裝堆疊510之間的空間裡面的該些構件。
於在圖15至16中所見的其中一變化例中，第一引線框元件637-1以及第二引線框元件637-2會延伸至並且終止於第一封裝接點627以及第二封裝接點629中，它們在製造公差內齊平於該封裝的遠端表面630。於此實施例中，一順從特徵元件640可以被併入於該封裝之中，用以吸收因為該外部基板(舉例來說，圖3中的基板138)與該封裝的該些接點之間的差異熱膨脹而造成的應力。圖16圖解一併入複數個封裝608的微電子組件600，其中，該些封裝接點依照此方式被排列。圖15雖然描繪第一封裝接點627以及第二封裝接點629齊平於遠端表面630；不過，它們亦可以凹陷於該遠端表面630裡面。
雖然沒有在圖式中明確顯示或是在前面特別說明；不過，各種圖式以及各種已述實施例中的元件亦能夠在本發明的額外變化例中被組 合在一起。
108‧‧‧堆疊式微電子子組件或是微電子封裝
110‧‧‧封裝堆疊

Claims (22)

  1. 一種堆疊式微電子組件，其包括：複數個堆疊式囊封微電子封裝，每一個囊封微電子封裝皆包括：一微電子元件，其具有一定義一平面的前表面以及延伸遠離該前表面之該平面的複數個邊緣表面，該微電子元件在該前表面具有複數個晶片接點；每一個封裝皆具有複數個遠端表面以及一囊封區，該囊封區接觸該微電子元件的至少一邊緣表面並且延伸遠離該至少一邊緣表面抵達該些遠端表面中的一對應的遠端表面，該囊封區具有反向相向的第一主要表面與第二主要表面，每一個主要表面實質上平行於該微電子元件的平面；以及複數個第一導電封裝接點被設置成相鄰於由該第一主要表面所定義的第一平面以及複數個第二導電封裝接點被設置成相鄰於一第二平面，該第二平面平行於該第一平面並且與其移位，該些第一封裝接點以及該些第二封裝接點被設置在該些遠端表面中的單一遠端表面處，該些晶片接點會電氣耦接該些封裝接點，該複數個微電子封裝在該堆疊式組件之中被相互堆疊於彼此的上方，俾使得在該複數個微電子封裝中的每一個微電子封裝之中的微電子元件的平面彼此平行。
  2. 根據申請專利範圍第1項的堆疊式微電子組件，其中，在該堆疊式組件之中的每一個封裝的該些第一封裝接點以及該些第二封裝接點面向並且電氣耦接位於該堆疊式組件的每一個封裝的囊封區外部的一基板的一主要表面處對應基板接點，該主要表面被配向成不平行於該堆疊式組件之中的 該些微電子元件的平面。
  3. 根據申請專利範圍第2項的堆疊式微電子組件，其中，該些封裝被堆疊成使得每一個次高封裝的該第一主要表面面向與其相鄰的次低封裝的第二主要表面，其中，複數對第一封裝接點以及第二封裝接點彼此對齊並且電氣耦接，每一對皆包括每一個次高封裝的該第一封裝接點以及與其對齊並且電氣耦接的次低封裝的第二封裝接點。
  4. 根據申請專利範圍第2項的堆疊式微電子組件，其中，該些基板接點包括複數組基板接點，每一組皆包括複數個第一基板接點以及複數個第二基板接點，該複數個第一基板接點透過一導電的黏接材料接合該些微電子封裝中的唯一一個微電子封裝的第一封裝接點，以及該複數個第二基板接點透過一導電的黏接材料接合該唯一一個微電子封裝的第二封裝接點。
  5. 根據申請專利範圍第3項的堆疊式微電子組件，其中，每一個封裝中的該些第一封裝接點以及該些第二封裝接點中的每一個封裝接點分別為一共同引線框的一第一引線框元件的一部分或是一第二引線框元件的一部分，該些第二引線框元件有多個第一部分交錯於相鄰的多個第一引線框元件之間，該些第二封裝接點遠離該些第一部分並且遠離該些第一引線框元件。
  6. 根據申請專利範圍第5項的堆疊式微電子組件，其中，該些封裝中的至少其中一者的第二引線框元件在該些第一部分與該些第二封裝接點之間有彎折。
  7. 根據申請專利範圍第4項的堆疊式微電子組件，其中，該些封裝中的至少其中一者的該共同引線框進一步包括一晶粒附接墊，其中，該微電子 元件有一面被黏接至該晶粒附接墊。
  8. 根據申請專利範圍第7項的堆疊式微電子組件，其中，該些封裝中的至少其中一者包含一第一微電子元件，該第一微電子元件的該面被黏接至該晶粒附接墊的一第一表面；並且包含一第二微電子元件，該第二微電子元件的該面被黏接至該晶粒附接墊中和該第一表面反向的第二表面。
  9. 根據申請專利範圍第8項的堆疊式微電子組件，其中，至少其中一個封裝包含複數個第一堆疊式微電子元件，其包含該第一微電子元件，每一個第一堆疊式微電子元件疊置在該第一表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點；並且包含複數個第二堆疊式微電子元件，其包含該第二微電子元件，每一個第二堆疊式微電子元件疊置在該第二表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點。
  10. 根據申請專利範圍第1項的堆疊式微電子組件，其進一步包括第三封裝接點，其中，該些第一封裝接點、第二封裝接點、以及第三封裝接點分別為第一引線框元件的一部分、第二引線框元件的一部分、以及第三引線框元件的一部分，其中，緊密相鄰的封裝接點在正交於該封裝的主要表面的方向中彼此分隔，並且該些第一封裝接點在該正交方向中與該些第三封裝接點分隔的距離會比與該些第二封裝接點分隔的距離更遠。
  11. 根據申請專利範圍第5項的堆疊式微電子組件，其中，該些封裝包括：多個第一封裝，每一個第一封裝皆有第一配向；以及多個第二封裝，其具有和該第一配向反向的第二配向，其中，該些第一封裝以及該些第二封裝中的每一者具有由其上的第一封裝接點以及第二封裝接點所組成的完 全相同的排列，其中，該些第一封裝中的至少一部分於該些堆疊式封裝中被堆疊成緊密相鄰於該些第二封裝中的至少一部分。
  12. 一種囊封微電子封裝，其包括：一微電子元件，其具有一定義一平面的前表面、延伸遠離該前表面之該平面的複數個邊緣表面、以及位於該前表面的複數個晶片接點；該封裝有複數個遠端表面以及一囊封區，該囊封區會接觸該微電子元件的至少一邊緣表面並且延伸遠離該至少一邊緣表面抵達該些遠端表面中的一對應的遠端表面，該囊封區具有反向相向的第一主要表面與第二主要表面，每一個主要表面至少實質上平行於該微電子元件的該平面；以及複數個第一導電封裝接點被設置成相鄰於由該第一主要表面所定義的第一平面以及複數個第二導電封裝接點被設置成相鄰於一由該第二主要表面所定義的平面，該些第一封裝接點以及該些第二封裝接點被設置在該些遠端表面中的單一遠端表面處，該些晶片接點會電氣耦接該些封裝接點。
  13. 根據申請專利範圍第12項的微電子封裝，其中，每一個封裝中的該些第一封裝接點以及該些第二封裝接點中的每一個封裝接點分別為一共同引線框的一第一引線框元件的一部分或是一第二引線框元件的一部分，該些第二引線框元件有多個第一部分交錯於相鄰的多個第一引線框元件之間，該些第二封裝接點遠離該些第一部分並且遠離該些第一引線框元件。
  14. 根據申請專利範圍第13項的微電子封裝，其中，該些封裝中的至少其中一者的第二引線框元件在該些第一部分與該些第二封裝接點之間有彎折。
  15. 根據申請專利範圍第13項的微電子封裝，其中，該共同引線框進一 步包括一晶粒附接墊，其中，該微電子元件有一面被黏接至該晶粒附接墊。
  16. 根據申請專利範圍第15項的微電子封裝，其中，該微電子元件係一第一微電子元件，該第一微電子元件的該面面向該晶粒附接墊的一第一表面，該封裝進一步包括一第二微電子元件，該第二微電子元件的該面面向該晶粒附接墊中與該第一表面反向的第二表面。
  17. 根據申請專利範圍第15項的微電子封裝，其中，該微電子元件包括第一微電子元件以及第二微電子元件，該些第一微電子元件以及第二微電子元件的該些面疊置在該晶粒附接墊的一第一表面上方並且機械性耦接該第一表面。
  18. 根據申請專利範圍第16項的微電子封裝，其中，該微電子元件包括複數個該些第一微電子元件，它們被堆疊並且疊置在該第一表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點；並且包括複數個該些第二微電子元件，它們被堆疊並且疊置在該第二表面上方並且電氣耦接該些第一封裝接點或第二封裝接點中的至少其中一個封裝接點。
  19. 根據申請專利範圍第13項的微電子封裝，其進一步包括第三封裝接點，其中，該些第一封裝接點、第二封裝接點、以及第三封裝接點分別為第一引線框元件的末端部分、第二引線框元件的末端部分、以及第三引線框元件的末端部分，其中，緊密相鄰的末端部分在正交於該封裝的主要表面的方向中彼此分隔，並且該些第一封裝接點在該正交方向中與該些第三封裝接點分隔的距離會比與該些第二封裝接點分隔的距離更遠。
  20. 根據申請專利範圍第18項的微電子封裝，其中，該複數個第一堆疊 式微電子元件被堆疊成使得每一個第一堆疊式微電子元件的一邊緣表面在正交於該邊緣表面的方向中偏離緊密位於此第一堆疊式微電子元件下方的每一個第一堆疊式微電子元件的邊緣表面，以及該複數個第一堆疊式微電子元件透過焊線電氣耦接該些第一封裝接點以及該些第二封裝接點。
  21. 根據申請專利範圍第13項的微電子封裝，其中，該些第一封裝接點以及該些第二封裝接點延伸超越該囊封區的一表面不超過25微米，該封裝在靠近該囊封的該遠端表面的位置處進一步包括一被設置在第一引線框元件以及至少一部分的該些第二引線框元件之間的順從材料。
  22. 根據申請專利範圍第13項的微電子封裝，其中，該些第二引線框元件突出超越該囊封區的一表面超過50微米。
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WO2017105740A1 (en) 2017-06-22

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