CN102820270A - 封装基板及其制法 - Google Patents

封装基板及其制法 Download PDF

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CN102820270A
CN102820270A CN2011102444643A CN201110244464A CN102820270A CN 102820270 A CN102820270 A CN 102820270A CN 2011102444643 A CN2011102444643 A CN 2011102444643A CN 201110244464 A CN201110244464 A CN 201110244464A CN 102820270 A CN102820270 A CN 102820270A
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layer
insulating barrier
packaging
base plate
pattern
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CN102820270B (zh
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陈宗源
程石良
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Unimicron Technology Corp
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

本发明公开了一种封装基板，包含有一核心层、一第一介电层、一第二线路图案、一第一防焊层以及一绝缘层。核心层的一第一表面设有一第一线路图案。第一介电层覆盖第一线路图案。第二线路图案设于第一介电层上，且第二线路图案包含有一内联机路图案，其位于一芯片接合区域内。第一防焊层覆盖住芯片接合区域以外的第二线路图案。绝缘层覆盖住芯片接合区域以及内联机路图案。多个埋入式接垫，设于绝缘层的一上表面。

Description

封装基板及其制法
技术领域
本发明涉及一种封装基板及其制法，具体涉及一种直接在基板表面制作中介层并制作内埋线路的封装基板及其制法。
背景技术
因应半导体封装组件的微缩及高密度等需求，业界已发展出一种三维封装技术，例如，直通硅晶穿孔(Through-Silicon Via，TSV)封装技术。TSV封装技术可大幅度提高芯片的晶体管立体密度，使半导体产业可以超越摩尔定律的发展速度。TSV封装技术的等级是L/S(线宽/线距比)小于6/6，使用硅载板，成本约为覆晶球格数组(FCBGA)基板的四倍。
目前，由于成本上的考虑，业界亟欲将覆晶球格数组技术应用在三维封装领域中，以代替较昂贵的TSV封装技术，但是会遭遇到以下问题。首先，在L/S＜6/6的制作工艺挑战下，现阶段的半加成(Semi-additive process，SAP)制作工艺仍无法制造出这类封装产品。其次，IC载板产业上所使用的介电材，其热膨胀系数(thermal expansion，CTE)与硅材相差过大，因而可能会产生可靠度上的问题。此外，超高密度的中介层(interposer)布局，会受限于目前防焊开口(SRO)＞65um的制作工艺瓶颈。最后，以目前的技术水平，基板的盲口开口仍有需大于40μm的限制，故浪费掉许多线路布局空间。
由此可知，产业上亟需一种封装基板及其制法，可解决上述先前技术所遇到的瓶颈及问题。
发明内容
本发明的目的在于提供一种封装基板及其制法，其主要结合激光埋线技术(Laser Embedded，LE)、热固化介电材技术(Thermal Curing Dielectric，TCD)以及化学机械抛光技术(Chemical Mechanical Polishing，CMP)，而直接在基板表面制作中介层并制作内线路，以解决上述封装技术的限制，并提升封装基板的集成度。
为达上述的目的，本发明提供一种封装基板，包含有一核心层、一第一介电层、一第二线路图案、一第一防焊层以及一绝缘层。核心层的一第一表面设有一第一线路图案。第一介电层覆盖第一线路图案。第二线路图案设于第一介电层上，且第二线路图案包含有一内联机路图案，其位于一芯片接合区域(chip mounting area)内。第一防焊层覆盖住芯片接合区域以外的第二线路图案。绝缘层覆盖住芯片接合区域以及内联机路图案。多个埋入式接垫，设于绝缘层的一上表面，且接垫上表面齐平或不高于绝缘层的上表面。其中所述埋入式接垫通过至少一设于所述绝缘层内的导电插塞电连接所述内联机路图，且所述埋入式接垫、所述内联机路图案、所述导电插塞以及所述绝缘层构成一中介层(interposer)
本发明提供一种封装基板的制法。提供一基板，包含有至少一内层线路图案以及至少一外层线路图案。外层线路图案包含有一内联机路图案，其位于一芯片接合区域内。于基板上覆盖一防焊层，覆盖住外层线路图案。将芯片接合区域内的防焊层去除，暴露出内联机路图案。于芯片接合区域内形成一绝缘层，覆盖住内联机路图案。对绝缘层进行一固化制作工艺。于绝缘层的一上表面形成多个埋入式接垫。
因此，本发明提出一种封装基板及其制法，其具有一内埋线路图案的绝缘层作为中介层，可取代传统中直通硅晶穿孔封装的次基板而直接制作于基板中。如此，可一并解决公知中半加成制作工艺在线宽限制下无法制造的问题、封装基板的介电材与硅材相差过大而产生的可靠度问题、防焊开口的尺寸无法缩小的瓶颈、以及基板的盲孔开口过大的问题。因此，本发明的封装基板具有尺寸更小以及可靠度更好的优势。
附图说明
图1-10为依据本发明一优选实施例所绘示的封装基板的制作方法的剖面示意图。
其中，附图标记说明如下：
100    基板              110a  内层线路图案
110b   内层线路图案      120a  外层线路图案
120b   外层线路图案      122a  内联机路图案
130    核心层            140   导电通孔
150a   第一介电层        150b  第二介电层
210a   防焊层            210b  防焊层
220a   接垫              220b  锡球焊垫
230    绝缘层            240   导电层
250    埋入式接垫        260   导电插塞
270    保护层            280   锡球
290    内建的中介层      300   芯片
310    焊垫锡球          320   打线
400    封装基板          A     芯片接合区域
P      抗镀铜层          R1、  开口
                         R2
S1、   外侧表面          S3    上表面
S2
S4     第一表面          S5    第二表面
t      沟槽
具体实施方式
图1-10为依据本发明一优选实施例所绘示的封装基板的制作方法的剖面示意图。首先，提供一基板100，包含有内层线路图案110a、110b以及外层线路图案120a、120b。本实施例中，基板100可例如为四层基板，但在其它实施例中亦可为六层基板或八层基板等，本发明不以此为限。内层线路图案110及外层线路图案120可以下列步骤形成，但本发明不以此为限。
如图1所示，首先，提供一核心层130。于核心层130中具有至少一导电通孔140以电性连接核心层130相对两面的内层线路图案110a与内层线路图案110b。核心层130例如为一玻纤预浸绝缘材，但不限于此。内层线路图案110a与内层线路图案110b可包含铜等导电材质。导电通孔140可以利用例如激光钻孔、机械钻孔或光刻工艺等各种方法形成。
接着，在核心层130相对两面上分别压合一第一介电层150a与一第二介电层150b，其中第一介电层150a与第二介电层150b分别覆盖内层线路图案110a与内层线路图案110b。然后，于第一介电层150a与第二介电层150b的表面上分别形成外层线路图案120a与外层线路图案120b。根据本发明的优选实施例，第一介电层150a与一第二介电层150b的材质可以是，例如，味之素树脂(Ajinomoto Bond Film，ABF)，但亦可为其它绝缘材质。外层线路图案120a与外层线路图案120b可包含铜等导电材质。值得注意的是，外层线路图案120a包含有一内联机路图案122a，其位于一芯片接合区域A内。
如图2所示，接着于基板100的二相对外侧表面S1、S2上分别覆盖防焊层210a、210b，其中，防焊层210a覆盖住外层线路图案120a以及第一介电层150a，防焊层210b覆盖住外层线路图案120b以及第二介电层150b。接着，将外侧表面S1上的芯片接合区域A内的防焊层210a去除，暴露出内联机路图案122a，以及在芯片接合区域A外的防焊层210a中形成多个防焊开口R1，其分别暴露出多个接垫220a。同样地，将外侧表面S2上的防焊层210b形成多个防焊开口R2，其分别暴露出多个接垫220b。防焊层210a以及防焊层210b可由环氧树脂形成，其中环氧树脂可以包含可感光的树脂成分，如此可直接对于防焊层210a以及防焊层210b进行光刻显影，并分别形成开口R1以及R2。
如图3所示，接着于芯片接合区域A内，以涂布法或印刷法在基板100的外侧表面S1上形成一绝缘层230，例如，热固化介电材(Thermal Curing Dielectric，TCD)，覆盖住内联机路图案122a。接着，再对绝缘层230进行一固化制作工艺。依据本发明的优选实施例，绝缘层230与第一介电层150a直接接触。依据本发明的优选实施例，绝缘层230不会与防焊层210a重叠。然而，在本发明其它实施例中，绝缘层230有可能与防焊层210a重迭。
接着，图4-8例示于绝缘层230的上表面S3形成多个埋入式接垫的方法。如图4所示，于芯片接合区域A以外形成一抗镀铜层P，其中，抗镀铜层P的材质例如抗镀铜介电材，但本发明不以此为限。抗镀铜层P可以利用印刷等方式形成。如图5所示，以激光埋线技术(Laser Embedded，LE)，于绝缘层230的上表面S3形成多个沟槽t。如图6所示，于沟槽t中填入一导电层240，其中导电层可包括一铜层，例如，利用电镀法或选择性化学铜填入沟槽t中，但本发明不以此为限。如图7所示，可选择性地先剥除抗镀铜层P，以暴露出其下方的防焊层210a及接垫220a。如图8所示，例如利用化学机械抛光制作工艺等方式，对导电层240进行平坦化，以形成多个埋入式接垫250以及导电插塞260，其中埋入式接垫250与内联机路图案122a可通过绝缘层230内的导电插塞260电连接。如此一来，由埋入式接垫250、内联机路图案122a、导电插塞260以及绝缘层230构成一内建的中介层(interposer)290。此内建的中介层290可整合于封装基板制作工艺中，直接形成于基板100的一表面上。
如图9所示，在对导电层240进行抛光后，可于多个埋入式接垫250表面形成一保护层270，用以防止埋入式接垫250直接与空气接触氧化，其中保护层270可包含无电镀镍/无电镀钯/浸镀金(electroless nickel/electroless palladium/immersion gold，ENEPIG)、无电镀镍/自催化金(electroless nickel/auto-catalyticgold，ENAG)或有机保焊剂等等。
如图10所示，通过将埋入式接垫250与芯片300中的金属凸块或焊垫锡球310接合，以及于绝缘层230与芯片300中填入底胶，可使芯片300与绝缘层230紧密接合，形成一封装构件400。如此，使芯片300与基板100接合。在一优选实施例中，绝缘层230的热膨胀系数与芯片300的热膨胀系数互相匹配。再者，芯片300可再进一步以打线(wire-bonding)320，电连接接垫220a。另外，可使多个锡球280，分别设于多个开口R2内，并与多个锡球焊垫220b接合。
详细而言，可将此封装构件400以核心层130为中心轴分为上、下二部分。封装构件400的上部分包含有核心层130、第一介电层150a、外层线路图案120a、防焊层210a以及绝缘层230。核心层130的一第一表面S4设有内层线路图案110a。第一介电层150a覆盖内层线路图案110a。外层线路图案120a设于第一介电层上150a，且外层线路图案120a包含有一内联机路图案122a，其位于一芯片接合区域A内。防焊层210a覆盖住芯片接合区域A以外的外层线路图案120a。绝缘层230覆盖住芯片接合区域A以及内联机路图案。多个埋入式接垫250，设于绝缘层230的一上表面S3上。此外，封装构件400的下部分包含核心层130、内层线路图案110b、第二介电层150b、外层线路图案120b、防焊层210b以及多个锡球280。内层线路图案110b设于核心层130的一第二表面S5。第二介电层150b覆盖内层线路图案110b。外层线路图案120b设于第二介电层150b上。外层线路图案120b包含有多个锡球焊垫220b。防焊层210b覆盖住第二介电层150b以及外层线路图案120b，其中防焊层210b包含有多个开口R2，分别暴露出多个锡球焊垫220b。多个锡球280分别设于多个开口R2内，并与多个锡球焊垫220b接合。
因此，本发明提出一种封装基板及其制法，其具有一内埋线路图案的绝缘层作为中介层，可取代传统硅次基板，而且本发明中介层直接制作并内建于基板上。详细而言，本发明的封装基板结合激光埋线技术(Laser Embedded，LE)、热固化介电材技术(Thermal Curing Dielectric，TCD)、化学机械抛光技术(Chemical Mechanical Polishing，CMP)以及选择性化学铜(Selective E-lessCopper Plating)，如此可一并解决公知技术半加成制作工艺在线宽限制下无法制造的问题、封装基板的介电材与硅材CTE相差过大而产生的可靠度问题、防焊开口的尺寸无法缩小的瓶颈、以及基板的盲孔开口过大浪费布线面积的问题。因此，本发明可大幅降低制作工艺时间以及制作工艺成本。并且，本发明的封装基板具有尺寸更小以及可靠度更好的优势。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种封装基板，其特征在于，包括：
一核心层，其一第一表面设有一第一线路图案；
一第一介电层，覆盖所述第一线路图案；
一第二线路图案，设于所述第一介电层上，所述第二线路图案包含有一内联机路图案，其位于一芯片接合区域内；
一第一防焊层，覆盖住所述芯片接合区域以外的所述第二线路图案；
一绝缘层，覆盖住所述芯片接合区域以及所述内联机路图案；以及
多个埋入式接垫，设于所述绝缘层的一上表面，其中所述埋入式接垫通过至少一设于所述绝缘层内的导电插塞电连接所述内联机路图，且所述埋入式接垫、所述内联机路图案、所述导电插塞以及所述绝缘层构成一中介层。
2.如权利要求1所述的封装基板，其特征在于，所述绝缘层包含热固型介电材。
3.如权利要求1所述的封装基板，其特征在于，所述绝缘层与所述第一介电层直接接触。
4.如权利要求1所述的封装基板，其特征在于，所述绝缘层的热膨胀系数与一芯片的热膨胀系数互相匹配。
5.如权利要求1所述的封装基板，其特征在于，还包括有一保护层，设于各所述多个埋入式接垫的表面上。
6.如权利要求1所述的封装基板，其特征在于，还包括：
一第三线路图案，设于所述核心层的一第二表面；
一第二介电层，覆盖所述第三线路图案；
一第四线路图案，设于所述第二介电层上，所述第四线路图案包含有多个锡球焊垫；
一第二防焊层，覆盖住所述第二介电层以及所述第四线路图案，其中所述第二防焊层包含有多个开口，分别暴露出所述多个锡球焊垫；以及
多个锡球，分别设于所述多个开口内，并与所述多个锡球焊垫接合。
7.一种封装基板的制法，其特征在于，包括：
提供一基板，包含有至少一内层线路图案以及至少一外层线路图案，所述外层线路图案包含有一内联机路图案，其位于一芯片接合区域内；
于所述基板上覆盖一防焊层，覆盖住所述外层线路图案；
将所述芯片接合区域内的所述防焊层去除，暴露出所述内联机路图案；
于所述芯片接合区域内形成一绝缘层，覆盖住所述内联机路图案；
对所述绝缘层进行一固化制作工艺；以及
于所述绝缘层的一上表面形成多个埋入式接垫。
8.如权利要求7所述的封装基板的制法，其特征在于，所述形成多个埋入式接垫包含以下步骤：
于所述芯片接合区域以外形成一抗镀铜层；
以激光于所述绝缘层的所述上表面形成多个沟槽；
于所述沟槽中填入一导电层；以及
抛光所述导电层，形成所述多个埋入式接垫。
9.如权利要求8所述的封装基板的制法，其特征在于，所述于所述沟槽中填入导电层利用电镀法或选择性化学铜。
10.如权利要求7所述的封装基板的制法，其特征在于，所述绝缘层包含热固型介电材。
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