CN116072637A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN116072637A
CN116072637A CN202211356322.0A CN202211356322A CN116072637A CN 116072637 A CN116072637 A CN 116072637A CN 202211356322 A CN202211356322 A CN 202211356322A CN 116072637 A CN116072637 A CN 116072637A
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China
Prior art keywords
pads
front surface
group
semiconductor chip
redistribution
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Pending
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CN202211356322.0A
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English (en)
Inventor
金善载
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN116072637A publication Critical patent/CN116072637A/zh
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体封装包括：第一凸块结构，包括设置在第二半导体芯片的第一组的第二后表面焊盘之下的钉头部分和从钉头部分延伸并连接到第一半导体芯片的第一组的第一前表面焊盘的接合引线部分；第二凸块结构，设置在第二半导体芯片的第二组的第二后表面焊盘之下；密封剂，包封第二半导体芯片以及第一凸块结构和第二凸块结构；以及再分布结构，设置在密封剂之下，并包括绝缘层、设置在绝缘层之下的再分布层、以及穿透绝缘层并将再分布层连接到第一凸块结构或第二凸块结构的再分布通路。连接到第一凸块结构的再分布通路的至少一部分与钉头部分接触。

Description

半导体封装
技术领域
本发明构思的实施方式针对半导体封装和制造该半导体封装的方法。
背景技术
安装在电子装置上的半导体封装被小型化以具有高性能和高容量。为了实现这些目标，正在研究其中包括贯穿硅通路(TSV)的半导体芯片垂直地堆叠的半导体封装。
发明内容
本发明构思的实施方式提供了具有简化的制造工艺和提高的良率的半导体封装以及制造该半导体封装的方法。
根据本发明构思的一实施方式，一种半导体封装包括：第一半导体芯片，包括第一前表面，第一组的第一前表面焊盘和第二组的第一前表面焊盘设置在第一前表面上；第二半导体芯片，包括第二前表面、第二后表面和贯通电极，第二前表面面对第一前表面并且电连接到第二组的第一前表面焊盘的第二前表面焊盘设置在第二前表面上，第二后表面与第二前表面相对并且第一组的第二后表面焊盘和第二组的第二后表面焊盘设置在第二后表面上，贯通电极将第一组的第二后表面焊盘和第二组的第二后表面焊盘的至少一部分与第二前表面焊盘彼此电连接；第一凸块结构，包括设置在第一组的第二后表面焊盘之下的钉头(stud)部分和从钉头部分延伸并连接到第一组的第一前表面焊盘的接合引线部分；第二凸块结构，设置在第二组的第二后表面焊盘之下；密封剂，包封第二半导体芯片以及第一凸块结构和第二凸块结构；以及设置在密封剂之下的再分布结构，其中再分布结构包括绝缘层、设置在绝缘层之下的再分布层、以及穿透绝缘层并将再分布层连接到第一凸块结构或第二凸块结构的再分布通路。连接到第一凸块结构的再分布通路的至少一部分与钉头部分接触。
根据本发明构思的一实施方式，一种半导体封装包括：第一半导体芯片，包括第一组的第一前表面焊盘和第二组的第一前表面焊盘；设置在第一半导体芯片之下的第二半导体芯片，包括第二前表面焊盘以及与第二前表面焊盘相对定位的第一组的第二后表面焊盘和第二组的第二后表面焊盘，第二前表面焊盘电连接到第二组的第一前表面焊盘；第一凸块结构，包括设置在第一组的第二后表面焊盘之下的钉头部分和从钉头部分延伸并连接到第一组的第一前表面焊盘的接合引线部分；以及设置在第二半导体芯片之下的再分布结构，其中再分布结构包括电连接到第一半导体芯片和第二半导体芯片的再分布层。第一组的第一前表面焊盘通过第一凸块结构电连接到再分布层。
根据本发明构思的一实施方式，一种半导体封装包括：第一半导体芯片，包括第一组的第一焊盘和第二组的第一焊盘；设置在第一半导体芯片之下的芯片结构，包括第二上焊盘以及与第二上焊盘相对定位的第一组的第二下焊盘和第二组的第二下焊盘，第二上焊盘电连接到第二组的第一焊盘；第一凸块结构，包括设置在第一组的第二下焊盘之下的钉头部分和从钉头部分延伸并连接到第一组的第一焊盘的接合引线部分；第二凸块结构，设置在第二组的第二下焊盘之下；以及设置在芯片结构之下的再分布结构，其中再分布结构包括电连接到第一凸块结构和第二凸块结构的再分布层。
根据本发明构思的一实施方式，一种制造半导体封装的方法包括：形成第一半导体晶片，第一半导体晶片包括彼此相对的第一前表面和第一后表面、以及设置在第一前表面上的第一组的第一前表面焊盘和第二组的第一前表面焊盘；形成至少一个第二半导体芯片，所述至少一个第二半导体芯片包括彼此相对的第二前表面和第二后表面、设置在第二后表面上的第一组的第二后表面焊盘和第二组的第二后表面焊盘、以及设置在第二组的第二后表面焊盘上的导电柱(post)；将所述至少一个第二半导体芯片附接到第一半导体晶片上，使得第二前表面面对第一前表面；形成将第一组的第一前表面焊盘和第一组的第二后表面焊盘电连接的接合引线，并在第一组的第二后表面焊盘上形成钉头凸块；在第一半导体晶片上形成初步密封剂，初步密封剂包封所述至少一个第二半导体芯片、接合引线和钉头凸块；执行抛光工艺，抛光工艺通过去除初步密封剂的一部分而形成密封剂，形成第一凸块结构并通过去除导电柱的一部分而形成第二凸块结构，第一凸块结构包括通过去除钉头凸块的一部分而形成的钉头部分，其中第一凸块结构和第二凸块结构通过密封剂的上表面暴露；以及在密封剂的上表面上形成再分布结构，其中再分布结构包括再分布层，再分布层电连接到第一凸块结构或第二凸块结构。
附图说明
图1A是根据本发明构思的一实施方式的半导体封装的截面图，图1B是沿着线I-I'截取的图1A的平面图，图1C是图1A的部分‘A’的局部放大图。
图2A是图1A的部分‘B’的局部放大图，图2B是示出图1A的部分‘B’的修改示例的局部放大图。
图3是根据本发明构思的一实施方式的半导体封装的区域的局部放大图。
图4A是根据本发明构思的一实施方式的半导体封装的截面图，图4B是图4A的部分‘C’的局部放大图。
图5是根据本发明构思的一实施方式的半导体封装的截面图。
图6是根据本发明构思的一实施方式的半导体封装的截面图。
图7A至图7C是示意性地示出制造图1A的第二半导体芯片的工艺的截面图。
图8A至图8D是示意性地示出制造图1A的半导体封装的工艺的截面图。
具体实施方式
在下文中，将参照附图描述本发明构思的实施方式。
图1A是根据本发明构思的一实施方式的半导体封装1的截面图，图1B是沿着线I-I'截取的图1A的平面图，图1C是图1A的部分‘A’的局部放大图。
参照图1A至图1C，根据一实施方式的半导体封装1包括第一半导体芯片100、至少一个第二半导体芯片200A或200B、第一凸块结构310和第二凸块结构320、密封剂410、以及再分布结构510。根据本发明构思的一实施方式，第一半导体芯片100具有第一宽度，至少一个第二半导体芯片200A或200B具有比第一宽度窄的第二宽度，再分布结构510在垂直方向或厚度方向(Z轴方向)上堆叠，第一半导体芯片100和再分布结构510使用接合引线和钉头凸块连接以降低工艺挑战和制造成本。当在第一半导体芯片100和再分布结构510之间形成金属柱时，良率可能降低，并且制造成本可能增加。例如，因为将金属柱形成至诸如100μm的特定高度或更高是挑战性的，并且产生诸如未对准的缺陷的可能性在诸如约300℃或更高的高温工艺中由于金属柱的变形而增加，所以当第一半导体芯片100和再分布结构510使用金属柱连接时，制造成本可能增加并且良率可能降低。在本发明构思的一实施方式中，通过引入替代金属柱的第一凸块结构310，能稳定地保持第一半导体芯片100和再分布结构510之间的连接状态，并且即使在高温工艺中，也能提高良率。
在下文中，将描述根据一实施方式的半导体封装1的每个部件。
第一半导体芯片100包括彼此相对的第一后表面BS1和第一前表面FS1，并进一步包括第一基板110、第一电路层120以及第一前表面焊盘131和132。尽管附图示出第一前表面FS1由第一电路层120提供，但实施方式不必然限于此，在一实施方式中，第一前表面FS1可以由堆叠在第一电路层120之下的单独绝缘材料层提供，诸如图4A所示的实施方式。
第一基板110是半导体晶片，其可以包括诸如硅或锗的半导体元素，或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)的化合物半导体。第一基板110包括有源表面(诸如面对第一电路层120的表面)和与有源表面相对的无源表面，有源表面包括掺有杂质的有源区。尽管图1A将第一基板110的上表面示为第一半导体芯片100的第一后表面BS1，但实施方式不必然限于此，在一实施方式中，提供第一半导体芯片100的第一后表面BS1的保护层形成在第一基板110上。保护层由诸如硅氧化物、硅氮化物或硅氮氧化物的绝缘材料制成，但根据一实施方式，也由绝缘聚合物制成。
第一电路层120设置在第一基板110的下表面上，并包括层间绝缘层121和布线结构125。层间绝缘层121包括可流动氧化物(FOX)、东燃硅氮烷(TOSZ)、未掺杂的硅石玻璃(USG)、硼硅玻璃(BSG)、磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、等离子体增强原硅酸乙酯(PETEOS)、氟化物硅酸盐玻璃(FSG)、高密度等离子体(HDP)氧化物、等离子体增强氧化物(PEOX)和可流动CVD(FCVD)氧化物中的至少一种或其组合。至少层间绝缘层121的围绕布线结构125的部分是低介电层。可以使用化学气相沉积(CVD)工艺、可流动CVD工艺或旋涂工艺形成层间绝缘层121。布线结构125是包括通路和布线图案的多层结构，布线图案包括例如铝(Al)、金(Au)、钴(Co)、铜(Cu)、镍(Ni)、铅(Pb)、钽(Ta)、碲(Te)、钛(Ti)和钨(W)之一或其组合。包括钛(Ti)、钛氮化物(TiN)、钽(Ta)或钽氮化物(TaN)的阻挡层可以设置在布线图案和/或通路与层间绝缘层121之间。构成集成电路的单独的器件115设置在第一基板110的下表面或其有源表面上。布线结构125通过诸如接触插塞的互连部分113电连接到单独的器件115。单独的器件115可以包括：FET，诸如平面FET或FinFET；存储器件，诸如闪存、DRAM、SRAM、EEPROM、PRAM、MRAM、FeRAM或RRAM；逻辑器件，诸如AND(与)、OR(或)或NOT(非)等；或各种有源和/或无源部件，诸如系统LSI、CIS或MEMS。
第一前表面焊盘131和132设置在第一半导体芯片100的第一前表面FS1上，并包括第一组的第一前表面焊盘131和第二组的第一前表面焊盘132。因为使第一电路层120和第二电路层220彼此面对缩短了信号传输路径，所以尽管第一前表面焊盘131和132被示为设置在第一前表面FS1之下的前表面焊盘，但是本发明构思的实施方式不必然限于此。根据一实施方式，第一半导体芯片100设置为使得第一后表面BS1面对第二半导体芯片200A和200B，并且与第一前表面焊盘131和132起相同作用的焊盘设置在第一后表面BS1之下，在这种情况下，所述焊盘可以被称为后表面焊盘。
第一组的第一前表面焊盘131和第二组的第一前表面焊盘132是每个电连接到第一电路层120的布线结构125的连接端子。第一组的第一前表面焊盘131和第二组的第一前表面焊盘132包括铜(Cu)、镍(Ni)、钛(Ti)、铝(Al)、金(Au)和银(Ag)中的任何一种或其合金。第一组的第一前表面焊盘131在垂直于第一前表面FS1的Z轴方向上不与第二半导体芯片200A和200B重叠。第二组的第一前表面焊盘132在Z轴方向上与第二半导体芯片200A和200B重叠。例如，第二组的第一前表面焊盘132面对第二半导体芯片200A和200B的第二前表面焊盘231，并通过单独的电连接构件(诸如导电凸块)电连接到第二前表面焊盘231，或者可以直接接触并连接到第二前表面焊盘231，如图4A的实施方式所示。第一组的第一前表面焊盘131通过第一凸块结构310电连接到位于比第二前表面焊盘231低的水平上的第二后表面焊盘的部分(在下文中，第一组的第二后表面焊盘251)。第一凸块结构310包括钉头部分312和接合引线部分311。
第二半导体芯片200A或200B具有彼此相对的第二后表面BS2和第二前表面FS2，并包括第二基板210、第二电路层220、第二前表面焊盘231、贯通电极240、第二布线层250以及第二后表面焊盘251和252。第二半导体芯片200A和200B水平分离并设置在第一半导体芯片100之下。根据一实施方式，第二半导体芯片的数量可以小于或大于图中所示的数量。此外，根据一实施方式，在Z轴方向上堆叠的多个第二半导体芯片设置在第一半导体芯片100之下，如图5的实施方式所示。例如，在一实施方式中，第一半导体芯片100以及第二半导体芯片200A和200B是构成多芯片模块(MCM)的芯粒。例如，在一实施方式中，第一半导体芯片100以及第二半导体芯片200A和200B可以分别包括中央处理单元(CPU)、图形处理单元(GPU)、现场可编程门阵列(FPGA)、I/O芯片或者诸如DRAM、SRAM、PRAM、MRAM、FeRAM或RRAM的存储器芯片等。第二基板210和第二电路层220具有与上述第一基板110和第一电路层120相同或相似的特性，彼此对应的部件可以由相似的附图标记表示，并且其重复描述可以被省略。尽管附图将第二半导体芯片200A和200B的第二电路层220示为面对第一半导体芯片100，但实施方式不必然限于此，在一实施方式中，第二布线层250面对第一半导体芯片100。
第二前表面焊盘231是设置在面对第一半导体芯片100的第一前表面FS1的第二前表面FS2上的连接端子，并电连接到第二电路层220的第二布线结构225。尽管附图将第二前表面焊盘231示为设置在第二前表面FS2上，但实施方式不必然限于此，在一实施方式中，第二前表面焊盘231与第二电路层220上的绝缘材料层一起提供平坦的第二前表面FS2，如图4A所示。
第二前表面焊盘231通过第三凸块结构330电连接到第二组的第一前表面焊盘132，第二前表面焊盘231和第二组的第一前表面焊盘132彼此面对。第三凸块结构330设置在第一半导体芯片100的第一前表面FS1与第二半导体芯片200A和200B的第二前表面FS2之间。此外，围绕第三凸块结构330的粘合膜335插置在第一半导体芯片100的第一前表面FS1与第二半导体芯片200A和200B的第二前表面FS2之间。第三凸块结构330可以是焊料球，或者可以是其中导电柱和焊料球组合的结构。粘合膜335可以是非导电膜(NCF)，但不必然限于此，并且可以包括例如能经受热压缩工艺的各种类型的聚合物膜之一。
第二前表面焊盘231通过贯通电极240电连接到第二后表面焊盘251和252的至少一部分。贯通电极240穿透第二基板210并将第二前表面焊盘231电连接到与其相对定位的第二后表面焊盘251和252的至少一部分。贯通电极240包括通路插塞245和围绕通路插塞245的侧表面的侧绝缘层241。侧绝缘层241将通路插塞245与第二基板210电分离。通路插塞245包括例如钨(W)、钛(Ti)、铝(Al)和铜(Cu)中的至少一种，并且可以通过镀覆工艺、PVD工艺或CVD工艺形成。侧绝缘层241包括诸如钨氮化物(WN)、钛氮化物(TiN)或钽氮化物(TaN)的金属化合物，并且可以通过PVD工艺或CVD工艺形成。
第二布线层250设置在第二基板210的下表面上并提供第二后表面BS2。第二布线层250包括在图2A中示出的后表面层间绝缘层253以及也在图2A中示出的后表面布线结构255。这具有与上述第一电路层120的层间绝缘层121和布线结构125相同或相似的特性，其重复描述可以被省略。
第二后表面焊盘251和252包括设置在第二后表面BS2上的第一组的第二后表面焊盘251和第二组的第二后表面焊盘252。第一组的第二后表面焊盘251与第二半导体芯片200A和200B的在图1B中示出的边缘200ed相邻设置，并与第二组的第二后表面焊盘252电隔离。第一组的第二后表面焊盘251通过第一凸块结构310电连接到再分布结构510的再分布层512。第二组的第二后表面焊盘252通过第二凸块结构320电连接到再分布结构510的再分布层512。根据本发明构思的一实施方式，钉头部分312形成在第一组的第二后表面焊盘251上，并且钉头部分312连接到再分布结构510的再分布通路513，再分布通路513缩短了第一半导体芯片100与再分布层512之间的信号传输距离。例如，第一半导体芯片100的通过接合引线部分311到达钉头部分312的信号通过再分布层512传输到外部连接端子520，而不经过第二布线层250的在图2A中示出的后表面布线结构255和第二凸块结构320。
第一凸块结构310包括设置在第一组的第二后表面焊盘251之下的钉头部分312、以及从钉头部分312延伸并连接到第一组的第一前表面焊盘131的接合引线部分311。钉头部分312和接合引线部分311可以一体形成，并且可以由相同的材料制成。钉头部分312和接合引线部分311包括金(Au)、银(Ag)、铅(Pb)、铝(Al)和铜(Cu)中的至少一种或其合金，但本发明构思的实施方式不必然限于此。钉头部分312包括未被密封剂410覆盖并接触再分布通路513的暴露表面。例如，钉头部分312包括图2A所示的下表面310BS、或通过密封剂410暴露的暴露表面。钉头部分312的暴露表面或下表面的在图1B中示出的直径D1与通过密封剂410暴露的第二凸块结构320的暴露表面或下表面的在图1B中示出的直径D2基本上相等。在这种情况下，“基本上相等”意思是没有故意不同地设计直径并且可能已经发生了工艺误差。钉头部分312的暴露表面或下表面的直径D1为约20μm或更大或者约30μm或更大。例如，钉头部分312的暴露表面或下表面的直径D1可以在从约20μm至约80μm、从约30μm至约70μm、或从约40μm至约60μm等的范围内。当钉头部分312的暴露表面或下表面的直径D1小于约20μm时，形成再分布通路513可能是挑战性的。钉头部分312的暴露表面或下表面的直径D1根据形成再分布通路513的工艺(诸如光刻工艺)的条件来确定，并且不必然限于以上提及的数值。
第二凸块结构320设置在第二组的第二后表面焊盘252之下，并直接连接到再分布通路513。第二凸块结构320包括与第一凸块结构310不同类型的金属。例如，第二凸块结构320包括铜(Cu)或铜合金(Cu)，但本发明构思的实施方式不必然限于此。第二凸块结构320的形状不同于第一凸块结构310的形状，这将在下面参照图2A描述。
密封剂410设置在第一半导体芯片100之下，并包封第二半导体芯片200A和200B以及第一凸块结构310和第二凸块结构320。密封剂410围绕第一凸块结构310的钉头部分312的侧表面和第二凸块结构320的侧表面，并且密封剂410的下表面与钉头部分312的下表面和第二凸块结构320的下表面共面。密封剂410包括例如热固性树脂(诸如环氧树脂)、热塑性树脂(诸如聚酰亚胺)、或包含无机填料和/或玻璃纤维的预浸料、ABF、FR-4、BT或EMC等。
再分布结构510设置在密封剂410以及第二半导体芯片200A和200B之下，并包括绝缘层511、再分布层512和再分布通路513。绝缘层511包括绝缘树脂。绝缘树脂包括以下至少一种：热固性树脂，诸如环氧树脂；热塑性树脂，诸如聚酰亚胺；或在这些树脂中浸渍有无机填料和/或玻璃纤维的树脂，诸如预浸料、ABF、FR-4、BT；或光敏树脂，诸如可光成像的电介质(PID)。绝缘层511可以包括在垂直方向上堆叠的多个绝缘层511。取决于工艺，多个绝缘层511之间的边界可能是不清晰的。
再分布层512设置在绝缘层511之下，并电连接到第一半导体芯片100以及第二半导体芯片200A和200B。再分布层512包括例如金属，该金属包括铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)和钛(Ti)中的至少一种或其合金。再分布层512包括例如接地图案、电源图案和信号图案。例如，再分布层512中的最下层比设置在其上的再分布层512厚以与外部连接端子520形成可靠的连接。外部连接端子520包括低熔点金属(诸如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)或铅(Pb))或含有它们的合金(诸如Sn-Ag-Cu)等，并且可以具有球形或类似球的形状。
再分布通路513穿透绝缘层511并将再分布层512电连接到第一凸块结构310或第二凸块结构320。特别地，连接到第一凸块结构310的再分布通路513的至少一个与钉头部分312直接接触。因此，第一组的第一前表面焊盘131和再分布层512之间的连接路径被最小化。再分布通路513包括与再分布层512的金属类似的金属。再分布通路513具有金属被填充到其中的填充通路形状、或其中金属材料沿着通路孔的内壁形成的共形通路形状。再分布通路513可以与再分布层512一体形成，但本发明构思的实施方式不必然限于此。
在下文中，将参照图2A和图2B更详细地描述第一凸块结构310和第二凸块结构320的结构。
图2A是图1A的部分‘B’的局部放大图，图2B是图1A的部分‘B’的修改示例的局部放大图。
参照图2A，在根据一实施方式的半导体封装1中，第一凸块结构310的钉头部分312在垂直于第二后表面BS2的Z轴方向上具有高度H1，高度H1基本上等于第二凸块结构320的高度H2。例如，第一组的第二后表面焊盘251和第二组的第二后表面焊盘252在相同的工艺中形成并具有基本相同的高度，分别设置在其之下的钉头部分312和第二凸块结构320通过参照图8C描述的抛光工艺也形成为具有基本相同的高度。此外，通过抛光工艺形成的钉头部分312的下表面310BS、第二凸块结构320的下表面320BS和密封剂410的下表面410BS基本上共面。
第一凸块结构310和第二凸块结构320通过不同的制造工艺形成。例如，第一凸块结构310的钉头部分312通过图8B所示的使用毛细管30的引线接合工艺与接合引线部分311一体形成，第二凸块结构320通过使用光致抗蚀剂的镀覆工艺形成。因此，第一凸块结构310的钉头部分312具有柱形状或硬币形状，其中侧面在水平方向(诸如X方向)上被凸形地圆化，第二凸块结构320具有拥有平坦侧表面(例如，在水平方向上没有被凸形地圆化的表面)的柱形状。例如，第二凸块结构320包括导电柱。例如，钉头部分312在水平方向(诸如平行于第二后表面BS2的X轴方向和Y轴方向)上具有最大宽度W1，最大宽度W1大于第二凸块结构320的最大宽度W2。
如上所述，由于与接合引线部分311一体形成的钉头部分312，将第一半导体芯片100的第一组的第一前表面焊盘131连接到再分布结构510的再分布层512或再分布通路513的电路径能被确保而无需穿过第二半导体芯片200A和200B的后表面布线结构255。其上设置钉头部分312的第一组的第二后表面焊盘251通过后表面布线结构255电连接到贯通电极240。来自第二半导体芯片200A和200B的信号可以通过贯通电极240和钉头部分312传输到再分布层512。
参照图2B，在一实施方式中，在一修改示例的半导体封装1a中，其上设置钉头部分312的第一组的第二后表面焊盘251与后表面布线结构255和贯通电极240电绝缘。不管第二半导体芯片200A和200B如何，从第一半导体芯片100的第一组的第一前表面焊盘131连接到再分布结构510的再分布层512或再分布通路513的电路径能够通过钉头部分312确保。
图3是根据本发明构思的一实施方式的半导体封装1A的区域的局部放大图。图3示出了在图1A的部分‘B’中的其中示出第一凸块结构310的区域。
参照图3，一实施方式的半导体封装1A具有与参照图1A至图2B描述的特征相同或相似的特征，除了钉头部分312由多个钉头层形成之外。例如，根据本实施方式的第一凸块结构310包括堆叠在第一组的第二后表面焊盘251和再分布通路513之间的第一钉头层312a和第二钉头层312b。第一钉头层312a和第二钉头层312b之一与接合引线部分311一体形成。第一钉头层312a具有硬币状的形状，第二钉头层312b具有硬币状的形状，或者可以具有面对再分布通路513的抛光表面。硬币形状例如通过使用平坦的硅片压缩钉头层而产生。第一钉头层312a和第二钉头层312b通过其间的界面分开。根据本实施方式，因为第一钉头层312a和第一组的第二后表面焊盘251之间的接触面积增大，所以确保了钉头部分312的连接可靠性和结构稳定性。取决于实施方式，钉头部分312包括比图中所示的钉头层数量更多的钉头层。
图4A是根据本发明构思的一实施方式的半导体封装1B的截面图，图4B是图4A的部分‘C’的局部放大图。
参照图4A和图4B，根据一实施方式的半导体封装1B进一步包括提供第一半导体芯片100的第一前表面FS1的第一绝缘层133、以及提供第二半导体芯片200A和200B的第二前表面FS2的第二绝缘层233。第一绝缘层133设置在第一电路层120的下表面120BS之下并围绕第一前表面焊盘131和132，第二绝缘层233设置在第二电路层220的上表面220US上并围绕第二前表面焊盘231。在本实施方式中，第一前表面FS1是由第一绝缘层133以及第一前表面焊盘131和132提供的平坦表面，第二前表面FS2是由第二绝缘层233和第二前表面焊盘231提供的平坦表面。第一前表面FS1和第二前表面FS2彼此接触和联接，并形成所谓的直接接合或混合接合结构。本实施方式的半导体封装1B具有与参照图1A至图3描述的特征相同或相似的特征，除了第一半导体芯片100以及第二半导体芯片200A和200B彼此直接接合之外。第一绝缘层133和第二绝缘层233每个包括能接合到另一个的材料，诸如硅氧化物(SiO)或硅碳氮化物(SiCN)。根据本实施方式，第一半导体芯片100与第二半导体芯片200A和200B之间的连接路径缩短，并且半导体封装1B的厚度减小。
图5是根据本发明构思的一实施方式的半导体封装1C的截面图。
参照图5，根据一实施方式的半导体封装1C具有与参照图1A至图4B描述的特征相同或相似的特征，除了半导体封装1C包括设置在第一半导体芯片100之下的至少一个芯片结构200之外，该至少一个芯片结构200包括多个第二半导体芯片200A、200B和200C。例如，第一半导体芯片100可以是包括CPU、GPU、FPGA、应用进程(AP)、数字信号处理器(DSP)、密码处理器、微处理器、微控制器、模数转换器和专用集成电路(ASIC)等中的至少一个的逻辑芯片，多个第二半导体芯片200A、200B和200C可以是诸如DRAM、SRAM、PRAM、MRAM、FeRAM或RRAM的存储器芯片。
第一半导体芯片100具有彼此相对的第一表面S1和第二表面S2，并包括设置在第二表面S2之下的第一组的第一焊盘130P1和第二组的第一焊盘130P2。
芯片结构200具有彼此相对的第三表面S3和第四表面S4，并包括设置在面对第一半导体芯片100的第三表面S3上的第二上焊盘230Pa、以及与第二上焊盘230Pa相对地设置在第四表面S4之下的第一组的第二下焊盘230Pb1和第二组的第二下焊盘230Pb2。
第二上焊盘230Pa通过单独的电连接构件(诸如导电凸块)电连接到第二组的第一焊盘130P2，或者直接接触并连接到第二组的第一焊盘130P2，如图4A的实施方式所示。
第一组的第二下焊盘230Pb1通过第一凸块结构310电连接到第一组的第一焊盘130P1和再分布结构510的再分布通路513或再分布层512。第二组的第二下焊盘230Pb2通过第二凸块结构320电连接到再分布结构510的再分布通路513或再分布层512。
第二上焊盘230Pa由多个第二半导体芯片200A、200B和200C中的最上面的第二半导体芯片200C的第二前表面焊盘231提供，第一组的第二下焊盘230Pb1和第二组的第二下焊盘230Pb2分别由多个第二半导体芯片200A、200B和200C中的最下面的第二半导体芯片200A的第二后表面焊盘251和252提供。
本实施方式的芯片结构200具有在垂直方向上的高度，在该高度可能不形成连接第一组的第一焊盘130P1和再分布层512的金属柱。例如，从第一半导体芯片100的第一表面S1到第二表面S2的高度小于从芯片结构200的第三表面S3到第四表面S4的高度。此外，从第一半导体芯片100的第二表面S2到芯片结构200的第四表面S4的高度H3为约100μm或更大。例如，从第二表面S2到第四表面S4的高度H3可以在从约100μm至约1mm、从约200μm至约1mm、从约300μm至约1mm、或从约300μm至约900μm的范围内。如上所述，根据本实施方式，可以使用第一凸块结构310形成约100μm或更大的电连接路径以提高工艺可靠性和良率。
图6是根据本发明构思的一实施方式的半导体封装1D的截面图。
参照图6，根据一实施方式的半导体封装1D具有与参照图1A至图5描述的特征相同或相似的特征，除了进一步包括布线基板600和散热结构630之外。
布线基板600是其上安装包括第一半导体芯片100、第二半导体芯片200A和200B、第一凸块结构310、第二凸块结构320、再分布结构510等的封装结构的支撑基板，并且是用于半导体封装的基板，诸如印刷电路板(PCB)、陶瓷基板或带布线基板等。布线基板600包括设置在布线基板600的主体的下表面上的下焊盘612、设置在主体的上表面上的上焊盘611、以及电连接下焊盘612和上焊盘611的布线电路613。取决于基板的类型，布线基板600的主体可以包括不同的材料。例如，当布线基板600是印刷电路板时，主体可以是薄铜堆叠板，或者具有布线层附加地堆叠在薄铜堆叠板的一侧或两侧上的形式。下焊盘612和上焊盘611以及布线电路613形成连接布线基板600的下表面和上表面的电路径。连接到下焊盘612的外部连接凸块620设置在布线基板600的下表面上。外部连接凸块620包括锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)和铅(Pb)中的至少一种和/或其合金。
散热结构630设置在布线基板600的上表面上，并覆盖第一半导体芯片100的上部。散热结构630通过粘合剂附接到布线基板600。粘合剂可以是导热粘合胶带、导热油脂和导热粘合剂等之一。散热结构630通过在第一半导体芯片100的上表面上的粘合构件631与第一半导体芯片100紧密接触。散热结构630包括导热材料。例如，散热结构630包括：金属或金属合金，其包括金(Au)、银(Ag)、铜(Cu)和铁(Fe)等中的至少一种；或者诸如石墨或石墨烯等的导电材料。散热结构630可以具有与图中所示的形状不同的形状。例如，散热结构630可以仅覆盖第一半导体芯片100的上表面。
图7A至图7C是示意性地示出制造图1A的第二半导体芯片200A的工艺的截面图。
参照图7A，在一实施方式中，制备从其形成多个第二半导体芯片的半导体晶片W2，其可以被称为“第二半导体晶片”，半导体晶片W2具有彼此相对的上表面US'和下表面LS。使用接合材料层12将第二半导体晶片W2临时接合到载体基板11。接合材料层12由可在后续工艺期间稳定地支撑第二半导体晶片W2的粘合聚合物材料制成。第二半导体晶片W2处于第二半导体芯片的一些部件被形成的状态。例如，第二半导体晶片W2包括设置在第二基板210的一个表面上的第二电路层220、设置在第二电路层220之下的第二前表面焊盘231、以及延伸穿过第二基板210的贯通电极240。与诸如“在……上”、“上”、“朝上”、“在……之下”、“下”、“朝下”等的方向相关的表述是基于图7A至图7C所示的方向。
参照图7B，在一实施方式中，在第二半导体晶片W2的已经通过抛光工艺被平坦化的上表面US上形成第二布线层250、第一组的第二后表面焊盘251和第二组的第二后表面焊盘252。随着第二半导体晶片W2的一部分通过抛光工艺被去除，贯通电极240的上端被暴露。
抛光工艺可以是诸如化学机械抛光(CMP)工艺、回蚀刻工艺或其组合的研磨工艺之一。例如，执行研磨工艺以将第二半导体晶片W2的厚度减小至预定厚度，并且应用具有适当条件的回蚀刻工艺以暴露贯通电极240。
第二布线层250包括在图2A中示出的后表面层间绝缘层253以及也在图2A中示出的后表面布线结构255。可以使用化学气相沉积(CVD)工艺、可流动CVD工艺或旋涂工艺形成后表面层间绝缘层253。可以使用蚀刻工艺或镀覆工艺等形成后表面布线结构255。
可以使用光刻工艺或镀覆工艺等形成第一组的第二后表面焊盘251和第二组的第二后表面焊盘252。在第二组的第二后表面焊盘252上形成导电柱320p。通过具有暴露第二组的第二后表面焊盘252的被蚀刻区域的在第二电路层220上的光致抗蚀剂图案以及通过用诸如铜(Cu)等的金属填充光致抗蚀剂的被蚀刻区域的镀覆工艺，形成导电柱320p。
参照图7C，在一实施方式中，图7B的第二半导体晶片W2被支撑在切割带13上，并且被切割并分离成多个第二半导体芯片200A。可以使用例如激光切割工艺来分离第二半导体晶片W2。使用取放装置分别将多个第二半导体芯片200A附接到图8A所示的第一半导体晶片W1的第一半导体芯片100。
图8A至图8D是示意性地示出制造图1A的半导体封装1的工艺的截面图。
参照图8A，在一实施方式中，制备第一半导体晶片W1，其包括彼此相对的第一前表面FS1和第一后表面BS1、以及设置在第一前表面FS1上的第一组的第一前表面焊盘131和第二组的第一前表面焊盘132。第一半导体晶片W1由第二载体基板20支撑。
此外，通过图7A至图7C的制造工艺制备至少一个第二半导体芯片200A或200B。至少一个第二半导体芯片200A或200B包括彼此相对的第二前表面FS2和第二后表面BS2、设置在第二后表面BS2上的第一组的第二后表面焊盘251和第二组的第二后表面焊盘252、以及设置在第二组的第二后表面焊盘252上的导电柱320p。
将至少一个第二半导体芯片200A或200B附接到第一半导体晶片W1，使得第二前表面FS2面对第一前表面FS1。将围绕第三凸块结构330的初步粘合膜层335p设置在至少一个第二半导体芯片200A或200B的第二前表面FS2之下。初步粘合膜层335p是非导电膜(NCF)。
参照图8B，在一实施方式中，在将至少一个第二半导体芯片200A或200B附接到第一半导体晶片W1上之后，形成电连接第一组的第一前表面焊盘131和第一组的第二后表面焊盘251的接合引线311p、以及在第一组的第二后表面焊盘251上的钉头凸块312p。通过使用毛细管30的引线接合工艺形成接合引线311p和钉头凸块312p。例如，钉头凸块312p与接合引线311p一体形成。通过热压工艺固定至少一个第二半导体芯片200A或200B。在热压工艺中，初步粘合膜层335流动以形成粘合膜335。
参照图8C，在一实施方式中，在第一半导体晶片W1上形成覆盖至少一个第二半导体芯片200A或200B、接合引线311p、钉头凸块312p和导电柱320p的初步密封剂410'。对初步密封剂410'应用抛光工艺以形成第一凸块结构310、第二凸块结构320和密封剂410。例如，抛光工艺形成钉头部分312，其中图8B的钉头凸块312p的一部分被去除，并形成第二凸块结构320，其中图8B的导电柱320p的部分被去除。第一凸块结构310包括在第一组的第二后表面焊盘251上的钉头部分312和从钉头部分312延伸的接合引线部分311。
每个第一凸块结构310的上表面312US和每个第二凸块结构320的上表面320US通过密封剂410的上表面410US暴露。密封剂410的上表面410US、第一凸块结构310的上表面或钉头部分312的上表面312US、以及第二凸块结构320的上表面320US共面。此外，通过密封剂410的上表面410US暴露的钉头部分312的上表面312US具有预定尺寸。例如，钉头部分312的上表面312US的直径为约50μm。
参照图8D，在一实施方式中，在密封剂410的上表面410US上形成再分布结构510。再分布结构510包括电连接到第一凸块结构310或第二凸块结构320的再分布层512。再分布结构510包括绝缘层511、再分布层512和再分布通路513。绝缘层511通过在密封剂410的上表面410US上涂覆并固化诸如PID的光敏树脂而形成。再分布层512和再分布通路513使用光刻工艺、蚀刻工艺和镀覆工艺等之一形成。
根据本发明构思的实施方式，通过引入包括接合引线的凸块结构，提供了具有降低的制造成本和提高的良率的半导体封装和制造该半导体封装的方法。
虽然以上已经示出和描述了实施方式，但是对于本领域技术人员将明显的是，在不脱离由所附权利要求限定的本发明构思的实施方式的范围的情况下，可以进行修改和变化。
本申请要求2021年11月2日在韩国知识产权局提交的第10-2021-0148489号韩国专利申请的优先权，该韩国专利申请的内容通过引用全部合并于此。

Claims (20)

1.一种半导体封装，包括：
第一半导体芯片，包括第一前表面，第一组的第一前表面焊盘和第二组的第一前表面焊盘设置在所述第一前表面上；
第二半导体芯片，包括第二前表面、第二后表面和贯通电极，所述第二前表面面对所述第一前表面并且电连接到所述第二组的所述第一前表面焊盘的第二前表面焊盘设置在所述第二前表面上，所述第二后表面与所述第二前表面相对并且第一组的第二后表面焊盘和第二组的第二后表面焊盘设置在所述第二后表面上，所述贯通电极将所述第一组的所述第二后表面焊盘和所述第二组的所述第二后表面焊盘的至少一部分与所述第二前表面焊盘彼此电连接；
第一凸块结构，包括设置在所述第一组的所述第二后表面焊盘之下的钉头部分和从所述钉头部分延伸并连接到所述第一组的所述第一前表面焊盘的接合引线部分；
第二凸块结构，设置在所述第二组的所述第二后表面焊盘之下；
密封剂，包封所述第二半导体芯片以及所述第一凸块结构和所述第二凸块结构；以及
设置在所述密封剂之下的再分布结构，其中所述再分布结构包括绝缘层、设置在所述绝缘层之下的再分布层、以及穿透所述绝缘层并将所述再分布层连接到所述第一凸块结构或所述第二凸块结构的再分布通路，
其中连接到所述第一凸块结构的所述再分布通路的至少一部分与所述钉头部分接触。
2.根据权利要求1所述的半导体封装，其中所述第一组的所述第二后表面焊盘与所述第二半导体芯片的边缘相邻设置。
3.根据权利要求1所述的半导体封装，其中所述第一组的所述第一前表面焊盘在垂直于所述第一前表面的方向上不与所述第二半导体芯片重叠。
4.根据权利要求1所述的半导体封装，其中所述第一凸块结构包括与所述第二凸块结构的金属不同的金属。
5.根据权利要求4所述的半导体封装，其中所述第一凸块结构包括金(Au)或金(Au)的合金。
6.根据权利要求4所述的半导体封装，其中所述第二凸块结构包括铜(Cu)或铜(Cu)的合金。
7.根据权利要求1所述的半导体封装，其中所述钉头部分在垂直于所述第二后表面的方向上的高度基本上等于每个所述第二凸块结构的高度。
8.根据权利要求1所述的半导体封装，其中所述钉头部分的下表面与每个所述第二凸块结构的下表面和所述密封剂的下表面基本上共面。
9.根据权利要求8所述的半导体封装，其中通过所述密封剂暴露的所述钉头部分的所述下表面的直径为约30μm或更大。
10.根据权利要求1所述的半导体封装，其中所述钉头部分在平行于所述第二后表面的方向上的最大宽度大于每个所述第二凸块结构的最大宽度。
11.根据权利要求1所述的半导体封装，进一步包括：
第三凸块结构，设置在所述第一半导体芯片的所述第一前表面和所述第二半导体芯片的所述第二前表面之间，其中所述第三凸块结构连接所述第二组的所述第一前表面焊盘和所述第二前表面焊盘；以及
粘合膜，插置在所述第一半导体芯片的所述第一前表面和所述第二半导体芯片的所述第二前表面之间，其中所述粘合膜围绕所述第三凸块结构。
12.根据权利要求1所述的半导体封装，其中所述第一半导体芯片进一步包括围绕所述第一组的所述第一前表面焊盘和所述第二组的所述第一前表面焊盘的第一绝缘层，其中所述第一前表面是由所述第一绝缘层和所述第一前表面焊盘提供的平坦表面，
所述第二半导体芯片进一步包括围绕所述第二前表面焊盘的第二绝缘层，其中所述第二前表面是由所述第二绝缘层和所述第二前表面焊盘提供的平坦表面，以及
所述第一前表面和所述第二前表面彼此接触。
13.一种半导体封装，包括：
第一半导体芯片，包括第一组的第一前表面焊盘和第二组的第一前表面焊盘；
设置在所述第一半导体芯片之下的第二半导体芯片，其中所述第二半导体芯片包括电连接到所述第二组的所述第一前表面焊盘的第二前表面焊盘、以及与所述第二前表面焊盘相对定位的第一组的第二后表面焊盘和第二组的第二后表面焊盘；
第一凸块结构，包括设置在所述第一组的所述第二后表面焊盘之下的钉头部分和从所述钉头部分延伸并连接到所述第一组的所述第一前表面焊盘的接合引线部分；以及
设置在所述第二半导体芯片之下的再分布结构，其中所述再分布结构包括电连接到所述第一半导体芯片和所述第二半导体芯片的再分布层，
其中所述第一组的所述第一前表面焊盘通过所述第一凸块结构电连接到所述再分布层。
14.根据权利要求13所述的半导体封装，进一步包括设置在所述第二组的所述第二后表面焊盘之下的第二凸块结构，
其中所述第二组的所述第二后表面焊盘通过所述第二凸块结构电连接到所述再分布层。
15.根据权利要求13所述的半导体封装，其中所述第二半导体芯片进一步包括电连接所述第二前表面焊盘与所述第一组的所述第二后表面焊盘和所述第二组的所述第二后表面焊盘的贯通电极。
16.一种半导体封装，包括：
第一半导体芯片，包括第一组的第一焊盘和第二组的第一焊盘；
设置在所述第一半导体芯片之下的芯片结构，其中所述芯片结构包括电连接到所述第二组的所述第一焊盘的第二上焊盘以及与所述第二上焊盘相对定位的第一组的第二下焊盘和第二组的第二下焊盘；
第一凸块结构，包括设置在所述第一组的所述第二下焊盘之下的钉头部分和从所述钉头部分延伸并连接到所述第一组的所述第一焊盘的接合引线部分；
第二凸块结构，设置在所述第二组的所述第二下焊盘之下；以及
设置在所述芯片结构之下的再分布结构，其中所述再分布结构包括电连接到所述第一凸块结构和所述第二凸块结构的再分布层。
17.根据权利要求16所述的半导体封装，其中所述第一半导体芯片包括彼此相对的第一表面和第二表面，其中所述第一组的所述第一焊盘和所述第二组的所述第一焊盘设置在所述第二表面之下，以及
所述芯片结构包括彼此相对的第三表面和第四表面，其中所述第二上焊盘设置在所述第三表面上，所述第一组的所述第二下焊盘和所述第二组的所述第二下焊盘设置在所述第四表面之下。
18.根据权利要求17所述的半导体封装，其中所述第一半导体芯片的从所述第一表面到所述第二表面的高度小于所述芯片结构的从所述第三表面到所述第四表面的高度。
19.根据权利要求17所述的半导体封装，其中从所述第一半导体芯片的所述第二表面到所述芯片结构的所述第四表面的高度为约100μm或更大。
20.根据权利要求16所述的半导体封装，其中所述芯片结构包括多个第二半导体芯片。
CN202211356322.0A 2021-11-02 2022-11-01 半导体封装 Pending CN116072637A (zh)

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