TWI746868B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI746868B
TWI746868B TW107124765A TW107124765A TWI746868B TW I746868 B TWI746868 B TW I746868B TW 107124765 A TW107124765 A TW 107124765A TW 107124765 A TW107124765 A TW 107124765A TW I746868 B TWI746868 B TW I746868B
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Taiwan
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contact pad
semiconductor
electrode
semiconductor device
contact
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TW107124765A
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TW201941392A (zh
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築山慧至
小柳勝
伊東幹彦
河崎一茂
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日商東芝記憶體股份有限公司
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

實施形態提供一種能夠實現高速信號之收發之半導體裝置。 實施形態之半導體裝置具備：基底構件；及複數個半導體晶片，其等積層於上述基底構件上，且經由連接構件相互電性連接；上述複數個半導體晶片中之第1半導體晶片包含：半導體基板，其具有元件面及其相反側之背面；功能層，其設置於上述元件面上；及複數個貫通電極，其等在上述半導體基板中自上述背面延伸至上述元件面，且電性連接於上述功能層；上述第1半導體晶片經由連接於上述複數個貫通電極之上述連接構件而電性連接於上述複數個半導體晶片中相鄰之第2半導體晶片；上述功能層包含：第1接觸墊；及第2接觸墊，其位於上述複數個半導體晶片之積層方向上之上述半導體基板與上述第1接觸墊之間之層級；上述複數個貫通電極包含：第1貫通電極，其連接於上述第1接觸墊；及第2貫通電極，其連接於上述第2接觸墊。

Description

半導體裝置
實施形態係關於一種半導體裝置。
存在基底基板上積層複數個半導體晶片之構造之半導體裝置。此種半導體裝置中，將基底基板上之配線與各半導體晶片之間用金屬線電性連接，並經由基底基板之配線將外部電路與各晶片電性連接。然而，對於外部電路與各半導體晶片之間之高速信號之收發，金屬線之寄生電容及寄生電感成為了障礙。
實施形態提供一種能夠實現高速信號之收發之半導體裝置。
實施形態之半導體裝置具備：基底構件；及複數個半導體晶片，其等積層於上述基底構件上，且經由連接構件相互電性連接；上述複數個半導體晶片中之第1半導體晶片包含：半導體基板，其具有元件面及其相反側之背面；功能層，其設置於上述元件面上；及複數個貫通電極，其等在上述半導體基板中自上述背面延伸至上述元件面，且電性連接於上述功能層；上述第1半導體晶片係經由連接於上述複數個貫通電極之上述連接構件而電性連接於上述複數個半導體晶片中相鄰之第2半導體晶片；上述功能層包含：第1接觸墊；及第2接觸墊，其位於上述複數個半導體晶片之積層方向上之上述半導體基板與上述第1接觸墊之間之層級；上 述複數個貫通電極包含：第1貫通電極，其連接於上述第1接觸墊；及第2貫通電極，其連接於上述第2接觸墊。
1:半導體裝置
10:基底構件
13:微凸塊
15:配線
17:連接凸塊
20:邏輯晶片
23:FC凸塊
25:連接凸塊
31:絕緣膜
33:層間絕緣膜
35:絕緣膜
37:絕緣膜
BL:位元線
C/D:行解碼器
C0:接觸插塞
C1:接觸插塞
C2:接觸插塞
CC:接觸插塞
CG:接觸插塞
CM0:接觸墊
CM1:接觸墊
CM2:接觸墊
CMB:接觸墊
CP:微凸塊
CS:接觸插塞
D/C:降壓電路
DCC:資料控制電路
DRC:控制電路
FL:功能層
GL:閘極配線
I/F:介面電路
M0:配線層
M1:配線層
MC:記憶胞
MCA:記憶胞陣列
R/D:列解碼器
SC:半導體通道
SC1~SCn:半導體晶片
SGD:選擇閘極
SGS:選擇閘極
SL:源極層
SS:半導體基板
SSB:背面
SST:元件面
TP:端子部
TP1:端子部
TP2:端子部
Tr:電晶體
U/C:升壓電路
VB:接觸插塞
VC:貫通電極
VC1:貫通電極
VC2:貫通電極
VCC:外部電壓
VDD:內部電壓
VPP:外部電壓
VSS:外部電壓
WL:字元線
圖1係表示實施形態之半導體裝置之模式剖視圖。
圖2係模式性地表示實施形態之半導體裝置之連接構造之局部剖視圖。
圖3係模式性地表示實施形態之半導體裝置之另一連接構造之局部剖視圖。
圖4係表示實施形態之半導體裝置之功能層之構成之方塊圖。
圖5係表示實施形態之半導體裝置之功能層之模式剖視圖。
以下，一面參照圖式，一面對實施形態進行說明。對於圖式中之同一部分標附同一編號並適當省略其詳細說明，而對不同部分進行說明。再者，圖式係模式性或概念性之圖，各部分之厚度與寬度之關係、部分間之大小之比率等未必與實物相同。又，即便於表示相同部分之情形時，根據圖式亦存在相互之尺寸或比率不同地被表示之情形。
進而，用各圖中所示之X軸、Y軸及Z軸來說明各部分之配置及構成。X軸、Y軸、Z軸相互正交，分別表示X方向、Y方向、Z方向。又，存在將Z方向作為上方且將其相反方向作為下方進行說明之情形。
圖1係表示實施形態之半導體裝置1之模式剖視圖。半導體裝置1具備基底構件10及複數個半導體晶片SC1~SCn。半導體晶片SC1~ SCn積層於基底構件10上。又，半導體晶片SC1~SCn經由連接構件(以下為微凸塊13)而相互電性連接。
半導體晶片SC1~SCn-1包含複數個貫通電極VC(例如矽通孔(Through Silicon Via：TSV))，且經由連接於各個貫通電極VC之微凸塊13而相互電性連接。在半導體晶片SC1~SCn中位於最下段之半導體晶片SC1之下表面，設置有配線15。配線15電性連接於半導體晶片SC1。半導體晶片SC1係利用連接於配線15之連接凸塊17而連接於基底構件10。
半導體晶片SC1~SCn隔著微凸塊13依序覆晶接合。微凸塊13例如具有直徑5~50μm之尺寸，且以10~100μm之間距配置於半導體基板SS之背面上。貫通電極VC沿著半導體基板SS之背面以例如10~100μm之間距配置。
如圖1所示，半導體裝置1進而具備配置於基底構件10與半導體晶片SC1之間之邏輯晶片20。邏輯晶片20例如經由覆晶凸塊(以下為FC凸塊23)連接於配線15。邏輯晶片20與半導體晶片SC1~SCn經由配線15進行例如資料及指令之收發。
基底構件10具有與配置有半導體晶片SC1~SCn之上表面為相反側之下表面，複數個連接凸塊25配置於基底構件10之下表面。連接凸塊25經由設置於基底構件10之配線及連接插塞(未圖示)而電性連接於半導體晶片SC1~SCn及邏輯晶片20。連接凸塊25將半導體裝置1例如連接於未圖示之安裝基板，並且將半導體晶片SC1~SCn及邏輯晶片20連接於外部電路。
如此，半導體裝置1中，藉由將半導體晶片SC1~SCn經由貫通電極VC及微凸塊13相互連接，從而能在與邏輯晶片20之間進行高速 信號之收發。
圖2及圖3係模式性地表示實施形態之半導體裝置1之連接構造之局部剖視圖。圖2係表示將半導體晶片SC1~SCn相互連接之端子部TP1之模式剖視圖。圖3係表示另一端子部TP2之模式剖視圖。
如圖2及圖3所示，半導體晶片SC1~SCn分別包含半導體基板SS與功能層FL。半導體基板SS例如具有元件面SST及其相反側之背面SSB。功能層FL例如包含記憶元件，設置於元件面SST之上。
圖2所示之端子部TP1包含貫通電極VC1與微凸塊CP。貫通電極VC1將半導體基板SS自背面SSB貫通至元件面SST，電性連接於功能層FL。微凸塊CP設置於功能層FL之正面側。
貫通電極VC1利用絕緣膜31而與半導體基板SS電性絕緣。又，貫通電極VC1經由微凸塊13連接於與半導體基板SS之背面SSB側相鄰之半導體晶片之功能層FL。微凸塊CP經由另一微凸塊13連接於與功能層FL之正面側相鄰之半導體晶片之背面。
功能層FL於貫通電極VC1與微凸塊CP之間包含複數個接觸墊CMB、CM0、CM1及CM2。接觸墊CMB、CM0、CM1及CM2於自貫通電極VC1朝向微凸塊CP之方向上依序配置。
於各接觸墊間，設置有層間絕緣膜33。接觸墊CMB隔著絕緣膜35設置於半導體基板SS上。接觸墊CMB經由複數個接觸插塞C0連接於接觸墊CM0。接觸墊CM0經由複數個接觸插塞C1連接於接觸墊CM1。又，接觸墊CM1經由複數個接觸插塞C2連接於接觸墊CM2。又，接觸墊CM1例如設置於與Z方向上之功能層FL之配線層M1之層級相同之層級，且連接於配線層M1中之配線。
貫通電極VC1貫穿絕緣膜35而延伸，連接於接觸墊CMB。微凸塊CP貫穿覆蓋功能層FL之表面之絕緣膜37而延伸，連接於接觸墊CM2。連接各接觸墊間之接觸插塞C0、C1及C2之X方向及Y方向之寬度較貫通電極VC1之X方向及Y方向之寬度窄，且較微凸塊CP之X方向及Y方向之寬度窄。
圖3所示之端子部TP2包含貫通電極VC2與微凸塊CP。貫通電極VC2自背面SSB至元件面SST貫通半導體基板SS，電性連接於功能層FL。貫通電極VC2利用絕緣膜31而與半導體基板SS電性絕緣。
於端子部TP2，未設置接觸墊CMB及接觸插塞C0，貫通電極VC2直接連接於接觸墊CM0。又，貫通電極VC2之連接於接觸墊CM0之部分之X方向之寬度W2較貫通電極VC1之連接於接觸墊CMB之部分之X方向之寬度W1(參照圖2)寬。
圖4係表示實施形態之半導體裝置1之功能層FL之構成之方塊圖。功能層FL例如為記憶元件，包含記憶胞陣列MCA與控制電路DRC。
控制電路DRC例如經由列解碼器R/D、行解碼器C/D、資料控制電路DCC、介面電路I/F及升壓電路U/C而控制記憶胞陣列MCA之動作。
如圖4所示，對功能層FL供給例如外部電壓VCC、VPP及VSS。又，介面電路I/F例如與邏輯晶片20之間進行資料及指令之收發。
外部電壓VCC例如被供給至降壓電路D/C，降壓電路D/C向功能層內之各電路區塊供給內部電壓VDD。外部電壓VPP例如被供給至升壓電路U/C，升壓電路U/C例如向列解碼器供給程式電壓，向記憶胞 陣列MCA供給資料刪除電壓。
介面電路I/F例如經由端子部TP1進行資料及指令之收發。外部電壓VCC、VPP及VSS例如經由複數個端子部TP2被分別供給。
於端子部TP2，例如未設置接觸墊CMB及接觸插塞C0，貫通電極VC2直接連接於接觸墊CM0。藉此，能降低貫通電極VC2與微凸塊CP之間之電阻。
例如，隨著功能層FL中所包含之記憶胞陣列MCA及各電路之微細化進展，接觸插塞C0、C1及C2之X方向及Y方向之寬度亦變窄，而內部電阻變大。因此，貫通電極VC與微凸塊CP之間之內部電阻亦變大，因其電壓降低而使得經由端子部TP供給至半導體晶片SC1~SCn之電壓變得各不相同，而有產生各功能層FL之誤動作之虞。
本實施形態中，藉由經由端子部TP2供給外部電壓，從而能夠降低其內部電阻，抑制被供給至半導體晶片SC1~SCn之電壓之差。另一方面，於端子部TP1，由於使用相較於貫通電極VC2而言X方向及Y方向之寬度較窄之貫通電極VC1，故而於邏輯晶片20與各功能層FL之介面電路I/F之間能夠進行更高速之收發。
圖5係例示實施形態之半導體裝置之功能層FL之模式剖視圖。功能層FL例如為包含經三維配置之記憶胞MC之NAND(Not and，反及)型記憶元件。
如圖5所示，記憶胞陣列MCA包含積層於半導體基板SS上方之複數個電極層(例如選擇閘極SGS、字元線WL、選擇閘極SGD)及半導體通道SC。半導體通道SC貫穿複數個電極層而於Z方向上延伸。記憶胞MC設置於半導體通道SC與字元線WL交叉之部分。
於複數個電極層中位於最下層之選擇閘極SGS與半導體基板SS之間，設置有源極層SL。源極層SL連接於半導體通道SC。又，於半導體基板SS與源極層SL之間，配置有包含設置於半導體基板SS之表層之電晶體Tr之電路。
於複數個電極層之上方，設置有配線層M0及M1。配線層M0位於複數個電極層與配線層M1之間，例如包含連接於半導體通道SC之位元線BL及連接於各電極層之閘極配線GL。
於記憶胞陣列MCA，配置有接觸插塞CG、CS、CC及VB。接觸插塞CG將各電極層連接於閘極配線GL。接觸插塞CS將源極層SL連接於配線層M0中之其他配線。接觸插塞CC將下層之電路連接於配線層M0中更為其他之配線。又，接觸插塞VB將配線層M0中之配線連接於配線層M1中之配線。
端子部TP1包含設置於貫通電極VC1與微凸塊CP(參照圖2)之間之接觸墊CMB、接觸墊CM0、及接觸墊CM1。
如圖5所示，接觸墊CMB配置於與Z方向上之源極層SL之層級相同之位置。接觸墊CM0配置於與Z方向上之配線層M0之層級相同之位置。接觸墊CM1配置於與Z方向上之配線層M1之層級相同之位置。又，接觸墊CM1於未圖示之部分與配線層M1中之配線連接。
接觸墊CMB與接觸墊CM0經由複數個接觸插塞C0而電性連接。接觸插塞C0配置於與記憶胞陣列MCA中之接觸插塞CG、CS及CC相同之層級。即，於半導體晶片SC1~SCn之製造過程中，接觸插塞C0係在與接觸插塞CG、CS及CC相同之製造過程中形成。因此，接觸插塞C0具有與接觸插塞CG、CS及CC大致相同之尺寸。
進而，接觸墊CM0與接觸墊CM1經由複數個接觸插塞C1而電性連接。接觸插塞C1配置於與記憶胞陣列MCA中之接觸插塞VB相同之層級。即，於半導體晶片SC1~SCn之製造過程中，接觸插塞C1係在與接觸插塞VB相同之製造過程中形成，具有與接觸插塞VB大致相同之尺寸。
如此，於端子部TP1，連接貫通電極VC1與微凸塊CP之間之接觸墊CMB~CM1、接觸插塞C0及C1係與記憶胞陣列MCA同時形成。因此，當記憶胞陣列MCA之微細化進展時，接觸插塞C0及C1之尺寸亦縮小，而其內部電阻變大。因此，於為了向功能層FL供給外部電壓而設置之端子部TP2，減少接觸墊CMB~CM1之層數，將貫通電極VC2連接於更上層之接觸墊。藉此，能夠抑制被供給至功能層FL之電壓VCC、VPP及VSS之偏差。圖5所示之功能層FL亦包含配置於未圖示部分之端子部TP2。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為例而提出，並未意欲限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且能夠在不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請]
本申請享有以日本專利申請2018-55227號(申請日：2018年3月22日)為基礎申請之優先權。本申請係藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧半導體裝置
10‧‧‧基底構件
13‧‧‧微凸塊
15‧‧‧配線
17‧‧‧連接凸塊
20‧‧‧邏輯晶片
23‧‧‧FC凸塊
25‧‧‧連接凸塊
SC1~SCn‧‧‧半導體晶片
TP‧‧‧端子部
VC‧‧‧貫通電極

Claims (20)

  1. 一種半導體裝置，其具備： 基底構件；及 複數個半導體晶片，其等積層於上述基底構件上，經由連接構件而相互電性連接；且 上述複數個半導體晶片中之第1半導體晶片包含：半導體基板，其具有元件面及其相反側之背面；功能層，其設置於上述元件面上；及複數個貫通電極，其等在上述半導體基板中自上述背面延伸至上述元件面，且電性連接於上述功能層； 上述第1半導體晶片經由連接於上述複數個貫通電極之上述連接構件而電性連接於上述複數個半導體晶片中相鄰之第2半導體晶片； 上述功能層包含：第1接觸墊；及第2接觸墊，其位於上述複數個半導體晶片之積層方向上之上述半導體基板與上述第1接觸墊之間之層級； 上述複數個貫通電極包含：第1貫通電極，其連接於上述第1接觸墊；及第2貫通電極，其連接於上述第2接觸墊。
  2. 如請求項1之半導體裝置，其中上述第1半導體晶片構成為經由上述第1貫通電極及上述第1接觸墊向上述功能層供給外部電壓。
  3. 如請求項1之半導體裝置，其進而具備設置於上述複數個半導體晶片中配置於最接近上述基底構件之位置的半導體晶片與上述基底構件之間、且向上述複數個半導體晶片發送信號的另一半導體晶片；且 上述第1半導體晶片構成為經由上述第2貫通電極及上述第2接觸墊向上述功能層發送上述信號。
  4. 如請求項1之半導體裝置，其中上述第2貫通電極之與上述積層方向交叉之第1方向之寬度較上述第1貫通電極之上述第1方向之寬度窄。
  5. 如請求項1之半導體裝置，其中上述功能層包含：配線層，其位於上述積層方向上之與上述第1接觸墊之層級接近之層級；及第3接觸墊，其位於與上述配線層之上述積層方向之層級大致相同之層級，連接於上述配線層中之配線； 上述第2接觸墊位於上述第2貫通電極與上述第3接觸墊之間，經由複數個第1接觸插塞而電性連接於上述第3接觸墊； 上述複數個第1接觸插塞在與上述積層方向交叉之第1方向上之寬度較上述第1貫通電極及上述第2貫通電極之上述第1方向之寬度窄。
  6. 如請求項5之半導體裝置，其中上述功能層進而包含位於上述第2接觸墊與上述第3接觸墊之間之第4接觸墊； 上述第2接觸墊經由上述複數個第1接觸插塞而連接於上述第4接觸墊； 上述第4接觸墊經由複數個第2接觸插塞而連接於上述第3接觸墊。
  7. 如請求項1之半導體裝置，其中上述複數個半導體晶片分別包含將上述複數個貫通電極與上述半導體基板電性絕緣之絕緣膜。
  8. 如請求項1之半導體裝置，其中上述複數個半導體晶片進而包含與上述第1半導體晶片相鄰之第3半導體晶片； 上述第1半導體晶片位於上述第2半導體晶片與上述第3半導體晶片之間，且經由上述連接構件之外之另一連接構件而電性連接於上述第3半導體晶片； 上述功能層包含連接於上述另一連接構件之第5接觸墊。
  9. 如請求項8之半導體裝置，其中上述第1接觸墊及上述第2接觸墊位於上述積層方向上之上述第5接觸墊與上述半導體基板之間之層級。
  10. 如請求項9之半導體裝置，其中上述功能層包含：配線層，其位於上述積層方向上之與上述第1接觸墊之層級接近之層級；及第3接觸墊，其位於與上述配線層之上述積層方向之層級大致相同之層級，連接於上述配線層中之配線；且 上述第5接觸墊經由複數個第3接觸插塞而連接於上述第3接觸墊。
  11. 一種半導體裝置，其具備： 基底構件；及 複數個記憶體晶片，其等積層於上述基底構件上，經由連接構件而相互電性連接； 上述複數個記憶體晶片中之第1記憶體晶片包含：半導體基板，其具有元件面及其相反側之背面；記憶胞陣列，其設置於上述元件面上，包含複數個記憶胞；端子部，其電性連接於上述記憶胞陣列；及複數個貫通電極，其等在上述半導體基板中自上述背面延伸至上述元件面，連接於上述端子部； 上述第1記憶體晶片經由連接於上述複數個貫通電極之上述連接構件而電性連接於上述複數個記憶體晶片中相鄰之第2記憶體晶片； 上述端子部包含：第1接觸墊；及第2接觸墊，其位於上述複數個記憶體晶片之積層方向上之上述半導體基板與上述第1接觸墊之間之層級； 上述複數個貫通電極包含：第1貫通電極，其連接於上述第1接觸墊；及第2貫通電極，其連接於上述第2接觸墊。
  12. 如請求項11之半導體裝置，其中上述第1記憶體晶片進而包含設置於上述半導體基板與上述記憶胞陣列之間之電路； 上述第1記憶體晶片構成為經由上述第1貫通電極及上述第1接觸墊而被供給外部電壓至上述電路。
  13. 如請求項12之半導體裝置，其中上述第1記憶體晶片構成為經由上述第2貫通電極及上述第2接觸墊而被傳送信號至上述電路。
  14. 如請求項13之半導體裝置，其中上述第1記憶體晶片進而包含：第3接觸墊，其設置於上述端子部；及配線層，其包含連接於上述記憶胞陣列及上述第3接觸墊之配線； 上述2接觸墊位於上述第2貫通電極與上述第3接觸墊之間，經由複數個第1接觸插塞而電性連接於上述第3接觸墊。
  15. 如請求項14之半導體裝置，其中上述記憶胞陣列包含：複數個電極層，其等在上述積層方向上積層；半導體層，其於上述積層方向上貫穿上述複數個電極層；及複數個第2接觸插塞，其等連接上述複數個電極層與上述配線層中之配線； 上述複數個第2接觸插塞位於與上述複數個第1接觸插塞在上述積層方向上之層級大致相同之層級。
  16. 如請求項14之半導體裝置，其中上述配線層包含將上述第3接觸墊與上述電路連接之配線。
  17. 如請求項14之半導體裝置，其中上述第3接觸墊位於與上述積層方向上之上述配線層之層級大致相同之層級。
  18. 如請求項14之半導體裝置，其中上述端子部進而包含位於上述第2接觸墊與上述第3接觸墊之間之第4接觸插塞； 上述第2接觸墊經由上述複數個第1接觸插塞而連接於上述第4接觸墊； 上述第4接觸墊經由複數個第3接觸插塞而連接於上述第3接觸墊。
  19. 如請求項14之半導體裝置，其中與上述積層方向交叉之第1方向上之上述複數個第1接觸插塞之寬度較上述第2貫通電極之上述第1方向之寬度窄。
  20. 如請求項11之半導體裝置，其中與上述積層方向交叉之第1方向上之上述第1貫通電極之寬度較上述第1方向上之上述第2貫通電極之寬度寬。
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