TWI740555B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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TWI740555B
TWI740555B TW109121785A TW109121785A TWI740555B TW I740555 B TWI740555 B TW I740555B TW 109121785 A TW109121785 A TW 109121785A TW 109121785 A TW109121785 A TW 109121785A TW I740555 B TWI740555 B TW I740555B
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contacts
layer
electrodes
chip
area
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TW109121785A
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TW202113824A (zh
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岡田信彬
内海哲章
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日商鎧俠股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
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    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract

實施方式提供一種高速地動作之半導體記憶裝置。  實施方式之半導體記憶裝置具備第1、第2晶片及第1、第2電源電極。第1晶片具備複數個第1導電層、與其等對向之半導體柱、連接於複數個第1導電層之複數個第1接點、連接於第1電源電極之複數個第2接點、連接於第2電源電極之複數個第3接點、及連接於複數個第1接點之複數個第1貼合電極。第2晶片具備半導體基板、設置於半導體基板之複數個電晶體、連接於複數個電晶體之複數個第4接點、及連接於複數個第4接點之複數個第2貼合電極。複數個第2接點與複數個第3接點對向。

Description

半導體記憶裝置
本實施方式係關於一種半導體記憶裝置。
已知有具備相互連接之第1晶片及第2晶片之半導體記憶裝置。第1晶片具備：複數個第1導電層，其等沿第1方向排列；半導體柱，其沿第1方向延伸且與複數個第1導電層對向；複數個接點，其等沿第1方向延伸且連接於複數個第1導電層；及複數個第1貼合電極，其等經由該等複數個接點而連接於複數個第1導電層。第2晶片具備：半導體基板，其具有與第1方向交叉之表面；複數個電晶體，其等設置於半導體基板；複數個接點，其等沿第1方向延伸且連接於複數個電晶體；及複數個第2貼合電極，其等經由該等複數個接點而連接於複數個電晶體。第1晶片及第2晶片係以複數個第1貼合電極與複數個第2貼合電極對向之方式配置，複數個第1貼合電極連接於複數個第2貼合電極。
實施方式提供一種高速地動作之半導體記憶裝置。
一實施方式之半導體記憶裝置具備相互連接之第1晶片及第2晶片、以及設置於第1晶片及第2晶片之至少一者之第1電源電極及第2電源電極。第1晶片具備：複數個第1導電層，其等沿第1方向排列；半導體柱，其沿第1方向延伸，且與複數個第1導電層對向；複數個第1接點，其等沿第1方向延伸，且連接於複數個第1導電層；複數個第2接點，其等沿第1方向延伸，且連接於第1電源電極；複數個第3接點，其等沿第1方向延伸，且連接於第2電源電極；及複數個第1貼合電極，其等經由複數個第1接點而連接於複數個第1導電層。第2晶片具備：半導體基板，其具有與第1方向交叉之表面；複數個電晶體，其等設置於半導體基板之表面；複數個第4接點，其等沿第1方向延伸，且連接於複數個電晶體；及複數個第2貼合電極，其等經由複數個第4接點而連接於複數個電晶體。第1晶片及第2晶片係以複數個第1貼合電極與複數個第2貼合電極對向之方式配置，複數個第1貼合電極連接於複數個第2貼合電極。複數個第2接點與複數個第3接點對向。
接下來，參照圖式對實施方式之半導體記憶裝置詳細地進行說明。再者，以下之實施方式僅為一例，不以限定本發明為意圖而表示。
又，於本說明書中，將相對於半導體基板之表面平行之特定之方向稱為X方向，將相對於半導體基板之表面平行且與X方向垂直之方向稱為Y方向，將相對於半導體基板之表面垂直之方向稱為Z方向。
又，於本說明書中，有時將沿著特定之平面之方向稱為第1方向，將沿著該特定之平面與第1方向交叉之方向稱為第2方向，將與該特定之平面交叉之方向稱為第3方向。該等第1方向、第2方向及第3方向既可與X方向、Y方向及Z方向中之任一個對應，亦可不對應。
又，於本說明書中，「上」或「下」等表達以半導體基板為基準。例如，於上述第1方向與半導體基板之表面交叉之情形時，將沿著該第1方向自半導體基板離開之方向稱為上，將沿著第1方向靠近半導體基板之方向稱為下。又，於針對某構成表達為下表面或下端部之情形時，係指該構成之半導體基板側之面或端部，於表達為上表面或上端部之情形時，係指該構成之與半導體基板為相反側之面或端部。又，將與第2方向或第3方向交叉之面稱為側面等。
又，於本說明書中，表達為第1構成「電性連接」於第2構成之情形時，既可為第1構成直接連接於第2構成，亦可為第1構成經由配線、半導體構件或電晶體等而連接於第2構成。例如，於將3個電晶體串聯連接之情形時，即便第2個電晶體為斷開狀態，第1個電晶體亦「電性連接」於第3個電晶體。
又，於本說明書中，表達為電路等使2條配線等「導通」之情形時，例如有時指該電路等包含電晶體等，該電晶體等設置於2條配線間之電流路徑中，且該電晶體等成為接通狀態。
又，於本說明書中，表達為第1構成與第2構成「電性絕緣」之情形時，例如指如下狀態，即，於第1構成與第2構成之間設置有絕緣膜等，且未設置連接第1構成與第2構成之接點或配線等。
又，於本說明書中，表達為「場效型電晶體」或「場效電晶體」之情形時，係指具備作為通道區域發揮功能之半導體層、閘極絕緣膜及閘極電極之電晶體。
[第1實施方式]
以下，參照圖式，對第1實施方式之半導體記憶裝置之構成進行說明。再者，以下之圖式係模式性之圖，為了便於說明，有時省略一部分構成。
[記憶體系統MSY]
圖1係表示本實施方式之半導體記憶裝置之構成例之模式性側視圖。圖2係表示本實施方式之半導體記憶裝置之構成例之模式性俯視圖。
如圖1所示，本實施方式之記憶體系統MSY具備安裝基板MSB、積層於安裝基板MSB之複數個記憶體裸晶MD、及積層於記憶體裸晶MD之控制裸晶CD。該等構成係以形成於上表面之外部焊墊電極PX露出之方式於Y方向上錯開地積層，經由接著劑等而相互連接。
如圖2所示，安裝基板MSB、複數個記憶體裸晶MD及控制裸晶CD分別具備複數個外部焊墊電極PX。安裝基板MSB、複數個記憶體裸晶MD及控制裸晶CD上所設置之複數個外部焊墊電極PX分別經由接合線B而相互連接。
記憶體系統MSY例如係記憶體晶片、記憶卡或其他能夠記憶用戶資料之系統。
記憶體裸晶MD記憶用戶資料。複數個記憶體裸晶MD根據控制裸晶CD之控制信號，執行用戶資料之讀出動作、寫入動作或刪除動作等。
控制裸晶CD例如具備處理器、RAM(Random Access Memory，隨機存取記憶體)、ROM(Read Only Memory，唯讀記憶體)等，進行邏輯位址與實體位址之轉換、位元錯誤檢測/校正、耗損平均等處理。控制裸晶CD連接於複數個記憶體裸晶MD及主電腦等。
[記憶體裸晶MD]
圖3係表示本實施方式之半導體記憶裝置之構成例之模式性方塊圖。圖4係表示本實施方式之半導體記憶裝置之構成例之模式性電路圖。
如圖3所示，記憶體裸晶MD具備：記憶胞陣列MCA，其記憶資料；及周邊電路PC，其連接於記憶胞陣列MCA。
[記憶胞陣列MCA]
如圖4所示，記憶胞陣列MCA具備複數個記憶體區塊BLK。該等複數個記憶體區塊BLK分別具備複數個串單元SU。該等複數個串單元SU分別具備複數個記憶體串MS。該等複數個記憶體串MS之一端分別經由位元線BL連接於周邊電路PC。又，該等複數個記憶體串MS之另一端分別經由共通之配線SC及源極線SL連接於周邊電路PC。
記憶體串MS具備串聯連接於位元線BL與源極線SL之間之汲極選擇電晶體STD、複數個記憶胞MC及源極選擇電晶體STS。以下，有時將汲極選擇電晶體STD及源極選擇電晶體STS簡稱為選擇電晶體(STD、STS)。
記憶胞MC係具備作為通道區域發揮功能之半導體層、包含電荷儲存膜之閘極絕緣膜及閘極電極之場效型電晶體。記憶胞MC之閾值電壓根據電荷儲存膜中之電荷量而變化。記憶胞MC記憶1位元或複數位元之資料。再者，於與1個記憶體串MS對應之複數個記憶胞MC之閘極電極分別連接字元線WL。該等字元線WL分別共通連接於1個記憶體區塊BLK中之所有記憶體串MS。
選擇電晶體(STD、STS)係具備作為通道區域發揮功能之半導體層、閘極絕緣膜及閘極電極之場效型電晶體。於選擇電晶體(STD、STS)之閘極電極分別連接選擇閘極線(SGD、SGS)。汲極選擇線SGD對應於串單元SU而設置，且共通連接於1個串單元SU中之所有記憶體串MS。源極選擇線SGS共通連接於1個記憶體區塊BLK中之所有記憶體串MS。
[周邊電路PC]
如圖3所示，周邊電路PC具備列解碼器RD、感測放大器模組SAM、電壓產生電路VG及定序器SQC。又，周邊電路PC具備位址暫存器ADR、指令暫存器CMR、及狀態暫存器STR。又，周邊電路PC具備輸入輸出控制電路I/O與邏輯電路CTR。
列解碼器RD例如具備解碼電路及開關電路。解碼電路將位址暫存器ADR中保持之列位址RA解碼。開關電路根據解碼電路之輸出信號，使與列位址RA對應之字元線WL及選擇閘極線(SGD、SGS)與對應之電壓供給線導通。
感測放大器模組SAM具備與複數條位元線BL對應之複數個感測放大器電路、複數個電壓調整電路及複數個資料鎖存器。感測放大器電路根據位元線BL之電流或電壓，使表示記憶胞MC之接通/斷開之“H(High，高)”或“L(Low，低)”之資料鎖存於資料鎖存器中。電壓調整電路根據鎖存於資料鎖存器之資料，使位元線BL與對應之電壓供給線導通。
又，感測放大器模組SAM具備未圖示之解碼電路及開關電路。解碼電路將位址暫存器ADR中保持之行位址CA解碼。開關電路根據解碼電路之輸出信號，使與行位址CA對應之資料鎖存器與匯流排DB導通。
電壓產生電路VG例如具備連接於電源端子VCC、VSS之電荷泵電路等升壓電路、調節器等降壓電路、及未圖示之複數條電壓供給線。電壓產生電路VG根據來自定序器SQC之內部控制信號，產生在對於記憶胞陣列MCA之讀出動作、寫入動作及刪除動作時施加至位元線BL、源極線SL、字元線WL及選擇閘極線(SGD、SGS)之複數種動作電壓，並自複數條電壓供給線同時輸出。再者，電源端子VCC、VSS例如被分配給參照圖1、圖2所說明之複數個外部焊墊電極PX之一部分。對電源端子VCC供給電源電壓VC，對電源端子VSS供給接地電壓VS。
定序器SQC將指令暫存器CMR中保持之指令資料CMD依次解碼，並向列解碼器RD、感測放大器模組SAM及電壓產生電路VG輸出內部控制信號。又，定序器SQC適當將表示自身狀態之狀態資料STT輸出至狀態暫存器STR。
輸入輸出控制電路I/O具備資料輸入輸出端子I/O0～I/O7、連接於該等資料輸入輸出端子I/O0～I/O7之移位暫存器、及連接於該移位暫存器之緩衝記憶體。資料輸入輸出端子I/O0～I/O7例如被分配給參照圖1、圖2所說明之複數個外部焊墊電極PX之一部分。
緩衝記憶體根據來自邏輯電路CTR之內部控制信號，向感測放大器模組SAM內之資料鎖存器XDL、位址暫存器ADR或指令暫存器CMR輸出資料。又，根據來自邏輯電路CTR之內部控制信號，自資料鎖存器XDL或狀態暫存器STR輸入資料。再者，緩衝記憶體既可藉由上述移位暫存器之一部分而實現，亦可藉由SRAM(Static Random-Access Memory，靜態隨機存取記憶體)等構成而實現。
邏輯電路CTR經由外部控制端子/CEn、CLE、ALE、/WE、/RE自控制裸晶CD接收外部控制信號，並據此向輸入輸出控制電路I/O輸出內部控制信號。外部控制端子/CEn、CLE、ALE、/WE、/RE例如被分配給參照圖1、圖2所說明之複數個外部焊墊電極PX之一部分。
圖5係表示輸入輸出控制電路I/O之一部分構成之模式性電路圖。如上所述，複數個外部焊墊電極PX中之一部分分別作為電源端子VCC、VSS及資料輸入輸出端子I/On(n為0～7之自然數)發揮功能。電源端子VCC、VSS連接於輸入輸出控制電路I/O中之各構成，對該等構成供給電力。
輸入輸出控制電路I/O包含：資料輸出控制電路，其於輸出資料時自資料輸入輸出端子I/On輸出信號；及資料輸入控制電路，其於輸入資料時自資料輸入輸出端子I/On輸入信號。
資料輸出控制電路具備：上拉電路PU，其連接於電源端子VCC與資料輸入輸出端子I/On之間；及下拉電路PD，其連接於電源端子VSS與資料輸入輸出端子I/On之間。上拉電路PU包含並聯連接於電源端子VCC與資料輸入輸出端子I/On之間之K(K為自然數)個PMOS(P-channel Metal Oxide Semiconductor，P通道金屬氧化物半導體)電晶體。該等複數個PMOS電晶體之閘極電極分別連接於圖5之IO(Input/Output，輸入/輸出)電路中包含之上拉驅動電路之K個輸出端子。下拉電路PD包含並聯連接於電源端子VSS與資料輸入輸出端子I/On之間之L(L為自然數)個NMOS(N-channel Metal Oxide Semiconductor，N通道金屬氧化物半導體)電晶體。該等複數個NMOS電晶體之閘極電極分別連接於圖5之IO電路中包含之下拉驅動電路之L個輸出端子。於輸出資料時，根據輸出之資料，選擇性地驅動上拉電路PU或下拉電路PD，使資料輸入輸出端子I/On與電源端子VSS或電源端子VSS導通。此時，根據驅動時成為接通狀態之PMOS電晶體或NMOS電晶體之數量控制輸出阻抗。
資料輸入控制電路具備圖5之IO電路中包含之比較器。該比較器之一輸入端子連接於資料輸入輸出端子I/On，另一輸入端子連接於參考電壓供給線。於輸入資料時，例如，於資料輸入輸出端子I/On之電壓大於參考電壓之情形時，自比較器輸出“H”。又，例如，於資料輸入輸出端子I/On之電壓大於參考電壓之情形時，自比較器輸出“L”。
又，於電源端子VCC與電源端子VSS之間連接有電容元件Cap。電容元件Cap例如如下所述，作為使電源端子VCC與電源端子VSS之間之電壓即電源電壓於高速動作時亦穩定化之所謂旁路電容器發揮功能。
[記憶體裸晶MD之構成例]
圖6係表示本實施方式之半導體記憶裝置之構成例之模式性立體圖。如圖6所示，記憶體裸晶MD具備第1晶片C1與第2晶片C2。
以下，關於第1晶片C1，將設置複數個第1貼合電極PI1之面稱為正面，將設置複數個外部焊墊電極PX之面稱為背面。又，關於第2晶片C2，將設置複數個第2貼合電極PI2之面稱為正面，將正面之相反側之面稱為背面。第2晶片C2之正面設置於較第2晶片C2之背面更上方，第1晶片C1之背面設置於較第1晶片C1之正面更上方。
第1晶片C1及第2晶片C2係以第1晶片C1之正面與第2晶片C2之正面對向之方式配置。於第1晶片C1之背面設置複數個外部焊墊電極PX，於第1晶片C1之正面設置複數個第1貼合電極PI1。於第2晶片C2之正面設置複數個第2貼合電極PI2。複數個第1貼合電極PI1分別對應於複數個第2貼合電極PI2而設置，且配置於能夠與複數個第2貼合電極PI2貼合之位置。第1貼合電極PI1與第2貼合電極PI2作為用以將第1晶片C1與第2晶片C2貼合且使其電性導通之貼合電極發揮功能。第1貼合電極PI1與第2貼合電極PI2例如包含銅(Cu)等導電性材料。
再者，於圖6之例中，第1晶片C1之角部a1、a2、a3、a4分別與第2晶片C2之角部b1、b2、b3、b4對應。
圖7係表示第1晶片C1之構成例之模式性仰視圖。圖7右下方之由虛線包圍之部分表示設置有複數個第1貼合電極PI1之第1晶片C1之較正面更靠內部之構造。圖8係表示第2晶片C2之構成例之模式性俯視圖。圖8左下方之由虛線包圍之部分表示設置有複數個第2貼合電極PI2之第2晶片C2之較正面更靠內部之構造。圖9係與圖7之A1-A1'線及圖8之B1-B1'線對應之模式性剖視圖。圖10係與圖7之A2-A2'線及圖8之B2-B2'線對應之模式性剖視圖。圖9及圖10表示將圖7、圖8所示之構造沿著各線切斷並沿箭頭方向觀察時之剖面。
再者，圖7～圖10係表示模式性構成之圖，具體構成可適當變更。又，於圖7～圖10中，省略了一部分構成。
[第1晶片C1]  第1晶片C1例如如圖7所示，具備沿X及Y方向排列之4個記憶平面MP。記憶平面MP具備：區域R11，其供設置上述記憶胞陣列MCA；區域R12a，其設置於區域R11之X方向之一端側及另一端側；及區域R12b，其設置於區域R12a之X方向之一端側及另一端側。又，第1晶片C1具備相對於4個記憶平面MP設置於Y方向之一端側區域的區域R13。
又，第1晶片C1例如如圖9及圖10所示，具備基體層SBL、設置於基體層SBL下方之記憶體層ML、以及設置於記憶體層ML下方之複數個配線層M0、M1、M2。
基體層SBL具備：絕緣層100，其設置於第1晶片C1之背面；絕緣層101，其設置於絕緣層100之下方；N型井層102，其設置於絕緣層101之下方；及P型井層103，其設置於N型井層102之下方。絕緣層100例如係包含聚醯亞胺等絕緣材料之鈍化層。絕緣層101例如係包含氧化矽(SiO2 )等絕緣材料之絕緣層。N型井層102例如係包含含有磷(P)等N型雜質之矽(Si)之半導體層。P型井層103例如係包含含有硼(B)等P型雜質之矽(Si)之半導體層。P型井層103作為配線SC發揮功能。N型井層102及P型井層103介隔絕緣區域VZ按每一記憶平面MP(圖7)而分斷。
又，基體層SBL例如如圖10所示，具備設置於區域R13之背面配線MZ。背面配線MZ例如係包含鋁(Al)等導電性材料之配線層。背面配線MZ藉由絕緣層101而與N型井層102及P型井層103電性絕緣。又，背面配線MZ之一部分經由設置於絕緣層100之開口TV而露出至記憶體裸晶MD之外部，作為外部焊墊電極PX發揮功能。
再者，圖9等所示之基體層SBL之構成僅為例示，具體構成等可適當調整。例如基體層SBL亦可進而具備設置於絕緣層101與N型井層102之間之P型半導體區域。又，例如基體層SBL亦可不具備N型井層102。
又，於圖9等中，作為絕緣區域VZ，例示出設置於將記憶平面MP分斷之區域之構成。然而，絕緣區域VZ亦可設置於記憶平面MP外部之除此以外之區域。
記憶體層ML例如如圖10所示，具備設置於區域R11之記憶胞陣列MCA。記憶胞陣列MCA具備沿Y方向排列之複數個記憶體區塊BLK。於在Y方向上相鄰之2個記憶體區塊BLK之間設置沿X方向延伸之區塊間絕緣層ST。該等2個記憶體區塊BLK中包含之字元線WL經由區塊間絕緣層ST而電性絕緣。
記憶體區塊BLK具備沿Y方向排列之2個串單元SU、及設置於該等2個串單元SU之間之子區塊間絕緣層SHE。
串單元SU具備：複數個導電層110，其等設置於較P型井層103更下方；複數個半導體柱120；及未圖示之閘極絕緣膜，其分別設置於複數個導電層110與複數個半導體柱120之間。
導電層110係沿X及Y方向延伸之大致板狀之導電層，且沿Z方向排列。導電層110例如既可包含氮化鈦(TiN)及鎢(W)之積層膜等，亦可包含含有磷或硼等雜質之多晶矽等。又，於導電層110之間設置有氧化矽(SiO2 )等之絕緣層111。
複數個導電層110中位於最上方之一個或複數個導電層110作為源極選擇線SGS(圖4)及連接於其之複數個源極選擇電晶體STS(圖4)之閘極電極發揮功能。又，較之位於更下側之複數個導電層110作為字元線WL(圖4)及連接於其之複數個記憶胞MC(圖4)之閘極電極發揮功能。又，較之位於更下側之一個或複數個導電層110作為汲極選擇線SGD(圖4)及連接於其之複數個汲極選擇電晶體STD(圖4)之閘極電極發揮功能。
半導體柱120於X方向及Y方向上配設複數個。半導體柱120例如係非摻雜多晶矽(Si)等之半導體膜。半導體柱120例如具有大致圓筒狀之形狀，於中心部分設置有氧化矽等之絕緣膜。又，半導體柱120之外周面分別被導電層110包圍。半導體柱120分別作為1個記憶體串MS(圖4)中包含之複數個記憶胞MC及汲極選擇電晶體STD之通道區域發揮功能。半導體柱120之上端部經由非摻雜單晶矽等之半導體層而連接於P型井層103。半導體柱120之下端部經由含有磷(P)等N型雜質之半導體層、接點ch及接點cb而連接於位元線BL。
再者，於半導體柱120與導電層110之間設置未圖示之閘極絕緣膜。該閘極絕緣膜例如包含氮化矽(SiN)等之絕緣性電荷儲存膜或浮動閘極等之導電性電荷儲存膜。
於區塊間絕緣層ST之內部設置配線LI。配線LI例如既可包含含有磷(P)等N型雜質或硼(B)等P型雜質之半導體等，亦可含有鎢(W)等，還可含有矽化物等。配線LI作為源極線SL發揮功能。配線LI之上端部與P型井層103連接。配線LI之下端部經由接點、配線層M0等而連接於配線層M1內之配線。
又，記憶體層ML例如如圖9所示，具備設置於區域R12a之複數個字元線接點CC1。字元線接點CC1例如包含鎢(W)等導電性材料。字元線接點CC1沿Z方向延伸。字元線接點CC1之上端連接於導電層110之X方向之端部。字元線接點CC1之下端連接於配線層M0內之配線231。配線231分別經由配線層M1內之配線而連接於複數個第1貼合電極PI1。
又，記憶體層ML具備設置於區域R12b之氧化矽等之絕緣層220、及貫通絕緣層220之複數個貫通電極CC2、CC3。
複數個貫通電極CC2、CC3貫通絕緣層220而沿Z方向延伸。複數個貫通電極CC2及CC3例如包含鎢(W)等導電性材料。複數個貫通電極CC2、CC3之上端與設置於絕緣區域VZ之絕緣層100相接。複數個貫通電極CC2及CC3之下端分別經由配線層M0內之配線232、233而連接於複數個第1貼合電極PI1。
再者，如上所述，絕緣區域VZ亦可設置於將記憶平面MP分斷之區域以外。複數個貫通電極CC2、CC3亦可與設置於此種區域之絕緣區域VZ之絕緣層100相接。
又，複數個貫通電極CC2、CC3分別作為參照圖5所說明之電容元件Cap之一個及另一個電極發揮功能。即，複數個貫通電極CC2分別與複數個貫通電極CC3對向。又，貫通電極CC2、CC3分別經由配線232、233而連接於電源端子VSS、VCC。於半導體記憶裝置之動作時，經由電源端子VSS、VCC對貫通電極CC2、CC3供給接地電壓VS及電源電壓VC。
又，記憶體層ML例如如圖10所示，具備設置於區域R13之複數個貫通電極CC2、CC3、CC3'。如上所述，貫通電極CC2、CC3作為電容元件Cap之一部分發揮功能。貫通電極CC3'構成為與貫通電極CC3大致相同。但，貫通電極CC3'之上端連接於設置於絕緣區域VZ'之背面配線MZ。又，貫通電極CC3'之下端連接於配線層M0內之配線233。再者，雖然於圖10中省略圖示，但記憶體層ML具備連接於背面配線MZ及配線232之貫通電極。
配線層M0設置於記憶體層ML之下方。配線層M0例如係包含銅(Cu)等導電性材料之配線層。配線層M0例如包含位元線BL及上述配線231～233。配線層M1設置於配線層M0之下方。配線層M1例如係包含銅(Cu)或鋁(Al)等導電性材料之配線層。配線層M2設置於配線層M1之下方。配線層M2例如係包含銅(Cu)等導電性材料之配線層，具備複數個第1貼合電極PI1。
[第2晶片C2]  第2晶片C2例如如圖8所示，具備對應於記憶平面MP而沿X及Y方向排列之4個周邊電路區域PCA。周邊電路區域PCA具備：區域R21a、區域R21b，其等設置於與區域R11對向之區域且沿Y方向排列；區域R22a，其設置於與區域R12a對向之區域；及區域R22b，其設置於與區域R12b對向之區域。又，第2晶片C2具備設置於與區域R13對向之區域的區域R23。
又，第2晶片C2例如如圖9所示，具備：半導體基板Sb；電晶體層TL，其設置於半導體基板Sb之上方；及複數個配線層M'0、M'1、M'2、M'3、M'4，其等設置於電晶體層TL之上方。
半導體基板Sb例如具備：P型半導體區域300；N型井層301，其設置於P型半導體區域300之一部分之上方；及P型井層302，其設置於P型半導體區域300及N型井層301之一部分之上方。P型半導體區域300例如係含有硼(B)等P型雜質之單晶矽(Si)等之半導體區域。N型井層301例如係含有磷(P)等N型雜質之半導體區域。P型井層302例如係含有硼(B)等P型雜質之半導體區域。又，於半導體基板Sb之正面之一部分設置有氧化矽等之絕緣區域STI。
電晶體層TL具備設置於區域R21a、R21b之複數個電晶體310、及連接於該等複數個電晶體310之複數個接點311。該等複數個電晶體310及接點311中設置於區域R21a者構成參照圖3等所說明之感測放大器模組SAM。該等複數個電晶體310之至少一部分例如經由設置於區域R21a之第2貼合電極PI2及設置於區域R11之第1貼合電極PI1而連接於位元線BL。又，該等複數個電晶體310及接點311中設置於區域R21b者構成周邊電路PC之一部分。
再者，於圖9中，例示出將N型井層301設為通道區域之PMOS電晶體作為電晶體310。又，於圖10中，例示出將設置於P型半導體區域300之P型井層302設為通道區域之NMOS電晶體作為電晶體310。但，雖然省略圖示，但亦可於區域R21a、R21b中包含例如將P型半導體區域300設為通道區域之NMOS型之高耐壓電晶體。高耐壓電晶體與電晶體層TL中包含之一部分電晶體相比，具備更大之閘極長度及閘極寬度。又，高耐壓電晶體與電晶體層TL中包含之一部分電晶體相比，閘極絕緣膜之膜厚更大。
又，電晶體層TL例如如圖9所示，具備設置於區域R22a之複數個電晶體320、及連接於該等複數個電晶體320之複數個接點321。該等複數個電晶體320及接點321構成參照圖3等所說明之列解碼器RD中之開關電路。該等複數個電晶體320例如經由設置於區域R22a之第2貼合電極PI2及設置於區域R12a之第1貼合電極PI1而連接於複數個導電層110。
再者，於圖9中，例示出將P型半導體區域300設為通道區域之NMOS型之高耐壓電晶體作為電晶體320。但，雖然省略圖示，但亦可於區域R22a中包含例如將介隔N型井層301設置於P型半導體區域300之P型井層302設為通道區域之NMOS電晶體。
又，電晶體層TL具備設置於區域R22b之複數個電晶體330、及連接於該等複數個電晶體330之複數個接點331。該等複數個電晶體330及接點331構成參照圖3等所說明之列解碼器RD中之解碼電路。再者，列解碼器RD中之解碼電路例如亦可設置於區域R21a、R21b或其他區域。於此種情形時，亦可於區域R22b設置構成解碼電路以外之電路之電晶體。
再者，於圖9中，例示出將介隔N型井層301設置於P型半導體區域300之P型井層302設為通道區域之NMOS電晶體作為電晶體330。但，此種構成僅為例示，具體構成可適當調整。例如，電晶體330既可為將P型半導體區域300設為通道區域之NMOS電晶體，亦可為將N型井層301設為通道區域之PMOS電晶體。
又，電晶體層TL例如如圖10所示，具備設置於區域R23之複數個電晶體340、及連接於該等複數個電晶體340之複數個接點341。該等複數個電晶體340及接點341構成參照圖3等所說明之周邊電路PC之一部分。
再者，於圖10中，例示出將介隔N型井層301設置於P型半導體區域300之P型井層302設為通道區域之NMOS電晶體作為電晶體340。但，此種構成僅為例示，具體構成可適當調整。例如，電晶體340既可為將P型半導體區域300設為通道區域之NMOS電晶體，亦可為將N型井層301設為通道區域之PMOS電晶體。
再者，第1晶片C1中包含之上述貫通電極CC2、CC3、CC3'之Z方向上之長度較第2晶片C2中包含之接點311、321、331、341之Z方向上之長度大。
配線層M'0設置於電晶體層TL之上方。配線層M'0例如係包含鎢(W)等導電性材料之配線層。配線層M'1設置於配線層M'0之上方。配線層M'1例如係包含銅(Cu)等導電性材料之配線層。配線層M'2雖然於圖9及圖10中省略地表示，但設置於配線層M'1之上方。配線層M'2例如係包含銅(Cu)等導電性材料之配線層。配線層M'3例如係包含銅(Cu)或鋁(Al)等導電性材料之配線層。配線層M'4例如係包含銅(Cu)等導電性材料之配線層，具備複數個第2貼合電極PI2。
[製造方法]  接下來，參照圖11～圖17，對本實施方式之半導體記憶裝置之製造方法進行說明。圖11～圖17係表示本實施方式之半導體記憶裝置之製造方法之模式性剖視圖。圖11～圖17表示與圖10中之區域R13及區域R23之一部分對應之剖面。
如圖11所示，於該製造方法中，於基板Sb'上形成設置於第1晶片C1上之構成。又，於半導體基板Sb上形成設置於第2晶片C2上之構成。又，以第1晶片C1正面側與第2晶片C2正面側對向之方式配置基板Sb'及半導體基板Sb。
繼而，如圖12所示，將第1貼合電極PI1與第2貼合電極PI2接合，從而將該等構成貼合。該貼合步驟例如藉由對於貼合電極之直接接合法而進行。
繼而，如圖12所示，將基板Sb'去除。於該步驟中，既可將基板Sb'完全去除，亦可使基板Sb'之一部分殘留。該步驟例如藉由研削加工、化學機械研磨法(Chemical Mechanical Polishing：CMP)或併用其等之方法而進行。
繼而，如圖13所示，於圖12所示之構成之上表面，形成複數個開口VZa、VZ'a。開口VZa、VZ'a貫通N型井層102及P型井層103，使貫通電極CC2、CC3之上端露出。再者，一個開口VZa、VZ'a可與一個貫通電極CC2、CC3對應，亦可與複數個貫通電極CC2、CC3對應。該步驟例如藉由反應性離子蝕刻(Reactive Ion Etching：RIE)等進行。
繼而，如圖14所示，於複數個開口VZa、VZ'a之底面、內周面及圖13所示之構造之上表面，形成氧化矽等之絕緣層101。該步驟例如藉由化學氣相沈積法(Chemical Vapor Deposition：CVD)等進行。
繼而，如圖15所示，將複數個開口VZ'a之底面之絕緣層101去除，使複數個貫通電極CC3之下端部露出。於該步驟中，不使複數個開口VZa之底面露出。該步驟例如藉由基於RIE之回蝕等方法進行。
繼而，如圖16所示，於複數個開口VZ'a之底面、內周面及開口VZ'a之周邊部，形成背面配線MZ。該步驟例如藉由基於CVD之成膜及基於蝕刻等之形成而進行。
繼而，如圖17所示，於圖16所示之構造之上表面形成絕緣層100，於絕緣層100形成開口TV。該步驟例如藉由CVD及RIE等方法進行。
其後，藉由切割等將圖17所示之構成單片化。藉此，製造參照圖6～圖10所說明之半導體記憶裝置。
[效果]
伴隨半導體記憶裝置之介面速度之高速化，電源端子VCC、VSS之電壓變動不斷變大。於此種情形時，有可能無法對半導體記憶裝置之各構成穩定地供給電力，從而無法使半導體記憶裝置穩定地動作。為了抑制此種情況，例如，考慮增大連接於電源端子VCC、VSS之旁路電容器之電容。
因此，於本實施方式之半導體記憶裝置中，利用第1晶片C1之記憶體層ML中設置之貫通電極CC2、CC3，形成旁路電容器。
此處，由於在第1晶片C1之記憶體層ML設置記憶胞陣列MCA，故而記憶體層ML之Z方向之長度相對較大。因此，設置於記憶體層ML之貫通電極CC2、CC3之Z方向之長度亦相對較大。因此，藉由利用此種貫通電極CC2、CC3形成旁路電容器，可形成電容較大之旁路電容器。藉此，不會使半導體記憶裝置之動作不穩定化，且可謀求半導體記憶裝置之介面速度之高速化。
再者，為了形成電容器，例如亦可利用配線層中之配線或電晶體層TL中之電晶體之通道區域及閘極電極。然而，於欲使此種構成之電容器大電容化之情形時，必須縮小配線層中之配線之面積、或電晶體層TL中之電晶體之面積。
此處，於本實施方式中，於第1晶片C1之記憶體層ML中、供設置記憶胞陣列MCA等之區域以外之區域形成複數個貫通電極CC2、CC3，利用該貫通電極CC2、CC3形成電容元件Cap。根據此種構成，無須縮小配線或電晶體之面積。
又，構成電容元件Cap之貫通電極CC2、CC3可於形成將外部焊墊電極PX與配線層M0中之配線233連接之貫通電極CC3'時一起形成。因此，能夠於不增大製造成本之情況下實現。
[貫通電極CC2、CC3之構成例]
於上述例中，如圖18所示，貫通電極CC2、CC3之上端與絕緣層100相接。然而，此種構成僅為一例，具體構成可適當調整。
例如，亦可如圖19中例示般，貫通電極CC2、CC3之上端連接於配線432、433。配線432、433例如亦可與背面配線MZ同時形成。根據此種構成，例如，即便於配線232、432中之一條發生斷線之情形或配線233、433中之一條發生斷線之情形時，亦可藉由另一條配線實現電容元件Cap。因此，可使電容元件Cap穩定地動作。
又，例如，亦可如圖20中例示般，於第1晶片C1之P型井層103設置注入有磷(P)等n型雜質之n+區域440，將貫通電極CC2之上端連接於P型井層103，將貫通電極CC3之上端連接於P型井層103。根據此種構成，電容元件Cap除了具有貫通電極CC2、CC3之間之靜電電容以外，還具有P型井層103與n+區域440之間之寄生電容。因此，與僅由貫通電極CC2、CC3構成之電容元件Cap相比，可獲得更大之電容值。
[配線232、233、432、433之構成例]  圖21係表示配線232、233、432、433之一構成例之模式性XY剖視圖。圖21(a)表示配線232、233之構成。圖21(b)表示配線432、433之構成。
於圖21(a)之例中，配線232、233形成為梳狀。即，於圖21(a)之例中，沿Y方向延伸之複數個電極232a沿X方向排列。於複數個電極232a分別連接有沿Y方向排列成一行之複數個貫通電極CC2。又，於圖21(a)之例中，沿Y方向延伸之複數個電極233a沿X方向排列。於複數個電極233a分別連接有沿Y方向排列成一行之複數個貫通電極CC3。於在X方向上相鄰之2個電極232a之間分別設置有電極233a。又，複數個電極232a之Y方向之一端共通連接於沿X方向延伸之電極232b。同樣地，複數個電極233a之Y方向之一端共通連接於沿X方向延伸之電極233b。上述複數個電極232a、232b構成配線232。又，上述複數個電極233a、233b構成配線233。
於圖21(b)之例中，配線432、433形成為梳狀。即，於圖21(b)之例中，沿Y方向延伸之複數個電極432a沿X方向排列。於複數個電極432a分別連接有沿Y方向排列之複數個貫通電極CC2。又，於圖21(b)之例中，沿Y方向延伸之複數個電極433a沿X方向排列。於複數個電極433a分別連接有沿Y方向排列之複數個貫通電極CC3。於在X方向上相鄰之2個電極432a之間分別設置有電極433a。又，複數個電極432a之Y方向之一端共通連接於沿X方向延伸之電極432b。同樣地，複數個電極433a之Y方向之一端共通連接於沿X方向延伸之電極433b。上述複數個電極432a、432b構成配線432。又，上述複數個電極433a、433b構成配線433。
圖22係表示配線232、233之另一構成例之模式性XY剖視圖。再者，於圖22中表示配線232、233之構成例，配線432、433亦可具有如圖22所示之構成。
於圖22之例中，配線232、233形成為梳狀。即，於圖22之例中，沿Y方向延伸之複數個電極232a沿X方向排列。又，於圖22之例中，沿Y方向延伸之複數個電極233a沿X方向排列。於在X方向上相鄰之2個電極232a之間分別設置有電極233a。又，於在X方向上相鄰之電極232a、233a之間設置有沿Y方向交替地排列之複數個貫通電極CC2、CC3。複數個貫通電極CC2分別連接於電極232a。複數個貫通電極CC3分別連接於電極233a。又，複數個電極232a之Y方向之一端共通連接於沿X方向延伸之電極232b。同樣地，複數個電極233a之Y方向之一端共通連接於沿X方向延伸之電極233b。上述複數個電極232a、232b構成配線232。又，上述複數個電極233a、233b構成配線233。
[區域R12a、R22a之關係]  於圖9之例中，第1晶片C1之區域R12a設置於與第2晶片C2之區域R22a對向之區域，區域R12a之面積與區域R22a之面積為相同程度。然而，例如亦可如圖23所示，削減第1晶片C1之區域R12a中包含之構成之電路面積而使區域R12a之面積小於區域R22a之面積。藉此，可相對增大區域R12b之面積，使貫通電極CC2、CC3之數量增大，從而謀求電容元件Cap之大電容化。再者，於此種情形時，例如有如圖23所示，區域R12b之一部分與區域R22a對向之情形
[基體層SBL之構成例]  於圖10之例中，第1晶片C1之基體層SBL具備絕緣層100、絕緣層101、N型井層102及P型井層103。然而，此種構成僅為一例，具體構成可適當調整。
例如，圖24中例示之基體層SBL'具備自第1晶片C1之背面側依次設置之絕緣層100與絕緣層501。又，於基體層SBL'之區域R11設置導電層502、導電層503及導電層504。又，於區域R11以外之區域設置絕緣層505。
絕緣層501例如具備氧化矽或氮化矽等之絕緣性單層膜、或包含氧化矽及氮化矽等複數個絕緣膜之積層層。絕緣層501作為第1晶片C1之背面側之鈍化膜發揮功能。
導電層502、503、504作為半導體柱120之配線SC發揮功能。導電層502、503、504例如包含含有磷(P)等n型雜質之多晶矽等導電性材料。導電層503連接於半導體柱120之外周面。又，導電層502及導電層504分別連接於導電層503。
絕緣層505例如包含例如氧化矽(SiO2 )等絕緣材料。
又，例如圖25中例示之基體層SBL''基本上與圖24中例示之基體層SBL'同樣地構成。但，於圖25中例示之基體層SBL''之區域R11以外之區域未設置絕緣層505，代替絕緣層505而設置導電層502、積層膜511及導電層504。積層膜511例如包含氧化矽層、多晶矽層及氧化矽層。又，導電層502、導電層504及積層膜511經由氧化矽等之絕緣膜512而與貫通電極CC2、CC3絕緣。
[其他實施方式]
於以上之說明中，對利用貫通電極CC2、CC3形成旁路電容器之例進行了說明。然而，例如，亦可利用貫通電極CC2、CC3構成旁路電容器以外之電容器。例如，亦可利用貫通電極CC2、CC3構成電荷泵電路中之電容器。此處，例如如上所述，區域R12b設置於列解碼器RD之附近。又，於區域R13設置外部焊墊電極PX。因此，例如，亦可利用設置於區域R12b之複數個貫通電極CC2、CC3構成電荷泵中之電容器，利用設置於區域R13之複數個貫通電極CC2、CC3構成旁路電容器。
[其他]  已對本發明之若干實施方式進行了說明，但該等實施方式係作為示例而提出，並不意圖限定發明之範圍。該等新穎之實施方式能夠以其他多種形態實施，可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施方式或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請]  本申請享有以日本專利申請2019-169250號(申請日：2019年9月18日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
100:絕緣層 101:絕緣層 102:N型井層 103:P型井層 110:導電層 111:絕緣層 120:半導體柱 220:絕緣層 231:配線 232:配線 232a:電極 232b:電極 233:配線 233a:電極 233b:電極 300:P型半導體區域 301:N型井層 302:P型井層 310:電晶體 311:接點 320:電晶體 321:接點 330:電晶體 331:接點 340:電晶體 341:接點 432:配線 432a:電極 432b:電極 433:配線 433a:電極 433b:電極 440:n+區域 501:絕緣層 502:導電層 503:導電層 504:導電層 505:絕緣層 511:積層膜 512:絕緣膜 a1:角部 a2:角部 a3:角部 a4:角部 b1:角部 b2:角部 b3:角部 b4:角部 ADR:位址暫存器 ALE:外部控制端子 B:接合線 BL:位元線 BLK:記憶體區塊 C1:第1晶片 C2:第2晶片 CC1:字元線接點 CC2:貫通電極 CC3:貫通電極 CC3':貫通電極 cb:接點 ch:接點 CA:行位址 Cap:電容元件 CD:控制裸晶 CTR:邏輯電路 /CEn:外部控制端子 CLE:外部控制端子 CMD:指令資料 CMR:指令暫存器 DB:匯流排 /WE:外部控制端子 /RE:外部控制端子 I/O:輸入輸出控制電路 I/O0～I/O7:資料輸入輸出端子 I/On:資料輸入輸出端子 LI:配線 M0:配線層 M1:配線層 M2:配線層 M'0:配線層 M'1:配線層 M'2:配線層 M'3:配線層 M'4:配線層 MC:記憶胞 MD:記憶體裸晶 MCA:記憶胞陣列 ML:記憶體層 MP:記憶平面 MS:記憶體串 MSB:安裝基板 MSY:記憶體系統 MZ:背面配線 P:焊墊電極 PC:周邊電路 PCA:周邊電路區域 PD:下拉電路 PI1:第1貼合電極 PI2:第2貼合電極 PU:上拉電路 PX:外部焊墊電極 RA:列位址 RD:列解碼器 R11:區域 R12a:區域 R12b:區域 R13:區域 R21a:區域 R21b:區域 R22a:區域 R22b:區域 R23:區域 SAM:感測放大器模組 Sb:半導體基板 Sb':基板 SBL:基體層 SBL':基體層 SBL'':基體層 SC:配線 SGD:選擇閘極線 SGS:選擇閘極線 SHE:子區塊間絕緣層 SL:源極線 SQC:定序器 ST:區塊間絕緣層 STD:汲極選擇電晶體 STI:絕緣區域 STS:源極選擇電晶體 STT:狀態資料 STR:狀態暫存器 SU:串單元 TL:電晶體層 TV:開口 VC:電源電壓 VCC:電源端子 VG:電壓產生電路 VS:接地電壓 VSS:電源端子 VZ:絕緣區域 VZ':絕緣區域 VZa:開口 VZ'a:開口 WL:字元線 XDL:資料鎖存器
圖1係表示第1實施方式之半導體記憶裝置之構成例之模式性側視圖。  圖2係表示該構成例之模式性俯視圖。  圖3係表示該構成例之模式性方塊圖。  圖4係表示該構成例之模式性電路圖。  圖5係表示該構成例之模式性電路圖。  圖6係表示該構成例之模式性立體圖。  圖7係表示該構成例之模式性仰視圖。  圖8係表示該構成例之模式性俯視圖。  圖9係與圖7之A1-A1'線及圖8之B1-B1'線對應之模式性剖視圖。  圖10係與圖7之A2-A2'線及圖8之B2-B2'線對應之模式性剖視圖。  圖11～17係表示該半導體記憶裝置之製造方法之模式性剖視圖。  圖18係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖19係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖20係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖21(a)、(b)係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖22係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖23係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖24係表示該半導體記憶裝置之構成例之模式性剖視圖。  圖25係表示該半導體記憶裝置之構成例之模式性剖視圖。
100:絕緣層
101:絕緣層
102:N型井層
103:P型井層
110:導電層
111:絕緣層
120:半導體柱
220:絕緣層
231:配線
232:配線
233:配線
300:P型半導體區域
301:N型井層
302:P型井層
310:電晶體
311:接點
320:電晶體
321:接點
330:電晶體
331:接點
BL:位元線
C1:第1晶片
C2:第2晶片
CC1:字元線接點
CC2:貫通電極
CC3:貫通電極
cb:接點
ch:接點
M0:配線層
M1:配線層
M2:配線層
M'0:配線層
M'1:配線層
M'2:配線層
M'3:配線層
M'4:配線層
MCA:記憶胞陣列
ML:記憶體層
PI1:第1貼合電極
PI2:第2貼合電極
R11:區域
R12a:區域
R12b:區域
R21a:區域
R21b:區域
R22a:區域
R22b:區域
Sb:半導體基板
SBL:基體層
SGD:選擇閘極線
SGS:選擇閘極線
STI:絕緣區域
TL:電晶體層
VZ:絕緣區域

Claims (7)

  1. 一種半導體記憶裝置，其具備相互連接之第1晶片及第2晶片、以及設置於上述第1晶片及第2晶片之至少一者之第1電源電極及第2電源電極，  上述第1晶片具備：  複數個第1導電層，其等沿第1方向排列；  半導體柱，其沿上述第1方向延伸，且與上述複數個第1導電層對向；  複數個第1接點，其等沿上述第1方向延伸，且連接於上述複數個第1導電層；  複數個第2接點，其等沿上述第1方向延伸，且連接於上述第1電源電極；  複數個第3接點，其等沿上述第1方向延伸，且連接於上述第2電源電極；及  複數個第1貼合電極，其等經由上述複數個第1接點而連接於上述複數個第1導電層；  上述第2晶片具備：  半導體基板，其具有與上述第1方向交叉之表面；  複數個電晶體，其等設置於上述半導體基板之表面；  複數個第4接點，其等沿上述第1方向延伸，且連接於上述複數個電晶體；及  複數個第2貼合電極，其等經由上述複數個第4接點而連接於上述複數個電晶體；  上述第1晶片及上述第2晶片係以上述複數個第1貼合電極與上述複數個第2貼合電極對向之方式配置，上述複數個第1貼合電極連接於上述複數個第2貼合電極，且  上述複數個第2接點與上述複數個第3接點對向。
  2. 如請求項1之半導體記憶裝置，其中  上述複數個第2接點及上述複數個第3接點於上述第1方向上之長度，大於上述複數個第4接點於上述第1方向上之長度。
  3. 如請求項1之半導體記憶裝置，其中  上述第1電源電極可對上述複數個電晶體供給第1電壓，  上述第2電源電極可對上述複數個電晶體供給第2電壓，且  上述第2電壓大於上述第1電壓。
  4. 如請求項1之半導體記憶裝置，其中  上述第1晶片具備較所有的上述複數個第1導電層更遠離上述半導體基板之絕緣層，且  上述複數個第2接點及上述複數個第3接點之上述第1方向之一端連接於上述絕緣層。
  5. 如請求項1之半導體記憶裝置，其中  上述第1晶片具備較上述複數個第1導電層更遠離上述半導體基板之配線層，且  上述複數個第2接點及上述複數個第3接點之上述第1方向之一端連接於上述配線層中之配線。
  6. 如請求項1之半導體記憶裝置，其中  上述第1晶片具備較上述複數個第1導電層更遠離上述半導體基板之半導體層，且  上述複數個第2接點及上述複數個第3接點之上述第1方向之一端連接於上述半導體層。
  7. 如請求項1至6中任一項之半導體記憶裝置，其中  上述第1晶片具備：  第1區域，其供設置上述半導體柱；  第2區域，其供設置上述複數個第1接點及上述複數個第1貼合電極；及  第3區域，其供設置上述複數個第2接點及上述複數個第3接點；  上述第2晶片具備：  第4區域，其與上述第1區域對向；及  第5區域，其與上述第2區域對向，且包含上述複數個第2貼合電極及連接於上述複數個第1接點之複數個上述電晶體；  上述第2區域之面積小於上述第5區域之面積，且  上述第3區域之一部分與上述第5區域之一部分對向。
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