CN112530958B - 半导体存储装置 - Google Patents

半导体存储装置 Download PDF

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CN112530958B
CN112530958B CN202010587736.9A CN202010587736A CN112530958B CN 112530958 B CN112530958 B CN 112530958B CN 202010587736 A CN202010587736 A CN 202010587736A CN 112530958 B CN112530958 B CN 112530958B
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chip
electrodes
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CN112530958A (zh
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冈田信彬
内海哲章
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Kioxia Corp
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Kioxia Corp
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    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract

实施方式提供一种高速地动作的半导体存储装置。实施方式的半导体存储装置具备第1、第2芯片及第1、第2电源电极。第1芯片具备多个第1导电层、与它们对向的半导体柱、连接于多个第1导电层的多个第1接点、连接于第1电源电极的多个第2接点、连接于第2电源电极的多个第3接点、及连接于多个第1接点的多个第1贴合电极。第2芯片具备半导体衬底、设置在半导体衬底的多个晶体管、连接于多个晶体管的多个第4接点、及连接于多个第4接点的多个第2贴合电极。多个第2接点与多个第3接点对向。

Description

半导体存储装置
[相关申请]
本申请享有以日本专利申请2019-169250号(申请日：2019年9月18日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体存储装置。
背景技术
已知有具备相互连接的第1芯片及第2芯片的半导体存储装置。第1芯片具备：多个第1导电层，沿第1方向排列；半导体柱，沿第1方向延伸且与多个第1导电层对向；多个接点，沿第1方向延伸且连接于多个第1导电层；及多个第1贴合电极，经由所述多个接点连接于多个第1导电层。第2芯片具备：半导体衬底，具有与第1方向交叉的表面；多个晶体管，设置在半导体衬底；多个接点，沿第1方向延伸且连接于多个晶体管；及多个第2贴合电极，经由所述多个接点连接于多个晶体管。第1芯片及第2芯片是以多个第1贴合电极与多个第2贴合电极对向的方式配置，多个第1贴合电极连接于多个第2贴合电极。
发明内容
实施方式提供一种高速地动作的半导体存储装置。
一实施方式的半导体存储装置具备相互连接的第1芯片及第2芯片、以及设置在第1芯片及第2芯片的至少一者的第1电源电极及第2电源电极。第1芯片具备：多个第1导电层，沿第1方向排列；半导体柱，沿第1方向延伸，且与多个第1导电层对向；多个第1接点，沿第1方向延伸，且连接于多个第1导电层；多个第2接点，沿第1方向延伸，且连接于第1电源电极；多个第3接点，沿第1方向延伸，且连接于第2电源电极；及多个第1贴合电极，经由多个第1接点连接于多个第1导电层。第2芯片具备：半导体衬底，具有与第1方向交叉的表面；多个晶体管，设置在半导体衬底的表面；多个第4接点，沿第1方向延伸，且连接于多个晶体管；及多个第2贴合电极，经由多个第4接点连接于多个晶体管。第1芯片及第2芯片是以多个第1贴合电极与多个第2贴合电极对向的方式配置，多个第1贴合电极连接于多个第2贴合电极。多个第2接点与多个第3接点对向。
附图说明
图1是表示第1实施方式的半导体存储装置的构成例的示意性侧视图。
图2是表示该构成例的示意性俯视图。
图3是表示该构成例的示意性框图。
图4是表示该构成例的示意性电路图。
图5是表示该构成例的示意性电路图。
图6是表示该构成例的示意性立体图。
图7是表示该构成例的示意性仰视图。
图8是表示该构成例的示意性俯视图。
图9是与图7的A1-A1'线及图8的B1-B1'线对应的示意性剖视图。
图10是与图7的A2-A2'线及图8的B2-B2'线对应的示意性剖视图。
图11～17是表示该半导体存储装置的制造方法的示意性剖视图。
图18是表示该半导体存储装置的构成例的示意性剖视图。
图19是表示该半导体存储装置的构成例的示意性剖视图。
图20是表示该半导体存储装置的构成例的示意性剖视图。
图21(a)、(b)是表示该半导体存储装置的构成例的示意性剖视图。
图22是表示该半导体存储装置的构成例的示意性剖视图。
图23是表示该半导体存储装置的构成例的示意性剖视图。
图24是表示该半导体存储装置的构成例的示意性剖视图。
图25是表示该半导体存储装置的构成例的示意性剖视图。
具体实施方式
接下来，参照附图对实施方式的半导体存储装置详细地进行说明。此外，以下的实施方式仅为一例，不以限定本发明为意图而表示。
另外，在本说明书中，将相对于半导体衬底的表面平行的规定的方向称为X方向，将相对于半导体衬底的表面平行且与X方向垂直的方向称为Y方向，将相对于半导体衬底的表面垂直的方向称为Z方向。
另外，在本说明书中，有时将沿着规定的平面的方向称为第1方向，将沿着该规定的平面与第1方向交叉的方向称为第2方向，将与该规定的平面交叉的方向称为第3方向。这些第1方向、第2方向及第3方向既可与X方向、Y方向及Z方向中的任一个对应，也可不对应。
另外，在本说明书中，“上”或“下”等表达以半导体衬底为基准。例如，在所述第1方向与半导体衬底的表面交叉的情况下，将沿着该第1方向从半导体衬底离开的方向称为上，将沿着第1方向靠近半导体衬底的方向称为下。另外，在针对某构成表达为下表面或下端部的情况下，是指该构成的半导体衬底侧的面或端部，在表达为上表面或上端部的情况下，是指该构成的与半导体衬底为相反侧的面或端部。另外，将与第2方向或第3方向交叉的面称为侧面等。
另外，在本说明书中，表达为第1构成“电连接”于第2构成的情况下，既可为第1构成直接连接于第2构成，也可为第1构成经由配线、半导体部件或晶体管等而连接于第2构成。例如，在将3个晶体管串联连接的情况下，即使第2个晶体管为断开状态，第1个晶体管也“电连接”于第3个晶体管。
另外，在本说明书中，表达为电路等使2条配线等“导通”的情况下，例如有时指该电路等包含晶体管等，该晶体管等设置在2条配线间的电流路径中，且该晶体管等成为接通状态。
另外，在本说明书中，表达为第1构成与第2构成“电绝缘”的情况下，例如指如下状态，即，在第1构成与第2构成之间设置着绝缘膜等，且未设置连接第1构成与第2构成的接点或配线等。
另外，在本说明书中，表达为“场效应型晶体管”或“场效应晶体管”的情况下，是指具备作为通道区域发挥功能的半导体层、栅极绝缘膜及栅极电极的晶体管。
[第1实施方式]
以下，参照附图，对第1实施方式的半导体存储装置的构成进行说明。此外，以下的附图是示意性的图，为了便于说明，有时省略一部分构成。
[存储器系统MSY]
图1是表示本实施方式的半导体存储装置的构成例的示意性侧视图。图2是表示本实施方式的半导体存储装置的构成例的示意性俯视图。
如图1所示，本实施方式的存储器系统MSY具备安装衬底MSB、积层在安装衬底MSB的多个存储器裸片MD、及积层在存储器裸片MD的控制裸片CD。这些构成是以形成在上表面的外部焊盘电极PX露出的方式在Y方向上错开地积层，经由粘接剂等而相互连接。
如图2所示，安装衬底MSB、多个存储器裸片MD及控制裸片CD分别具备多个外部焊盘电极PX。安装衬底MSB、多个存储器裸片MD及控制裸片CD上所设置的多个外部焊盘电极PX分别经由键合线B而相互连接。
存储器系统MSY例如是存储器芯片、存储卡或其它能够存储用户数据的系统。
存储器裸片MD存储用户数据。多个存储器裸片MD根据控制裸片CD的控制信号，执行用户数据的读出动作、写入动作或删除动作等。
控制裸片CD例如具备处理器、RAM(Random Access Memory，随机存取存储器)、ROM(Read Only Memory，只读存储器)等，进行逻辑地址与物理地址的转换、比特差错检测/纠正、耗损平均等处理。控制裸片CD连接于多个存储器裸片MD及主机等。
[存储器裸片MD]
图3是表示本实施方式的半导体存储装置的构成例的示意性框图。图4是表示本实施方式的半导体存储装置的构成例的示意性电路图。
如图3所示，存储器裸片MD具备：存储单元阵列MCA，存储数据；及周边电路PC，连接于存储单元阵列MCA。
[存储单元阵列MCA]
如图4所示，存储单元阵列MCA具备多个存储块BLK。所述多个存储块BLK分别具备多个串单元SU。所述多个串单元SU分别具备多个存储器串MS。所述多个存储器串MS的一端分别经由位线BL连接于周边电路PC。另外，所述多个存储器串MS的另一端分别经由共通的配线SC及源极线SL连接于周边电路PC。
存储器串MS具备串联连接在位线BL及源极线SL之间的漏极选择晶体管STD、多个存储单元MC及源极选择晶体管STS。以下，有时将漏极选择晶体管STD及源极选择晶体管STS简称为选择晶体管(STD、STS)。
存储单元MC是具备作为通道区域发挥功能的半导体层、包含电荷蓄积膜的栅极绝缘膜及栅极电极的场效应型晶体管。存储单元MC的阈值电压根据电荷蓄积膜中的电荷量而变化。存储单元MC存储1比特或多比特的数据。此外，在与1个存储器串MS对应的多个存储单元MC的栅极电极分别连接字线WL。这些字线WL分别共通连接于1个存储块BLK中的所有存储器串MS。
选择晶体管(STD、STS)是具备作为通道区域发挥功能的半导体层、栅极绝缘膜及栅极电极的场效应型晶体管。在选择晶体管(STD、STS)的栅极电极分别连接选择栅极线(SGD、SGS)。漏极选择线SGD对应于串单元SU而设置，且共通连接于1个串单元SU中的所有存储器串MS。源极选择线SGS共通连接于1个存储块BLK中的所有存储器串MS。
[周边电路PC]
如图3所示，周边电路PC具备行解码器RD、感测放大器模块SAM、电压产生电路VG及定序器SQC。另外，周边电路PC具备地址寄存器ADR、指令寄存器CMR、及状态寄存器STR。另外，周边电路PC具备输入输出控制电路I/O与逻辑电路CTR。
行解码器RD例如具备解码电路及开关电路。解码电路将地址寄存器ADR中保存的行地址RA解码。开关电路根据解码电路的输出信号，使与行地址RA对应的字线WL及选择栅极线(SGD、SGS)与对应的电压供给线导通。
感测放大器模块SAM具备与多条位线BL对应的多个感测放大器电路、多个电压调整电路及多个数据锁存器。感测放大器电路根据位线BL的电流或电压，使表示存储单元MC的接通/断开的“H(High，高)”或“L(Low，低)”的数据锁存在数据锁存器中。电压调整电路根据锁存在数据锁存器的数据，使位线BL与对应的电压供给线导通。
另外，感测放大器模块SAM具备未图示的解码电路及开关电路。解码电路将地址寄存器ADR中保存的列地址CA解码。开关电路根据解码电路的输出信号，使与列地址CA对应的数据锁存器与总线DB导通。
电压产生电路VG例如具备连接于电源端子VCC、VSS的电荷泵电路等升压电路、调节器等降压电路、及未图示的多条电压供给线。电压产生电路VG根据来自定序器SQC的内部控制信号，产生在对于存储单元阵列MCA的读出动作、写入动作及删除动作时施加至位线BL、源极线SL、字线WL及选择栅极线(SGD、SGS)的多种动作电压，并从多条电压供给线同时输出。此外，电源端子VCC、VSS例如被分配给参照图1、图2所说明的多个外部焊盘电极PX的一部分。对电源端子VCC供给电源电压VC，对电源端子VSS供给接地电压VS。
定序器SQC将指令寄存器CMR中保存的指令数据CMD依次解码，并向行解码器RD、感测放大器模块SAM及电压产生电路VG输出内部控制信号。另外，定序器SQC适当将表示自身状态的状态数据STT输出至状态寄存器STR。
输入输出控制电路I/O具备数据输入输出端子I/O0～I/O7、连接于这些数据输入输出端子I/O0～I/O7的移位寄存器、及连接于该移位寄存器的缓冲存储器。数据输入输出端子I/O0～I/O7例如被分配给参照图1、图2所说明的多个外部焊盘电极PX的一部分。
缓冲存储器根据来自逻辑电路CTR的内部控制信号，向感测放大器模块SAM内的数据锁存器XDL、地址寄存器ADR或指令寄存器CMR输出数据。另外，根据来自逻辑电路CTR的内部控制信号，从数据锁存器XDL或状态寄存器STR输入数据。此外，缓冲存储器既可通过所述移位寄存器的一部分来实现，也可通过SRAM(Static Random-Access Memory，静态随机存取存储器)等构成来实现。
逻辑电路CTR经由外部控制端子/CEn、CLE、ALE、/WE、/RE从控制裸片CD接收外部控制信号，并据此向输入输出控制电路I/O输出内部控制信号。外部控制端子/CEn、CLE、ALE、/WE、/RE例如被分配给参照图1、图2所说明的多个外部焊盘电极PX的一部分。
图5是表示输入输出控制电路I/O的一部分构成的示意性电路图。如上所述，多个外部焊盘电极PX中的一部分分别作为电源端子VCC、VSS及数据输入输出端子I/On(n是0～7的自然数)发挥功能。电源端子VCC、VSS连接于输入输出控制电路I/O中的各构成，对这些构成供给电力。
输入输出控制电路I/O包含：数据输出控制电路，在输出数据时从数据输入输出端子I/On输出信号；及数据输入控制电路，在输入数据时从数据输入输出端子I/On输入信号。
数据输出控制电路具备：上拉电路PU，连接在电源端子VCC与数据输入输出端子I/On之间；及下拉电路PD，连接在电源端子VSS与数据输入输出端子I/On之间。上拉电路PU包含并联连接在电源端子VCC与数据输入输出端子I/On之间的K(K为自然数)个PMOS(P-channel Metal Oxide Semiconductor，P通道金属氧化物半导体)晶体管。所述多个PMOS晶体管的栅极电极分别连接于图5的IO(Input/Output，输入/输出)电路中包含的上拉驱动电路的K个输出端子。下拉电路PD包含并联连接在电源端子VSS与数据输入输出端子I/On之间的L(L为自然数)个NMOS(N-channel Metal Oxide Semiconductor，N通道金属氧化物半导体)晶体管。所述多个NMOS晶体管的栅极电极分别连接于图5的IO电路中包含的下拉驱动电路的L个输出端子。在输出数据时，根据输出的数据，选择性地驱动上拉电路PU或下拉电路PD，使数据输入输出端子I/On与电源端子VSS或电源端子VSS导通。此时，根据驱动时成为接通状态的PMOS晶体管或NMOS晶体管的数量控制输出阻抗。
数据输入控制电路具备图5的IO电路中包含的比较器。该比较器的一输入端子连接于数据输入输出端子I/On，另一输入端子连接于参考电压供给线。在输入数据时，例如，在数据输入输出端子I/On的电压大于参考电压的情况下，从比较器输出“H”。另外，例如，在数据输入输出端子I/On的电压大于参考电压的情况下，从比较器输出“L”。
另外，在电源端子VCC与电源端子VSS之间连接着电容元件Cap。电容元件Cap例如如下所述，作为使电源端子VCC与电源端子VSS之间的电压即电源电压在高速动作时也稳定化的所谓旁路电容器发挥功能。
[存储器裸片MD的构成例]
图6是表示本实施方式的半导体存储装置的构成例的示意性立体图。如图6所示，存储器裸片MD具备第1芯片C1与第2芯片C2。
以下，关于第1芯片C1，将设置多个第1贴合电极PI1的面称为正面，将设置多个外部焊盘电极PX的面称为背面。另外，关于第2芯片C2，将设置多个第2贴合电极PI2的面称为正面，将正面的相反侧的面称为背面。第2芯片C2的正面设置在比第2芯片C2的背面更上方，第1芯片C1的背面设置在比第1芯片C1的正面更上方。
第1芯片C1及第2芯片C2是以第1芯片C1的正面与第2芯片C2的正面对向的方式配置。在第1芯片C1的背面设置多个外部焊盘电极PX，在第1芯片C1的正面设置多个第1贴合电极PI1。在第2芯片C2的正面设置多个第2贴合电极PI2。多个第1贴合电极PI1分别对应于多个第2贴合电极PI2而设置，配置在能够与多个第2贴合电极PI2贴合的位置。第1贴合电极PI1与第2贴合电极PI2作为用来将第1芯片C1与第2芯片C2贴合且电导通的贴合电极发挥功能。第1贴合电极PI1与第2贴合电极PI2例如包含铜(Cu)等导电性材料。
此外，在图6的例子中，第1芯片C1的角部a1、a2、a3、a4分别与第2芯片C2的角部b1、b2、b3、b4对应。
图7是表示第1芯片C1的构成例的示意性仰视图。图7右下方的由虚线包围的部分表示设置着多个第1贴合电极PI1的第1芯片C1的比正面更靠内部的构造。图8是表示第2芯片C2的构成例的示意性俯视图。图8左下方的由虚线包围的部分表示设置着多个第2贴合电极PI2的第2芯片C2的比正面更靠内部的构造。图9是与图7的A1-A1'线及图8的B1-B1'线对应的示意性剖视图。图10是与图7的A2-A2'线及图8的B2-B2'线对应的示意性剖视图。图9及图10表示将图7、图8所示的构造沿着各线切断并沿箭头方向观察时的截面。
此外，图7～图10是表示示意性构成的图，具体构成可适当变更。另外，在图7～图10中，省略了一部分构成。
[第1芯片C1]
第1芯片C1例如如图7所示，具备沿X及Y方向排列的4个存储平面MP。存储平面MP具备：区域R11，设置所述存储单元阵列MCA；区域R12a，设置在区域R11的X方向的一端侧及另一端侧；及区域R12b，设置在区域R12a的X方向的一端侧及另一端侧。另外，第1芯片C1具备相对于4个存储平面MP设置在Y方向的一端侧的区域的区域R13。
另外，第1芯片C1例如如图9及图10所示，具备基体层SBL、设置在基体层SBL的下方的存储器层ML、以及设置在存储器层ML的下方的多个配线层M0、M1、M2。
基体层SBL具备：绝缘层100，设置在第1芯片C1的背面；绝缘层101，设置在绝缘层100的下方；N型阱层102，设置在绝缘层101的下方；及P型阱层103，设置在N型阱层102的下方。绝缘层100例如是包含聚酰亚胺等绝缘材料的钝化层。绝缘层101例如是包含氧化硅(SiO2)等绝缘材料的绝缘层。N型阱层102例如是包含含有磷(P)等N型杂质的硅(Si)的半导体层。P型阱层103例如是包含含有硼(B)等P型杂质的硅(Si)的半导体层。P型阱层103作为配线SC发挥功能。N型阱层102及P型阱层103介隔绝缘区域VZ针对每一存储平面MP(图7)而分断。
另外，基体层SBL例如如图10所示，具备设置在区域R13的背面配线MZ。背面配线MZ例如是包含铝(Al)等导电性材料的配线层。背面配线MZ通过绝缘层101而与N型阱层102及P型阱层103电绝缘。另外，背面配线MZ的一部分经由设置在绝缘层100的开口TV而露出到存储器裸片MD的外部，作为外部焊盘电极PX发挥功能。
此外，图9等所示的基体层SBL的构成仅为例示，具体构成等可适当调整。例如基体层SBL也可还具备设置在绝缘层101与N型阱层102之间的P型半导体区域。另外，例如基体层SBL也可不具备N型阱层102。
另外，在图9等中，例示出设置在将存储平面MP分断的区域的构成作为绝缘区域VZ。然而，绝缘区域VZ也可设置在存储平面MP外部的、除此以外的区域。
存储器层ML例如如图10所示，具备设置在区域R11的存储单元阵列MCA。存储单元阵列MCA具备沿Y方向排列的多个存储块BLK。于在Y方向上相邻的2个存储块BLK之间设置沿X方向延伸的块间绝缘层ST。所述2个存储块BLK中包含的字线WL经由块间绝缘层ST而电绝缘。
存储块BLK具备沿Y方向排列的2个串单元SU、及设置在所述2个串单元SU之间的子块间绝缘层SHE。
串单元SU具备：多个导电层110，设置在比P型阱层103更下方；多个半导体柱120；及未图示的栅极绝缘膜，分别设置在多个导电层110与多个半导体柱120之间。
导电层110是沿X及Y方向延伸的大致板状的导电层，且沿Z方向排列。导电层110例如既可包含氮化钛(TiN)及钨(W)的积层膜等，也可包含含有磷或硼等杂质的多晶硅等。另外，在导电层110之间设置着氧化硅(SiO2)等的绝缘层111。
多个导电层110中位于最上方的一个或多个导电层110作为源极选择线SGS(图4)及连接于源极选择线SGS的多个源极选择晶体管STS(图4)的栅极电极发挥功能。另外，较之位于更下侧的多个导电层110作为字线WL(图4)及连接于字线WL的多个存储单元MC(图4)的栅极电极发挥功能。另外，较之位于更下侧的一个或多个导电层110作为漏极选择线SGD(图4)及连接于漏极选择线SGD的多个漏极选择晶体管STD(图4)的栅极电极发挥功能。
半导体柱120在X方向及Y方向上配设多个。半导体柱120例如是非掺杂多晶硅(Si)等的半导体膜。半导体柱120例如具有大致圆筒状的形状，在中心部分设置着氧化硅等的绝缘膜。另外，半导体柱120的外周面分别被导电层110包围。半导体柱120分别作为1个存储器串MS(图4)中包含的多个存储单元MC及漏极选择晶体管STD的通道区域发挥功能。半导体柱120的上端部经由非掺杂单晶硅等的半导体层而连接于P型阱层103。半导体柱120的下端部经由含有磷(P)等N型杂质的半导体层、接点ch及接点cb而连接于位线BL。
此外，在半导体柱120与导电层110之间设置未图示的栅极绝缘膜。该栅极绝缘膜例如包含氮化硅(SiN)等的绝缘性电荷蓄积膜或浮动栅极等的导电性电荷蓄积膜。
在块间绝缘层ST的内部设置配线LI。配线LI例如既可包含含有磷(P)等N型杂质或硼(B)等P型杂质的半导体等，也可含有钨(W)等，还可含有硅化物等。配线LI作为源极线SL发挥功能。配线LI的上端部与P型阱层103连接。配线LI的下端部经由接点、配线层M0等而连接于配线层M1内的配线。
另外，存储器层ML例如如图9所示，具备设置在区域R12a的多个字线接点CC1。字线接点CC1例如包含钨(W)等导电性材料。字线接点CC1沿Z方向延伸。字线接点CC1的上端连接于导电层110的X方向的端部。字线接点CC1的下端连接于配线层M0内的配线231。配线231分别经由配线层M1内的配线而连接于多个第1贴合电极PI1。
另外，存储器层ML具备设置在区域R12b的氧化硅等的绝缘层220、及贯通绝缘层220的多个贯通电极CC2、CC3。
多个贯通电极CC2、CC3贯通绝缘层220而沿Z方向延伸。多个贯通电极CC2及CC3例如包含钨(W)等导电性材料。多个贯通电极CC2、CC3的上端与设置在绝缘区域VZ的绝缘层100相接。多个贯通电极CC2及CC3的下端分别经由配线层M0内的配线232、233而连接于多个第1贴合电极PI1。
此外，如上所述，绝缘区域VZ也可设置在将存储平面MP分断的区域以外。多个贯通电极CC2、CC3也可与设置在这种区域的绝缘区域VZ的绝缘层100相接。
另外，多个贯通电极CC2、CC3分别作为参照图5所说明的电容元件Cap的一个及另一个电极发挥功能。也就是说，多个贯通电极CC2分别与多个贯通电极CC3对向。另外，贯通电极CC2、CC3分别经由配线232、233而连接于电源端子VSS、VCC。在半导体存储装置动作时，经由电源端子VSS、VCC对贯通电极CC2、CC3供给接地电压VS及电源电压VC。
另外，存储器层ML例如如图10所示，具备设置在区域R13的多个贯通电极CC2、CC3、CC3'。如上所述，贯通电极CC2、CC3作为电容元件Cap的一部分发挥功能。贯通电极CC3'构成为与贯通电极CC3大致相同。但是，贯通电极CC3'的上端连接于设置在绝缘区域VZ'的背面配线MZ。另外，贯通电极CC3'的下端连接于配线层M0内的配线233。此外，虽然在图10中省略图示，但存储器层ML具备连接于背面配线MZ及配线232的贯通电极。
配线层M0设置在存储器层ML的下方。配线层M0例如是包含铜(Cu)等导电性材料的配线层。配线层M0例如包含位线BL及所述配线231～233。配线层M1设置在配线层M0的下方。配线层M1例如是包含铜(Cu)或铝(Al)等导电性材料的配线层。配线层M2设置在配线层M1的下方。配线层M2例如是包含铜(Cu)等导电性材料的配线层，具备多个第1贴合电极PI1。
[第2芯片C2]
第2芯片C2例如如图8所示，具备对应于存储平面MP而沿X及Y方向排列的4个周边电路区域PCA。周边电路区域PCA具备：区域R21a、区域R21b，设置在与区域R11对向的区域且沿Y方向排列；区域R22a，设置在与区域R12a对向的区域；及区域R22b，设置在与区域R12b对向的区域。另外，第2芯片C2具备设置在与区域R13对向的区域的区域R23。
另外，第2芯片C2例如如图9所示，具备：半导体衬底Sb；晶体管层TL，设置在半导体衬底Sb的上方；及多个配线层M'0、M'1、M'2、M'3、M'4，设置在晶体管层TL的上方。
半导体衬底Sb例如具备：P型半导体区域300；N型阱层301，设置在P型半导体区域300的一部分的上方；及P型阱层302，设置在P型半导体区域300及N型阱层301的一部分的上方。P型半导体区域300例如是含有硼(B)等P型杂质的单晶硅(Si)等的半导体区域。N型阱层301例如是含有磷(P)等N型杂质的半导体区域。P型阱层302例如是含有硼(B)等P型杂质的半导体区域。另外，在半导体衬底Sb的正面的一部分设置着氧化硅等的绝缘区域STI。
晶体管层TL具备设置在区域R21a、R21b的多个晶体管310、及连接于所述多个晶体管310的多个接点311。所述多个晶体管310及接点311中，设置在区域R21a的晶体管310及接点311构成参照图3等所说明的感测放大器模块SAM。所述多个晶体管310的至少一部分例如经由设置在区域R21a的第2贴合电极PI2及设置在区域R11的第1贴合电极PI1而连接于位线BL。另外，所述多个晶体管310及接点311中，设置在区域R21b的晶体管310及接点311构成周边电路PC的一部分。
此外，在图9中，例示出将N型阱层301设为通道区域的PMOS晶体管作为晶体管310。另外，在图10中，例示出将设置在P型半导体区域300的P型阱层302设为通道区域的NMOS晶体管作为晶体管310。但是，虽然省略图示，但也可在区域R21a、R21b中包含例如将P型半导体区域300设为通道区域的NMOS型的高耐压晶体管。高耐压晶体管与晶体管层TL中包含的一部分晶体管相比，具备更大的栅极长度及栅极宽度。另外，高耐压晶体管与晶体管层TL中包含的一部分晶体管相比，栅极绝缘膜的膜厚更大。
另外，晶体管层TL例如如图9所示，具备设置在区域R22a的多个晶体管320、及连接于所述多个晶体管320的多个接点321。所述多个晶体管320及接点321构成参照图3等所说明的行解码器RD中的开关电路。所述多个晶体管320例如经由设置在区域R22a的第2贴合电极PI2及设置在区域R12a的第1贴合电极PI1而连接于多个导电层110。
此外，在图9中，例示出将P型半导体区域300设为通道区域的NMOS型的高耐压晶体管作为晶体管320。但是，虽然省略图示，但也可在区域R22a中包含例如将介隔N型阱层301设置在P型半导体区域300的P型阱层302设为通道区域的NMOS晶体管。
另外，晶体管层TL具备设置在区域R22b的多个晶体管330、及连接于所述多个晶体管330的多个接点331。所述多个晶体管330及接点331构成参照图3等所说明的行解码器RD中的解码电路。此外，行解码器RD中的解码电路例如也可设置在区域R21a、R21b或其它区域。这种情况下，也可在区域R22b设置构成解码电路以外的电路的晶体管。
此外，在图9中，例示出将介隔N型阱层301设置在P型半导体区域300的P型阱层302设为通道区域的NMOS晶体管作为晶体管330。但是，这种构成仅为例示，具体构成可适当调整。例如，晶体管330既可为将P型半导体区域300设为通道区域的NMOS晶体管，也可为将N型阱层301设为通道区域的PMOS晶体管。
另外，晶体管层TL例如如图10所示，具备设置在区域R23的多个晶体管340、及连接于所述多个晶体管340的多个接点341。所述多个晶体管340及接点341构成参照图3等所说明的周边电路PC的一部分。
此外，在图10中，例示出将介隔N型阱层301设置在P型半导体区域300的P型阱层302设为通道区域的NMOS晶体管作为晶体管340。但是，这种构成仅为例示，具体构成可适当调整。例如，晶体管340既可为将P型半导体区域300设为通道区域的NMOS晶体管，也可为将N型阱层301设为通道区域的PMOS晶体管。
此外，第1芯片C1中包含的所述贯通电极CC2、CC3、CC3'的Z方向上的长度比第2芯片C2中包含的接点311、321、331、341的Z方向上的长度大。
配线层M'0设置在晶体管层TL的上方。配线层M'0例如是包含钨(W)等导电性材料的配线层。配线层M'1设置在配线层M'0的上方。配线层M'1例如是包含铜(Cu)等导电性材料的配线层。配线层M'2虽然在图9及图10中省略地表示，但设置在配线层M'1的上方。配线层M'2例如是包含铜(Cu)等导电性材料的配线层。配线层M'3例如是包含铜(Cu)或铝(Al)等导电性材料的配线层。配线层M'4例如是包含铜(Cu)等导电性材料的配线层，具备多个第2贴合电极PI2。
[制造方法]
接下来，参照图11～图17，对本实施方式的半导体存储装置的制造方法进行说明。图11～图17是表示本实施方式的半导体存储装置的制造方法的示意性剖视图。图11～图17表示与图10中的区域R13及区域R23的一部分对应的截面。
如图11所示，在该制造方法中，在衬底Sb'上形成设置在第1芯片C1上的构成。另外，在半导体衬底Sb上形成设置在第2芯片C2上的构成。另外，以第1芯片C1正面侧与第2芯片C2正面侧对向的方式配置衬底Sb'及半导体衬底Sb。
接着，如图12所示，将第1贴合电极PI1与第2贴合电极PI2接合，从而将这些构成贴合。该贴合步骤例如通过对于贴合电极的直接接合法来进行。
接着，如图12所示，将衬底Sb'去除。在该步骤中，既可将衬底Sb'完全去除，也可使衬底Sb'的一部分残留。该步骤例如通过研削加工、化学机械研磨法(Chemical MechanicalPolishing：CMP)或并用研削加工及化学机械研磨法的方法来进行。
接着，如图13所示，在图12所示的构成的上表面形成多个开口VZa、VZ'a。开口VZa、VZ'a贯通N型阱层102及P型阱层103，使贯通电极CC2、CC3的上端露出。此外，一个开口VZa、VZ'a既可与一个贯通电极CC2、CC3对应，也可与多个贯通电极CC2、CC3对应。该步骤例如通过反应性离子蚀刻(Reactive Ion Etching：RIE)等进行。
接着，如图14所示，在多个开口VZa、VZ'a的底面、内周面及图13所示的构造的上表面形成氧化硅等的绝缘层101。该步骤例如通过化学气相沉积法(Chemical VaporDeposition：CVD)等进行。
接着，如图15所示，将多个开口VZ'a的底面的绝缘层101去除，使多个贯通电极CC3的下端部露出。在该步骤中，不使多个开口VZa的底面露出。该步骤例如通过基于RIE的回蚀等方法进行。
接着，如图16所示，在多个开口VZ'a的底面、内周面及开口VZ'a的周边部形成背面配线MZ。该步骤例如通过基于CVD的成膜及基于蚀刻等的形成来进行。
接着，如图17所示，在图16所示的构造的上表面形成绝缘层100，在绝缘层100形成开口TV。该步骤例如通过CVD及RIE等方法进行。
然后，通过切割等将图17所示的构成单片化。由此，制造参照图6～图10所说明的半导体存储装置。
[效果]
伴随半导体存储装置的接口速度的高速化，电源端子VCC、VSS的电压的变动正在变大。这种情况下，有无法对半导体存储装置的各构成稳定地供给电力，从而无法使半导体存储装置稳定地动作的情况。为了抑制这种情况，例如，考虑增大连接于电源端子VCC、VSS的旁路电容器的电容。
因此，在本实施方式的半导体存储装置中，利用第1芯片C1的存储器层ML中设置的贯通电极CC2、CC3，形成旁路电容器。
此处，由于在第1芯片C1的存储器层ML设置存储单元阵列MCA，所以，存储器层ML的Z方向的长度相对较大。因此，设置在存储器层ML的贯通电极CC2、CC3的Z方向的长度也相对较大。因此，通过利用这种贯通电极CC2、CC3形成旁路电容器，能够形成电容较大的旁路电容器。由此，不会使半导体存储装置的动作不稳定化，且可谋求半导体存储装置的接口速度的高速化。
此外，为了形成电容器，例如也可利用配线层中的配线或晶体管层TL中的晶体管的通道区域及栅极电极。然而，在想要使这种构成的电容器大电容化的情况下，必须缩小配线层中的配线的面积或晶体管层TL中的晶体管的面积。
此处，在本实施方式中，在第1芯片C1的存储器层ML中设置存储单元阵列MCA等的区域以外的区域形成多个贯通电极CC2、CC3，利用该贯通电极CC2、CC3形成电容元件Cap。根据这种构成，无须缩小配线或晶体管的面积。
另外，构成电容元件Cap的贯通电极CC2、CC3可在形成将外部焊盘电极PX与配线层M0中的配线233连接的贯通电极CC3'时一起形成。因此，能够在不增大制造成本的情况下实现。
[贯通电极CC2、CC3的构成例]
在所述例子中，如图18所示，贯通电极CC2、CC3的上端与绝缘层100相接。然而，这种构成只不过为一例，具体构成可适当调整。
例如，也可像图19中例示的那样，贯通电极CC2、CC3的上端连接于配线432、433。配线432、433例如也可与背面配线MZ同时形成。根据这种构成，例如，即使在配线232、432中的一条发生断线的情况或配线233、433中的一条发生断线的情况下，也可通过另一条配线实现电容元件Cap。因此，能够使电容元件Cap稳定地动作。
另外，例如，也可像图20中例示的那样，在第1芯片C1的P型阱层103设置注入有磷(P)等n型杂质的n+区域440，将贯通电极CC2的上端连接于P型阱层103，将贯通电极CC3的上端连接于P型阱层103。根据这种构成，电容元件Cap除了具有贯通电极CC2、CC3之间的静电电容以外，还具有P型阱层103与n+区域440之间的寄生电容。因此，与仅由贯通电极CC2、CC3构成的电容元件Cap相比，可获得更大的电容值。
[配线232、233、432、433的构成例]
图21是表示配线232、233、432、433的一构成例的示意性XY剖视图。图21(a)表示配线232、233的构成。图21(b)表示配线432、433的构成。
在图21(a)的例子中，配线232、233形成为梳状。也就是说，在图21(a)的例子中，沿Y方向延伸的多个电极232a沿X方向排列。在多个电极232a分别连接着沿Y方向排成一排的多个贯通电极CC2。另外，在图21(a)的例子中，沿Y方向延伸的多个电极233a沿X方向排列。在多个电极233a分别连接着沿Y方向排成一排的多个贯通电极CC3。于在X方向上相邻的2个电极232a之间分别设置着电极233a。另外，多个电极232a的Y方向的一端共通连接于沿X方向延伸的电极232b。同样地，多个电极233a的Y方向的一端共通连接于沿X方向延伸的电极233b。所述多个电极232a、232b构成配线232。另外，所述多个电极233a、233b构成配线233。
在图21(b)的例子中，配线432、433形成为梳状。也就是说，在图21(b)的例子中，沿Y方向延伸的多个电极432a沿X方向排列。在多个电极432a分别连接着沿Y方向排列的多个贯通电极CC2。另外，在图21(b)的例子中，沿Y方向延伸的多个电极433a沿X方向排列。在多个电极433a分别连接着沿Y方向排列的多个贯通电极CC3。于在X方向上相邻的2个电极432a之间分别设置着电极433a。另外，多个电极432a的Y方向的一端共通连接于沿X方向延伸的电极432b。同样地，多个电极433a的Y方向的一端共通连接于沿X方向延伸的电极433b。所述多个电极432a、432b构成配线432。另外，所述多个电极433a、433b构成配线433。
图22是表示配线232、233的另一构成例的示意性XY剖视图。此外，在图22中表示配线232、233的构成例，配线432、433也可具有如图22所示的构成。
在图22的例子中，配线232、233形成为梳状。也就是说，在图22的例子中，沿Y方向延伸的多个电极232a沿X方向排列。另外，在图22的例子中，沿Y方向延伸的多个电极233a沿X方向排列。于在X方向上相邻的2个电极232a之间分别设置着电极233a。另外，于在X方向上相邻的电极232a、233a之间设置着沿Y方向交替地排列的多个贯通电极CC2、CC3。多个贯通电极CC2分别连接于电极232a。多个贯通电极CC3分别连接于电极233a。另外，多个电极232a的Y方向的一端共通连接于沿X方向延伸的电极232b。同样地，多个电极233a的Y方向的一端共通连接于沿X方向延伸的电极233b。所述多个电极232a、232b构成配线232。另外，所述多个电极233a、233b构成配线233。
[区域R12a、R22a的关系]
在图9的例子中，第1芯片C1的区域R12a设置在与第2芯片C2的区域R22a对向的区域，区域R12a的面积与区域R22a的面积为相同程度。然而，例如也可如图23所示，削减第1芯片C1的区域R12a中包含的构成的电路面积而使区域R12a的面积小于区域R22a的面积。由此，能够相对增大区域R12b的面积，使贯通电极CC2、CC3的数量增大，从而谋求电容元件Cap的大电容化。此外，这种情况下，例如有如图23所示，区域R12b的一部分与区域R22a对向的情况。
[基体层SBL的构成例]
在图10的例子中，第1芯片C1的基体层SBL具备绝缘层100、绝缘层101、N型阱层102及P型阱层103。然而，这种构成只不过为一例，具体构成可适当调整。
例如，图24中例示的基体层SBL'具备从第1芯片C1的背面侧依次设置的绝缘层100与绝缘层501。另外，在基体层SBL'的区域R11设置导电层502、导电层503及导电层504。另外，在区域R11以外的区域设置绝缘层505。
绝缘层501例如具备氧化硅或氮化硅等的绝缘性单层膜、或包含氧化硅及氮化硅等多个绝缘膜的积层层。绝缘层501作为第1芯片C1的背面侧的钝化膜发挥功能。
导电层502、503、504作为半导体柱120的配线SC发挥功能。导电层502、503、504例如包含含有磷(P)等n型杂质的多晶硅等导电性材料。导电层503连接于半导体柱120的外周面。另外，导电层502及导电层504分别连接于导电层503。
绝缘层505例如包含例如氧化硅(SiO2)等绝缘材料。
另外，例如图25中例示的基体层SBL”基本上与图24中例示的基体层SBL'同样地构成。但是，在图25中例示的基体层SBL”的区域R11以外的区域未设置绝缘层505，代替绝缘层505而设置导电层502、积层膜511及导电层504。积层膜511例如包含氧化硅层、多晶硅层及氧化硅层。另外，导电层502、导电层504及积层膜511经由氧化硅等的绝缘膜512而与贯通电极CC2、CC3绝缘。
[其它实施方式]
在以上的说明中，对利用贯通电极CC2、CC3形成旁路电容器的例子进行了说明。然而，例如，也可利用贯通电极CC2、CC3构成旁路电容器以外的电容器。例如，也可利用贯通电极CC2、CC3构成电荷泵电路中的电容器。此处，例如如上所述，区域R12b设置在行解码器RD的附近。另外，在区域R13设置外部焊盘电极PX。因此，例如，也可利用设置在区域R12b的多个贯通电极CC2、CC3构成电荷泵中的电容器，利用设置在区域R13的多个贯通电极CC2、CC3构成旁路电容器。
[其它]
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新颖的实施方式能以其它多种方式实施，能够在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
MC 存储单元
MCA 存储单元阵列
PC 周边电路
P 焊盘电极

Claims (7)

1.一种半导体存储装置，具备相互连接的第1芯片及第2芯片、以及设置在所述第1芯片及第2芯片的至少一者的第1电源电极及第2电源电极，
所述第1芯片具备：
多个第1导电层，沿第1方向排列；
半导体柱，沿所述第1方向延伸，且与所述多个第1导电层对向；
多个第1接点，沿所述第1方向延伸，且连接于所述多个第1导电层；
多个第2接点，沿所述第1方向延伸，且连接于所述第1电源电极；
多个第3接点，沿所述第1方向延伸，且连接于所述第2电源电极；及
多个第1贴合电极，经由所述多个第1接点连接于所述多个第1导电层；
所述第2芯片具备：
半导体衬底，具有与所述第1方向交叉的表面；
多个晶体管，设置在所述半导体衬底的表面；
多个第4接点，沿所述第1方向延伸，且连接于所述多个晶体管；及
多个第2贴合电极，经由所述多个第4接点连接于所述多个晶体管；
所述第1芯片及所述第2芯片是以所述多个第1贴合电极与所述多个第2贴合电极对向的方式配置，所述多个第1贴合电极连接于所述多个第2贴合电极，且
所述多个第2接点与所述多个第3接点对向。
2.根据权利要求1所述的半导体存储装置，其中
所述多个第2接点及所述多个第3接点在所述第1方向上的长度比所述多个第4接点在所述第1方向上的长度大。
3.根据权利要求1所述的半导体存储装置，其中
所述第1电源电极能够对所述多个晶体管供给第1电压，
所述第2电源电极能够对所述多个晶体管供给第2电压，且
所述第2电压大于所述第1电压。
4.根据权利要求1所述的半导体存储装置，其中
所述第1芯片具备比所有所述多个第1导电层更远离所述半导体衬底的绝缘层，且
所述多个第2接点及所述多个第3接点的所述第1方向的一端连接于所述绝缘层。
5.根据权利要求1所述的半导体存储装置，其中
所述第1芯片具备比所述多个第1导电层更远离所述半导体衬底的配线层，且
所述多个第2接点及所述多个第3接点的所述第1方向的一端连接于所述配线层中的配线。
6.根据权利要求1所述的半导体存储装置，其中
所述第1芯片具备比所述多个第1导电层更远离所述半导体衬底的半导体层，且
所述多个第2接点及所述多个第3接点的所述第1方向的一端连接于所述半导体层。
7.根据权利要求1至6中任一项所述的半导体存储装置，其中
所述第1芯片具备：
第1区域，设置所述半导体柱；
第2区域，设置所述多个第1接点及所述多个第1贴合电极；及
第3区域，设置所述多个第2接点及所述多个第3接点；
所述第2芯片具备：
第4区域，与所述第1区域对向；及
第5区域，与所述第2区域对向，且包含所述多个第2贴合电极及连接于所述多个第1接点的多个所述晶体管；
所述第2区域的面积比所述第5区域的面积小，且
所述第3区域的一部分与所述第5区域的一部分对向。
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