TW201545297A - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TW201545297A
TW201545297A TW104126792A TW104126792A TW201545297A TW 201545297 A TW201545297 A TW 201545297A TW 104126792 A TW104126792 A TW 104126792A TW 104126792 A TW104126792 A TW 104126792A TW 201545297 A TW201545297 A TW 201545297A
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Taiwan
Prior art keywords
substrate
chip package
conductive
pad
semiconductor substrate
Prior art date
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TW104126792A
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English (en)
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TWI536525B (zh
Inventor
Chao-Yen Lin
Yi-Hang Lin
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Xintex Inc
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Publication of TW201545297A publication Critical patent/TW201545297A/zh
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Publication of TWI536525B publication Critical patent/TWI536525B/zh

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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Abstract

本發明揭露一種晶片封裝體，包括一下基底。一上基底具有一上表面及一下表面，且設置於下基底上方。一凹口鄰近於上基底的一側壁，其中凹口沿著自上基底的上表面朝下表面的一方向而形成。一元件區或感測區位於上基底的上表面。一導電墊位於上基底的上表面。一導電層電性連接導電墊，且沿著上基底的側壁延伸至凹口。

Description

晶片封裝體
本發明係有關於晶片封裝體，且特別是有關於感測晶片之晶片封裝體。
傳統晶片封裝體的製程涉及多道的圖案化製程與材料沉積製程，不僅耗費生產成本，亦需較長的製程時間。
因此，業界亟需更為簡化與快速的晶片封裝技術。
本發明實施例係提供一種晶片封裝體，包括一下基底。一上基底具有一上表面及一下表面，且設置於下基底上方。一凹口鄰近於上基底的一側壁，其中凹口沿著自上基底的上表面朝下表面的一方向而形成。一元件區或感測區位於上基底的上表面。一導電墊位於上基底的上表面。一導電層電性連接導電墊，且沿著上基底的側壁延伸至凹口。
本發明實施例係提供一種晶片封裝體，包括一承載基底。一半導體基底具有一上表面及一下表面，且設置於承載基底上方。一元件區或感測區位於半導體基底內。一導電墊位於半導體基底的上表面。一導電層電性連接導電墊，且自半導體基底的上表面延伸至半導體基底的一側壁上，其中半導體基底的側壁傾斜於半導體基底的上表面。
本發明實施例係提供一種晶片封裝體，包括一晶 片，其中晶片包括一承載基底以及位於承載基底上的一半導體基底。一指紋辨識區以及一導電墊位於晶片的一前表面。一凹口形成於晶片的前表面。一導電層電性連接導電墊，其中導電層更沿著凹口的一側壁而形成。一電路板具有一接墊，其中導電層透過一導電結構而與電路板上的接墊電性連接。
10‧‧‧封裝體
100‧‧‧基底
100a、100b‧‧‧表面
102‧‧‧元件區或感測區
104‧‧‧導電墊
106‧‧‧暫時性承載基板
108、112‧‧‧黏著層
110‧‧‧承載基底
114‧‧‧凹口
116‧‧‧絕緣層
118‧‧‧導電層
120‧‧‧電路板
122‧‧‧接墊
124‧‧‧焊球
126‧‧‧焊線
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的一系列製程剖面圖。
第2圖顯示本發明一實施例之晶片封裝體的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝感測晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)、噴墨頭(ink printer heads)、或功率模組(power IC modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1A-1D圖顯示根據本發明一實施例之晶片封裝體的一系列製程剖面圖。如第1A圖所示，提供半導體基底100，其具有上表面100a及下表面100b。半導體基底100例如為矽基底。在一實施例中，半導體基底100為一矽晶圓以利於進行晶圓級封裝。
如第1A圖所示，元件區或感測區102係形成於半導體基底100之中。在一實施例中，半導體基底100之中包括複數個元件區或感測區102。在一實施例中，元件區或感測區102例如為一感測區，如指紋辨識區等。元件區或感測區102係位於半導體基底100之上表面100a。在一實施例中，元件區或感測區102可能部分形成於半導體基底100之上表面100a之上。或者，在另一實施例中，元件區或感測區102完全形成於半導體基底100之中而於上表面100a露出。
如第1A圖所示，半導體基底100上還包括導電墊104。一般，導電墊104係透過內部線路(未顯示)而與元件區或感測區102電性連接。
接著，可選擇性將半導體基底100薄化以利後續製程之進行。例如，如第1B圖所示，在一實施例中，可將暫時性承載基板106設置於半導體基底100之上表面100a上。例如，可透過黏著層108而將暫時性承載基板106固定於半導體基底100之上表面100a上。接著，可以暫時性承載基板106為支撐，自半導體基底100之下表面100b進行薄化製程，如包括機械研磨或化學機械研磨等。在一實施例中，暫時性承載基板106可為玻璃基底或矽晶圓。
如第1B圖所示，在選擇性設置暫時性承載基板106與選擇性進行半導體基底100之薄化製程之後，於半導體基底100之下表面100b上設置承載基底110，半導體基底100可視為上基底且承載基底110可視為下基底。可於承載基底110與半導體基底100之間形成黏著層112以接合承載基底110與半導體基 底100。在一實施例中，承載基底110可為半導體基底或玻璃基底。
接著，如第1C圖所示，移除置暫時性承載基板106。在一實施例中，暫時性承載基板106下方之黏著層108完全自半導體基底100之上表面100a移除。在此情形下，元件區或感測區102大抵直接露出而不具有其他材料層於其上。
接著，自半導體基底100之上表面100a朝下表面100b之方向形成凹口(notch)114，鄰近於半導體基底100之側壁。在一實施例中，凹口114完全貫穿半導體基底100並延伸進入承載基底110之中。接著，於半導體基底100之上表面100a上及凹口114之側壁與底部上沉積絕緣材料，並將之圖案化以形成絕緣層116。接著，於絕緣層116之上形成圖案化的導電層118。
如第1C圖所示，導電層118係與導電墊104電性連接，並自半導體基底100之上表面100a延伸至凹口114之側壁與底部上。當凹口114貫穿半導體基底100而延伸進入承載基底110時，導電層118與絕緣層116還延伸進入承載基底110之中。此外，在一實施例中，在承載基底110之中，部分的導電層118與絕緣層116係大抵水平設置，即大抵平行於半導體基底100之上表面100a。這是因為在一實施例中，所形成之凹口114之底部係大抵平行於半導體基底100之上表面100a。
接著，如第1C圖所示，在一實施例中，自凹口114之底部切斷承載基底110以分離出複數個晶片封裝體10。由於電性連接導電墊104之導電層118延伸在晶片封裝體10之側壁 上(即自半導體基底100之上表面100a延伸至半導體基底100之側壁上)，可將導電通路自半導體基底100之上表面100a經由側壁而向下導引。在一實施例中，晶片封裝體10的封裝過程中僅需經歷兩道圖案化製程(即，絕緣層116之圖案化與導電層118之圖案化)，可使晶片之封裝製程大幅簡化，可節省製程時間與成本。此外，由於晶片之封裝製程大幅簡化，亦可使所形成之晶片封裝體的可靠度提升。
如第1D圖所示，在一實施例中，可進一步將所形成之晶片封裝體10設置於電路板120上。在一實施例中，電路板120上包括接墊122，其與電路板120中之線路相連，並作為與晶片封裝體中之元件區或感測區102電性連接之接觸點。如第1D圖之實施例所示，可於承載基底110與電路板120之間的轉角處形成焊球124。焊球124同時電性接觸導電層118與接墊122，形成導電層118與接墊122之間的導電通路。
應注意的是，本發明實施例不限於採用焊球124來形成元件區或感測區102與電路板120之間的導電通路。在其他實施例中，可採用導電層、導電塊、或焊線等其他的導電結構來取代焊球124。導電結構位於電路板的接墊與上基底的上表面之間。例如，在第2圖之實施例中，係改使用焊線126取代焊球124。導電結構的一部份位於上基底的上表面以及元件區或感測區的表面上方。因此，舉凡適於形成接墊122與導電層118之間的導電通路之導電結構，皆在本發明實施例所涵蓋之範圍之內。
本發明實施例透過於晶片(包括承載基底及半導體 基底)之正面/前表面(即與元件區或感測區同一側處)形成凹口及沿著凹口側壁形成與元件區或感測區電性連接之導電層，可順利形成所需之導電線路，並可大幅縮減晶片封裝製程所需之圖案化製程，可顯著地縮減製程時間與成本。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基底
102‧‧‧元件區或感測區
104‧‧‧導電墊
112‧‧‧黏著層
110‧‧‧承載基底
116‧‧‧絕緣層
118‧‧‧導電層
120‧‧‧電路板
122‧‧‧接墊
124‧‧‧焊球

Claims (21)

  1. 一種晶片封裝體，包括：一下基底；一上基底，具有一上表面及一下表面，且設置於該下基底上方；一凹口，鄰近於該上基底的一側壁，其中該凹口沿著自該上基底的該上表面朝該下表面的一方向而形成；一元件區或感測區，位於該上基底的該上表面；一導電墊，位於該上基底的該上表面；以及一導電層，電性連接該導電墊，且沿著該上基底的該側壁延伸至該凹口。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該上基底的該側壁傾斜於該上基底的該上表面。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該導電墊位於該凹口與該元件區或感測區之間。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該導電層更延伸至該凹口的一底部上。
  5. 如申請專利範圍第4項所述之晶片封裝體，其中該凹口的該底部位於該下基底的一表面上方且平行於該上基底的該上表面。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括一絕緣層，位於該導電層與該上基底之間及/或位於該導電層與該下基底之間。
  7. 如申請專利範圍第5項所述之晶片封裝體，更包括一電路 板，其中該導電層透過一導電結構而與該電路板上的一接墊電性連接。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該導電結構包括一焊球或一焊線。
  9. 如申請專利範圍第8項所述之晶片封裝體，其中該導電結構位於該電路板的該接墊與該上基底的該上表面之間。
  10. 如申請專利範圍第8項所述之晶片封裝體，其中該元件區或感測區的一表面位於該上基底的該上表面，且該導電結構的一部份位於該元件區或感測區的該表面上方。
  11. 一種晶片封裝體，包括：一承載基底；一半導體基底，具有一上表面及一下表面，且設置於該承載基底上方；一元件區或感測區，位於該半導體基底內；一導電墊，位於該半導體基底的該上表面；以及一導電層，電性連接該導電墊，且自該半導體基底的該上表面延伸至該半導體基底的一側壁上，其中該半導體基底的該側壁傾斜於該半導體基底的該上表面。
  12. 如申請專利範圍第11項所述之晶片封裝體，其中該元件區或感測區包括一指紋辨識區。
  13. 如申請專利範圍第11項所述之晶片封裝體，其中該導電層更延伸至該承載基底的一表面上，且該承載基底的該表面平行於該半導體基底的該上表面。
  14. 如申請專利範圍第13項所述之晶片封裝體，更包括一電路 板，其中該承載基底設置於該電路板上，且該導電層透過一導電結構而與該電路板上的一接墊電性連接。
  15. 如申請專利範圍第14項所述之晶片封裝體，其中該導電結構包括一焊球或一焊線。
  16. 如申請專利範圍第14項所述之晶片封裝體，其中該導電結構為一焊線，且該焊線的一部分位於該半導體基底的該上表面上方。
  17. 如申請專利範圍第14項所述之晶片封裝體，其中該導電結構位於該電路板的該接墊與該半導體基底的該上表面之間。
  18. 一種晶片封裝體，包括：一晶片，其中該晶片包括一承載基底以及位於該承載基底上的一半導體基底；一指紋辨識區以及一導電墊，位於該晶片的一前表面；一凹口，形成於該晶片的該前表面；一導電層，電性連接該導電墊，其中該導電層更沿著該凹口的一側壁而形成；以及一電路板，具有一接墊，其中該導電層透過一導電結構而與該電路板上的該接墊電性連接。
  19. 如申請專利範圍第18項所述之晶片封裝體，其中該導電結構位於該電路板的該接墊與該晶片的該前表面之間。
  20. 如申請專利範圍第19項所述之晶片封裝體，其中該導電結構包括一焊球或一焊線。
  21. 如申請專利範圍第20項所述之晶片封裝體，其中該導電墊 位於該指紋辨識區與該凹口之間。
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