CN106558525A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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CN106558525A
CN106558525A CN201610827085.XA CN201610827085A CN106558525A CN 106558525 A CN106558525 A CN 106558525A CN 201610827085 A CN201610827085 A CN 201610827085A CN 106558525 A CN106558525 A CN 106558525A
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substrate
thickness
wafer encapsulation
manufacture method
wafer
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关欣
刘沧宇
李柏汉
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其制造方法，该晶片封装体包括一第一基底及一第二基底。第一基底内包括一感测区或元件区。第一基底接合于一第二基底上，且电性连接至第二基底。第二基底的厚度与第一基底的厚度的比值为2至8。本发明能够进一步缩小晶片封装体的尺寸。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种薄化的晶片封装体及其制造方法。
背景技术
晶片封装制程是形成电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。
制作晶片封装体的过程包括将晶片接合于电路板上。然而，在接合的过程中晶片被取起及施压，因此晶片需要具有足够的厚度，以避免晶片遭受物理性破坏(例如，晶片出现破裂)，如此一来晶片封装体的尺寸难以进一步缩小。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明实施例提供一种晶片封装体，包括一第一基底及一第二基底。第一基底内包括一感测区或元件区。第一基底接合于一第二基底上，且电性连接至第二基底。第二基底的厚度与第一基底的厚度的比值为2至8。
本发明实施例提供一种晶片封装体的制造方法，包括：提供一第一基底，其中第一基底内包括一感测区或元件区；以及将第一基底接合于第二基底上，其中第一基底电性连接至第二基底，且第二基底的厚度与第一基底的厚度的比值为2至8。
本发明能够进一步缩小晶片封装体的尺寸。
附图说明
图1A至1F是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
其中，附图中符号的简单说明如下：
100：半导体基底；100a：第一表面；100b：第二表面；110：晶片区；120：感测区或元件区；130：绝缘层；140：导电垫；150：光学部件；160：第一基底；170：支撑基底；180：粘着层；185：子结构；190：第二基底；200：接触垫；210：导电结构；210a：末端；D1、D2、D3：距离；T1：初始厚度；T1’、T2、T3：厚度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然而其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System，MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package，WSP)制程对影像感测元件、发光二极管(light-emittingdiodes，LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识器(fingerprint recognition device)、微制动器(micro actuators)、表面声波元件(surface acoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)的晶片封装体或系统级封装(System in Package，SIP)的晶片封装体。
以下配合图1A至1F说明本发明一实施例的晶片封装体的制造方法，其中图1A至1F是绘示出根据本发明一实施例的晶片封装体的制造方法的剖面示意图。
请参照图1A，提供一半导体基底100，其具有一第一表面100a及与其相对的一第二表面100b，且包括多个晶片区110。为简化图式，此处仅绘示出一完整的晶片区及与其相邻的晶片区的一部分。在某些实施例中，半导体基底100可为一硅基底或其他半导体基底。在某些其他实施例中，半导体基底100为一硅晶圆，以利于进行晶圆级封装制程。
在某些实施例中，每一晶片区110的半导体基底100内具有一感测区或元件区120。感测区或元件区120可邻近于第一表面100a，且感测区或元件区120内包括一感测元件。在某些实施例中，感测区或元件区120内包括感光元件或其他适合的光电元件。在某些其他实施例中，感测区或元件区120内可包括感测生物特征的元件(例如，一指纹辨识元件)、感测环境特征的元件(例如，一温度感测元件、一湿度感测元件、一压力感测元件、一电容感测元件)或其他适合的感测元件。
半导体基底100的第一表面100a上具有一绝缘层130。一般而言，绝缘层130可由层间介电层、金属间介电层及覆盖的钝化层组成。为简化图式，此处仅绘示出单层绝缘层130。在某些实施例中，绝缘层130可包括无机材料，例如氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合或其他适合的绝缘材料。
在某些实施例中，每一晶片区110的绝缘层130内具有一个或一个以上的导电垫140。在某些实施例中，导电垫140可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明。在某些实施例中，每一晶片区110的绝缘层130内包括一个或一个以上的开口，露出对应的导电垫140。在某些实施例中，感测区或元件区120内的感测元件可通过半导体基底100内的内连线结构(未绘示)而与导电垫140电性连接。
在某些实施例中，可依序进行半导体装置的前段(front end)制程(例如，在半导体基底100内制作感测区或元件区120及后段(back end)制程(例如，在半导体基底100上制作绝缘层130、内连线结构及导电垫140)来制作前述结构。换句话说，以下晶片封装体的制造方法用于对完成后段制程的基底进行后续的封装制程。
在某些实施例中，每一晶片区110内还具有一光学部件150设置于半导体基底100的第一表面100a上，且对应于感测区或元件区120。在某些实施例中，光学部件150可为微透镜阵列、滤光层、其组合或其他适合的光学部件。
在某些实施例中，半导体基底100、绝缘层130及光学部件150共同构成一第一基底160，如图1A所示。在某些其他实施例中，第一基底160可仅由半导体基底100及绝缘层130所构成。在某些其他实施例中，除了半导体基底100及绝缘层130，第一基底160可能包括其他适合的部件。在某些实施例中，第一基底160的初始厚度T1为大约735μm或大约750μm。在某些其他实施例中，第一基底160可具有其他适合的厚度。
请参照图1B，将一支撑基底170贴附于第一基底160的前侧上。举例来说，导电垫140及光学部件150邻近于第一基底160的前侧，且导电垫140及光学部件150位于半导体基底100与支撑基底170之间。
在某些实施例中，支撑基底170的厚度T2为大约400μm或大于400μm。在某些实施例中，支撑基底170的平面尺寸大致上相同于半导体基底100的平面尺寸。在某些实施例中，支撑基底170由玻璃、半导体材料(例如，硅)或其他适合的支撑基底材料所构成。在某些实施例中，支撑基底170的材料相同于半导体基底100的材料。在某些其他实施例中，支撑基底170的材料不同于半导体基底100的材料。
在某些实施例中，支撑基底170通过一粘着层180贴附于第一基底160上。在某些实施例中，粘着层180为双面胶材或其他适合的粘着材料。再者，粘着层180包括可移除性材料，举例来说，粘着层180由可通过加热而消除粘性的材料所构成。
请参照图1C，以位于第一基底160前侧的支撑基底170作为承载基板，对第一基底160的背侧进行薄化制程，以减少第一基底160的初始厚度T1。
具体而言，对贴附有支撑基底170的半导体基底100的第二表面100b进行薄化制程，进而减少半导体基底100的厚度。在某些实施例中，支撑基底170为第一基底160提供支撑的功能，且支撑基底170具有足够的厚度T2，因此有利于尽可能减少第一基底160的厚度。在某些实施例中，薄化制程包括蚀刻制程、铣削(milling)制程、磨削(grinding)制程、研磨(polishing)制程或其他适合的制程。
在某些实施例中，第一基底160经薄化而减少了大约80％的初始厚度T1至大约95％的初始厚度T1。第一基底160的初始厚度T1经薄化后变成厚度T1’，且支撑基底170的厚度T2大于第一基底160的厚度T1’。
在某些实施例中，厚度T1’小于200μm。在某些实施例中，厚度T1’介于大约50μm至大约150μm之间。在某些实施例中，厚度T1’介于大约50μm至大约100μm之间。在某些其他实施例中，厚度T1’小于50μm。在某些实施例中，初始厚度T1与厚度T1’的比值介于大约5至大约15的范围内。在某些实施例中，厚度T2与厚度T1’的比值大于2。在某些实施例中，厚度T2与厚度T1’的比值介于大约2.6至大约8的范围内。
接着，沿着晶片区110之间的切割道SC切割第一基底160及支撑基底170，以形成多个独立的子结构(substructure)185，如图1D所示。子结构185为附有载板的晶片(chip)/晶粒(die)。子结构185亦可称为感测晶片/晶粒。
在某些实施例中，支撑基底170由易于切割的材料(例如，硅)所构成。在某些实施例中，支撑基底170的材料相同于半导体基底100的材料，以有助于切割制程的进行。
请参照图1D，每个子结构185包括薄化的第一基底160及贴附于前侧的支撑基底170。在某些实施例中，子结构185的厚度介于大约450μm至大约550μm的范围内。在某些实施例中，子结构185的厚度可能介于大约400μm至大约450μm的范围内。在某些其他实施例中，子结构185的厚度大于大约550μm。
请参照图1E，将子结构185接合(mount)于一第二基底190上，使得第二基底190位于第一基底160的背侧，且第一基底160位于支撑基底170与第二基底190之间。在某些实施例中，通过一粘着层(未绘示)将半导体基底100的第二表面100b贴附于第二基底190，使得半导体基底100位于支撑基底170与第二基底190之间。
在某些实施例中，第二基底190为电路板或其他适合的元件。第二基底190可能为印刷电路板(printed circuit board，PCB)。再者，第二基底190内具有接触垫(contactpad)200邻近于上表面。在某些实施例中，第二基底190的厚度T3介于大约300μm至大约400μm的范围内。在某些其他实施例中，第二基底190可具有其他适合的厚度。
在接合的过程中，通过点胶制程在子结构185上形成粘着层，并将子结构185取起及放置于第二基底190上，接着对子结构185施加向下的力量，以将子结构185与第二基底190之间的粘着层均匀地压散。由于子结构185内包括足够厚的支撑基底170，因此在上述接合的过程中可防止第一基底160遭受物理性破坏。特别是第一基底160的厚度极小的情况下，能够有效避免第一基底160出现破裂、弯曲或翘曲的问题。换句话说，由于子结构185内包括具有足够厚度的支撑基底170，因此可以尽可能降低第一基底160的厚度而不会对第一基底160造成损坏，如此一来能够进一步缩小晶片封装体的尺寸。
此外，支撑基底170亦可防止第一基底160被污染。举例来说，支撑基底170覆盖导电垫140及光学部件150，因此支撑基底170能够保护导电垫140及光学部件150在各个制程期间不被灰尘或颗粒污染，以显著提升晶片封装体的可靠度及品质。
在某些实施例中，支撑基底170的厚度T2与第一基底160的厚度T1’的比值应大致上相同或大于大约2。在某些情况下，如果厚度T2与厚度T1’的比值小于大约2，可能增加第一基底160出现破裂、弯曲或翘曲问题的机率。然而，本发明并不限定于此，在某些其他情况下，厚度T2与厚度T1’的比值有可能小于2。
在某些实施例中，支撑基底170的厚度T2与第一基底160的厚度T1’的比值应介于大约2.6至大约8的范围内。在某些情况下，如果厚度T2与厚度T1’的比值大于大约8，可能会增加沿着切割道SC切割第一基底160及支撑基底170的制程难度。然而，本发明并不限定于此，在某些其他情况下，厚度T2与厚度T1’的比值有可能大于8。
请参照图1F，将支撑基底170及粘着层180自第二基底190上的子结构185去除，进而露出光学部件150及导电垫140。在某些实施例中，经由加热来消除粘着层180的黏性，进而将支撑基底170分离(debond)及移除。例如，可利用紫外光(ultraviolet，UV)来进行加热。在去除支撑基底170及粘着层180之后，子结构185的厚度变成介于大约50μm至大约150μm之间或甚至小于50μm。
接着，在第二基底190上形成多个导电结构210。在某些实施例中，导电结构210为焊线或其他适合的导电结构。可通过打线接合(wire bonding)制程，将导电结构210自接触垫200延伸至导电垫140，以将半导体基底100与第二基底190电性连接。
在某些实施例中，晶片封装体具有极薄的厚度，特别是具有薄化的第一基底160，使得导电结构210的整体高度也随之降低。薄化的第一基底160的厚度T1’至少小于200μm，例如厚度T1’介于大约50μm至大约150μm之间，厚度T1’也可能小于50μm。因此，第二基底190的厚度T3与第一基底160的厚度T1’的比值介于大约2至大约8的范围内。
在某些实施例中，厚度T3与厚度T1’的比值应大致上相同或大于大约2。在某些情况下，如果厚度T3与厚度T1’的比值小于大约2，可能大幅增加第一基底160出现破裂、弯曲或翘曲问题的机率。
在某些实施例中，在接合过程中利用支撑基底170承载极薄的第一基底160，借此能够使得厚度T3与厚度T1’的比值大致上相同或小于大约8。在某些情况下，如果没有利用支撑基底170承载第一基底160，厚度T3与厚度T1’的比值将会大于8，因而难以降低晶片封装体的尺寸。然而，厚度T3与厚度T1’的比值并不限定于此。
在某些实施例中，第二基底190与导电垫140的距离D1大于第二基底190与感测区或元件区120的距离D2，且距离D1小于第二基底190与导电结构210位于导电垫140的末端210a之间的距离D3，如图1F所示。
在某些实施例中，距离D1小于200μm，例如距离D1介于大约50μm至大约150μm的范围内，距离D1也可能小于50μm。
在某些实施例中，距离D2远小于200μm，例如距离D2介于大约25μm至大约75μm的范围内，距离D2也可能小于25μm。
在某些实施例中，距离D3至少小于200μm，例如距离D3介于大约50μm至大约150μm的范围内，距离D3也可能小于50μm。
可以理解的是，虽然图1A至1F的实施例描述的是具有光学感测装置的晶片封装体的制造方法，然而本发明晶片封装体的制造方法亦可适用于其他类型的晶片封装体，而不限定于此。
一般而言，在薄化基底时，仅以厚度极小的胶带在薄化的过程中暂时性地保护基底，且为了避免后续在进行接合时基底出现破裂，基底的厚度不能变得太薄，因此导致晶片封装体的尺寸受到限制。
根据本发明的上述实施例，利用暂时性支撑基底提供结构强度，有利于协助晶圆基底的薄化及切割，也进一步协助晶片基底与电路板的接合，因此可在不破坏晶片基底的情况下大幅减少晶片基底的厚度，如此一来能够更进一步地降低晶片封装体的尺寸。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
第一基底，其中该第一基底内包括感测区或元件区；以及
第二基底，其中该第一基底接合于该第二基底上且电性连接至该第二基底，且该第二基底的厚度与该第一基底的厚度的比值为2至8。
2.根据权利要求1所述的晶片封装体，其特征在于，该第一基底的该厚度为50μm至150μm。
3.根据权利要求1所述的晶片封装体，其特征在于，该第二基底的该厚度为300μm至400μm。
4.根据权利要求1所述的晶片封装体，其特征在于，该第二基底为电路板。
5.根据权利要求1所述的晶片封装体，其特征在于，还包括导电结构，其中该导电结构位于该第一基底上，且将该第一基底电性连接至该第二基底。
6.根据权利要求5所述的晶片封装体，其特征在于，该第二基底与位于该第一基底上的该导电结构之间的距离为50μm至150μm。
7.根据权利要求1所述的晶片封装体，其特征在于，该第一基底具有前侧及背侧，该第二基底位于该第一基底的该背侧，且该第一基底内还包括导电垫，该导电垫邻近于该前侧。
8.根据权利要求7所述的晶片封装体，其特征在于，该第二基底与该导电垫之间的距离为50μm至150μm。
9.一种晶片封装体的制造方法，其特征在于，包括：
提供第一基底，其中该第一基底内包括感测区或元件区；以及
将该第一基底接合于第二基底上，其中该第一基底电性连接至该第二基底，且该第二基底的厚度与该第一基底的厚度的比值为2至8。
10.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该第一基底的该厚度为50μm至150μm。
11.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该第二基底的该厚度为300μm至400μm。
12.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该第一基底具有前侧及背侧，该第二基底位于该第一基底的该背侧，且该第一基底内还包括导电垫，该导电垫邻近于该前侧。
13.根据权利要求9所述的晶片封装体的制造方法，其特征在于，提供该第一基底的步骤包括将支撑基底贴附于该第一基底上，且该支撑基底的厚度大于该第一基底的该厚度。
14.根据权利要求13所述的晶片封装体的制造方法，其特征在于，该支撑基底的该厚度与该第一基底的该厚度的比值大于2。
15.根据权利要求13所述的晶片封装体的制造方法，其特征在于，该支撑基底由玻璃或半导体材料所构成。
16.根据权利要求13所述的晶片封装体的制造方法，其特征在于，提供该第一基底的步骤还包括对贴附有该支撑基底的该第一基底进行薄化制程，以得到该第一基底的该厚度。
17.根据权利要求16所述的晶片封装体的制造方法，其特征在于，在进行薄化制程之前该第一基底具有初始厚度，该初始厚度与该第一基底的该厚度的比值为5至15。
18.根据权利要求13所述的晶片封装体的制造方法，其特征在于，提供该第一基底的步骤还包括对该第一基底及该支撑基底进行切割制程。
19.根据权利要求13所述的晶片封装体的制造方法，其特征在于，将该第一基底接合于该第二基底上的步骤包括将贴附有该支撑基底的该第一基底接合于该第二基底上，且该第一基底位于该支撑基底与该第二基底之间。
20.根据权利要求19所述的晶片封装体的制造方法，其特征在于，还包括在将贴附有该支撑基底的该第一基底接合于该第二基底上之后去除该支撑基底。
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