TWI701774B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI701774B
TWI701774B TW107124478A TW107124478A TWI701774B TW I701774 B TWI701774 B TW I701774B TW 107124478 A TW107124478 A TW 107124478A TW 107124478 A TW107124478 A TW 107124478A TW I701774 B TWI701774 B TW I701774B
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Taiwan
Prior art keywords
semiconductor device
layer
electronic component
flash memory
adhesive layer
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TW107124478A
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English (en)
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TW201939684A (zh
Inventor
大石麻莉子
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日商東芝記憶體股份有限公司
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Publication of TW201939684A publication Critical patent/TW201939684A/zh
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Publication of TWI701774B publication Critical patent/TWI701774B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

實施形態提供一種能夠設置用以將電子零件掩埋之足夠量之接著層的半導體裝置。 一實施形態之半導體裝置具備基板、第1構件、第1接著層、第1電子零件、第2電子零件、及樹脂。上述基板具有第1面。上述第1構件具有朝向上述第1面之第2面、以及位於上述第2面之相反側並且由包含第1有機材料之材料形成之第3面。上述第1接著層處於上述第1面與上述第2面之間，且附著於上述第1面與上述第2面。上述第1電子零件處於上述第1面與上述第2面之間，安裝於上述第1面，且埋設於上述第1接著層。上述第2電子零件安裝於上述第3面。上述樹脂將上述第1構件、上述第1接著層、及上述第2電子零件掩埋，且附著於上述第1面及上述第3面。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
作為半導體裝置，已知有具備所積層之電子零件之裝置。例如，被稱為晶粒上薄膜(Film On Die：FOD)之構造具備所積層之記憶體、以及被如晶粒貼裝膜(Die Attach Film：DAF)之接著層掩埋之控制器。
上述FOD中，控制器埋設於用以將記憶體安裝於配線基板之DAF中。然而，於記憶體相對於控制器而言相對較小之情形時，DAF亦變小，故而有可能控制器不會充分地埋設至DAF中。
實施形態提供一種能夠設置用以將電子零件掩埋之足夠量之接著層的半導體裝置。
一實施形態之半導體裝置具備基板、第1構件、第1接著層、第1電子零件、第2電子零件、及樹脂。上述基板具有第1面。上述第1構件具有朝向上述第1面之第2面、以及位於上述第2面之相反側並且由包含第1有機材料之材料形成之第3面。上述第1接著層處於上述第1面與上述第2面之間，且附著於上述第1面與上述第2面。上述第1電子零件處於上述第1面與上述第2面之間，安裝於上述第1面，且埋設於上述第1接著層。上述第2電子零件安裝於上述第3面。上述樹脂將上述第1構件、上述第1接著層、及上述第2電子零件掩埋，且附著於上述第1面及上述第3面。
(第1實施形態) 以下，參照圖1至圖3對第1實施形態進行說明。再者，本說明書中，關於實施形態之構成要素及該要素之說明，有時記載複數種表達。被記載有複數種表達之構成要素及說明亦可進行未記載之其他表達。進而，未被記載複數種表達之構成要素及說明亦可進行未記載之其他表達。
圖1係概略性地表示第1實施形態之電子設備1之一部分之剖視圖。本實施形態中之作為一例之電子設備1係智慧型手機。電子設備1亦可為例如個人電腦、可攜式電腦、平板、行動電話、電視接收機、硬碟驅動器(Hard Disk Drive：HDD)、固態驅動器(Solid State Drive：SSD)、USB(Universal Serial Bus，通用串列匯流排)快閃驅動器、SD(Secure Digital，安全數位)卡、eMMC(註冊商標)、通用快閃儲存器(Universal Flash Storage：UFS)、記憶卡、其他記憶裝置、可佩戴裝置、智慧型揚聲器、家庭用電氣設備、及其他裝置。
如圖1所示，電子設備1具有電路基板5、及半導體裝置10。電路基板5例如為印刷電路板(PCB)。於電路基板5搭載有半導體裝置10。亦可進而於電路基板5搭載如控制電子設備1之中央處理裝置(CPU(Central Processing Unit，中央處理單元))之其他裝置。
本實施形態中之作為一例之半導體裝置10係具有晶粒上薄膜(FOD)構造之焊盤網格陣列(Land Grid Array：LGA)之半導體封裝。再者，半導體裝置10亦可具有其他構造，亦可為如球狀網格陣列(Ball Grid Array：BGA)之其他規格之半導體封裝。
如圖式所示，於本說明書中，定義X軸、Y軸及Z軸。X軸、Y軸及Z軸相互正交。X軸沿著半導體裝置10之寬度。Y軸沿著半導體裝置10之長度(深度)。Z軸沿著半導體裝置10之高度(厚度)。
半導體裝置10具有基板11、板材12、第1接著層13、控制器14、複數個快閃記憶體15、複數個第2接著層17、間隔片16、及密封樹脂18。半導體裝置10亦可進而具有如溫度感測器之其他零件。
板材12係第1構件之一例。控制器14係第1電子零件之一例。快閃記憶體15係第2電子零件之一例。控制器14及快閃記憶體15分別亦可被稱為例如半導體晶片。間隔片16係第2構件之一例。密封樹脂18係樹脂之一例。
基板11例如為印刷配線板(PWB)。基板11具有上表面11a及下表面11b。上表面11a係第1面之一例。上表面11a係朝向Z軸正方向(Z軸之箭頭所示之方向)之大致平坦之面。下表面11b係位於上表面11a之相反側、朝向Z軸負方向(Z軸之箭頭之相反方向)之大致平坦之面。
於基板11之上表面11a，設置有複數個焊墊21。焊墊21亦可被稱為例如焊盤。上表面11a之除焊墊21以外之部分例如由阻焊劑形成。另一方面，於基板11之下表面11b，設置有複數個焊盤22。下表面11b之除焊盤22以外之部分例如由阻焊劑形成。
複數個焊墊21與複數個焊盤22例如經由設置於基板11之通孔或配線而相互電性連接。再者，亦可至少一個焊墊21與其他焊墊21電性連接，且與焊盤22電性隔離。焊盤22例如經由焊料而電性連接於設置在電路基板5之焊盤。藉此，將半導體裝置10搭載於電路基板5。
板材12具有下表面12a、上表面12b及側面12c。下表面12a係第2面之一例。上表面12b係第3面之一例。側面12c係第4面之一例。再者，本說明書中之上方、下方、及側方之稱呼係為了基於圖1進行說明而附加，並非限定半導體裝置10或板材12之朝向及形狀。
下表面12a係朝向Z軸負方向之大致平坦之面。下表面12a於自基板11向Z軸之正方向隔開之位置，朝向基板11之上表面11a。上表面12b係位於下表面12a之相反側、朝向Z軸正方向之大致平坦之面。側面12c位於下表面12a與上表面12b之間，朝向與Z軸交叉之方向。
圖2係表示第1實施形態之半導體裝置10之一部分之剖視圖。再者，於圖2中，省略了密封樹脂18。如圖2所示，板材12具有基材31及有機層32。
基材31形成為板狀。再者，基材31並不限於該例。基材31具有板材12之下表面12a、及側面12c之一部分。進而，基材31具有塗佈面31a。塗佈面31a係位於下表面12a之相反側、朝向Z軸正方向之大致平坦之面。
基材31具有無機層35與中間層36。無機層35係無機構件之一例。無機層35與中間層36係一體地形成。再者，無機層35與中間層36亦可分別形成。
無機層35例如由包含用以製造半導體之矽(Si)之材料形成。矽係無機材料之一例。再者，無機層35亦可由其他材料形成。又，亦可於無機層35中混入有機物。無機層35具有板材12之下表面12a、及側面12c之一部分。
中間層36例如由包含氮化矽(矽氮化物，Si3 N4 )之材料形成。中間層36例如藉由使無機層35之一部分氮化而生成。即，中間層36由無機層35之材料即包含矽之氮化物之材料形成。再者，中間層36並不限於該例，亦可由矽之氧化物即二氧化矽(氧化矽，SiO2 )、或其他材料形成。中間層36具有基材31之塗佈面31a、及板材12之側面12c之一部分。
有機層32例如由包含聚醯亞胺(PI)樹脂之材料形成。聚醯亞胺樹脂係第1有機材料之一例。再者，有機層32亦可由例如包含酚系樹脂、環氧樹脂、或其他有機材料之材料形成。又，亦可於有機層32中混入無機物。
有機層32被塗佈於基材31之塗佈面31a。換言之，有機層32附著於具有塗佈面31a之中間層36。因此，中間層36位於無機層35與有機層32之間。有機層32具有板材12之上表面12b、及側面12c之一部分。即，板材12之上表面12b由包含聚醯亞胺樹脂之材料形成。
與直接附著於無機層35之情行相比，有機層32牢固地附著於中間層36。例如，有機層32與中間層36連接(附著)之部分之拉伸強度較有機層32附著於無機層35之情形時之有機層32與無機層35連接(附著)之部分之拉伸強度大。如此，附著於中間層36之有機層32相較於附著在無機層35之情形而言不易產生剝離。
第1接著層13為晶粒貼裝膜(DAF)，例如，由包含丙烯酸系聚合物及環氧樹脂之材料形成。晶粒貼裝膜亦可被稱為晶粒接合膜(Die Bonding Film)。
如圖1所示，第1接著層13配置於基板11之上表面11a與板材12之下表面12a之間。第1接著層13附著於上表面11a與下表面12a，將基板11與板材12相互固定。
控制器14例如控制複數個快閃記憶體15之記憶及讀出。再者，並不限於快閃記憶體15，控制器14亦可控制半導體裝置10所包含之其他電子零件。
控制器14位於基板11之上表面11a與板材12之下表面12a之間。如此，板材12隔著第1接著層13於Z軸方向上與控制器14重疊。
控制器14安裝於上表面11a，藉由複數條第1接合線41而電性連接於上表面11a之複數個焊墊21。如此，控制器14藉由線接合而與設置在基板11之配線電性連接。再者，控制器14並不限於該例，例如，亦可利用如覆晶安裝般之其他方法搭載於上表面11a。
包含第1接合線41之控制器14埋設於第1接著層13。即，控制器14在搭載於上表面11a之狀態下，被第1接著層13包圍，且被第1接著層13覆蓋。根據另一種表達，控制器14係被收容於第1接著層13，而處於第1接著層13之中。
於Z軸方向上，第1接著層13之長度(厚度)超過控制器14之長度(厚度)。進而，於與Z軸交叉之方向(例如，X軸方向)上，第1接著層13之長度(寬度)超過控制器14之長度(寬度)。
快閃記憶體15係NAND(Not-AND，反及)型快閃記憶體。再者，快閃記憶體15並不限於該例。快閃記憶體15包含矽基板(矽晶圓)43，該矽基板(矽晶圓)43作為由包含矽之材料形成之層。即，快閃記憶體15之材料與無機層35之材料均包含矽。
如圖2所示，複數個快閃記憶體15分別具有下表面15a、上表面15b、及側面15c。上表面15b係表面之一例。下表面15a係朝向Z軸負方向之大致平坦之面。上表面15b係位於下表面15a之相反側、朝向Z軸正方向之大致平坦之面。側面15c位於下表面15a與上表面15b之間，朝向與Z軸交叉之方向。
快閃記憶體15之上表面15b例如由包含聚醯亞胺樹脂之材料形成。即，快閃記憶體15之上表面15b之材料與板材12之有機層32之材料均包含聚醯亞胺樹脂。
如圖1所示，設置於快閃記憶體15之上表面15b之端子與設置於其他快閃記憶體15之上表面15b之端子、或上表面11a之焊墊21藉由第2接合線45而電性連接。即，複數個快閃記憶體15分別藉由複數條第2接合線45而電性連接於其他快閃記憶體15、或上表面11a之複數個焊墊21。
複數個快閃記憶體15經由第2接合線45、基板11之配線、及第1接合線41而電性連接於控制器14。因此，控制器14可控制快閃記憶體15。
複數個快閃記憶體15係於Z軸方向上積層，且被安裝於板材12之上表面12b。藉由被安裝於上表面12b，複數個快閃記憶體15隔著板材12及第1接著層13而於Z軸方向上與控制器14重疊。
複數個快閃記憶體15包含第1快閃記憶體51、第2快閃記憶體52、第3快閃記憶體53、及第4快閃記憶體54。第1至第4快閃記憶體51〜54分別具有下表面15a及上表面15b。第1至第4快閃記憶體51〜54於本實施形態中為相同之電子零件，但亦可例如形狀或容量互不相同。
第1快閃記憶體51安裝於板材12之上表面12b。第2快閃記憶體52安裝於第1快閃記憶體51之上表面15b。第3快閃記憶體53隔著間隔片16安裝於第2快閃記憶體52之上表面15b。第4快閃記憶體54安裝於第3快閃記憶體53之上表面15b。如此，第2至第4快閃記憶體52〜54隔著第1快閃記憶體51而安裝於板材12之上表面12b。
間隔片16例如由包含聚醯亞胺樹脂之材料形成。聚醯亞胺樹脂係第2有機材料之一例。再者，間隔片16亦可由例如酚系樹脂、環氧樹脂、或其他材料形成。
間隔片16形成為板狀。再者，間隔片16並不限於該例。間隔片16具有下表面16a、上表面16b、及側面16c。下表面16a係第5面之一例。上表面16b係第6面之一例。側面16c係第7面之一例。
下表面16a係朝向Z軸負方向之大致平坦之面。上表面16b係位於下表面16a之相反側且朝向Z軸正方向之大致平坦之面。側面16c位於下表面16a與上表面16b之間，朝向與Z軸交叉之方向。由於間隔片16由包含聚醯亞胺樹脂之材料形成，故而下表面16a、上表面16b、及側面16c由包含聚醯亞胺樹脂之材料形成。
間隔片16位於第2快閃記憶體52與第3快閃記憶體53之間。下表面16a朝向第2快閃記憶體52之上表面15b。上表面16b朝向第3快閃記憶體53之下表面15a。
第2接著層17為DAF。再者，第2接著層17並不限於該例。複數個第2接著層17附著於快閃記憶體15之下表面15a、及間隔片16之下表面16a。
第1快閃記憶體51上所附著之第2接著層17附著於板材12之上表面12b。藉此，第2接著層17將第1快閃記憶體51安裝於上表面12b。
第2快閃記憶體52上所附著之第2接著層17附著於第1快閃記憶體51之上表面15b。藉此，第2接著層17將第2快閃記憶體52安裝於第1快閃記憶體51。
間隔片16上所附著之第2接著層17附著於第2快閃記憶體52之上表面15b。藉此，第2接著層17將間隔片16之下表面16a安裝於第2快閃記憶體52。
第3快閃記憶體53上所附著之第2接著層17附著於間隔片16之上表面16b。藉此，第2接著層17將第3快閃記憶體53安裝於間隔片16之上表面16b。
第4快閃記憶體54上所附著之第2接著層17附著於第3快閃記憶體53之上表面15b。藉此，第2接著層17將第4快閃記憶體54安裝於第3快閃記憶體53。
間隔片16並不限於處在第2快閃記憶體52與第3快閃記憶體53之間，亦可處在第1快閃記憶體51與第2快閃記憶體52之間、或第3快閃記憶體53與第4快閃記憶體54之間。藉由間隔片16，例如，能夠抑制快閃記憶體15與其他零件之干涉，或者形成能夠配置第2接合線45之空間。
圖1中之第2接著層17較第1接著層13薄。然而，第2接著層17之厚度亦可與第1接著層13之厚度相同，還可較第1接著層13厚。
圖3係概略性地表示第1實施形態之半導體裝置10之俯視圖。於圖3中，密封樹脂18、第1接合線41、及第2接合線45被省略。
如圖3所示，於朝向Z軸負方向觀察之俯視下，控制器14較板材12小，且處於板材12之側面12c之內側。側面12c係第1構件之邊緣之一例。根據另一種表達，於朝向Z軸負方向觀察之俯視下，控制器14處於板材12之側面12c之內側，且與側面12c隔開。根據又一種表達，控制器14之X-Y平面內之區域落入板材12之X-Y平面中之區域內。
進而，於朝向Z軸負方向觀察之俯視下，複數個快閃記憶體15較板材12小，且處於板材12之側面12c之內側。再者，於朝向Z軸負方向觀察之俯視下，快閃記憶體15亦可較板材12大，還可處於側面12c之外側。
如上所述，於板材12之上表面12b，安裝有第1快閃記憶體51。上表面12b具有第1部分12ba、及第2部分12bb。第1部分12ba係上表面12b中供安裝第1快閃記憶體51且被第1快閃記憶體51覆蓋之部分。第2部分12bb係上表面12b中除第1部分12ba以外之部分。第2部分12bb之面積較板材12之側面12c之面積大。
圖1之密封樹脂18例如由包含混合有如二氧化矽之無機物之環氧樹脂的材料形成。再者，密封樹脂18亦可由包含其他合成樹脂之材料形成。密封樹脂18將搭載於基板11之板材12、第1接著層13、控制器14、複數個快閃記憶體15、間隔片16、及複數個第2接著層17密封。
板材12、埋設有控制器14之第1接著層13、複數個快閃記憶體15、間隔片16、及複數個第2接著層17埋設於密封樹脂18。即，板材12、第1接著層13、複數個快閃記憶體15、間隔片16、及複數個第2接著層17被密封樹脂18包圍，且被密封樹脂18覆蓋。根據另一種表達，板材12、第1接著層13、複數個快閃記憶體15、間隔片16、及複數個第2接著層17被收容於密封樹脂18，處於密封樹脂18之中。
密封樹脂18附著於基板11之上表面11a、板材12之上表面12b及側面12c、第1接著層13、快閃記憶體15之上表面15b及側面15c、間隔片16之側面16c、以及第2接著層17。密封樹脂18附著於板材12之上表面12b中之第2部分12bb。因此，上表面12b之附著有密封樹脂18之部分(第2部分12bb)之面積較側面12c之附著有密封樹脂18之部分之面積大。
基板11之上表面11a、板材12之上表面12b、第1接著層13、快閃記憶體15之上表面15b、間隔片16之側面16c、第2接著層17、及密封樹脂18由包含有機材料之材料形成。藉由有機樹脂彼此之附著，而與附著於無機材料之情形相比，密封樹脂18牢固地附著於基板11之上表面11a、板材12之上表面12b、第1接著層13、快閃記憶體15之上表面15b、間隔片16之側面16c、及第2接著層17。
例如，密封樹脂18與板材12之上表面12b之密接性變高。因此，密封樹脂18與板材12之上表面12b連接(附著)之部分之拉伸強度較密封樹脂18與無機層35之側面12c連接(附著)之部分之拉伸強度大。如此，密封樹脂18之附著於上表面12b之部分與附著於由無機材料形成之部分之情形相比，不易產生剝離。
以下，對板材12及第1接著層13之製造方法之一部分進行例示。再者，板材12及第1接著層13之製造方法並不限於以下之方法，亦可使用其他方法。
首先，利用製造快閃記憶體15之矽基板43之基板製造裝置製造矽晶圓。矽晶圓係切開分離(切割)前之包含複數個基材31之矽板。以下，為了說明，將切割前之矽晶圓亦作為基材31進行說明。
基板製造裝置既可利用與快閃記憶體15之矽基板43相同之材料形成基材31，亦可利用與快閃記憶體15之矽基板43略有不同之材料形成基材31。然而，快閃記憶體15之矽基板43之材料與基材31之材料均包含矽。
其次，利用氮化裝置，將基材31之一部分氮化。藉此，於基材31設置氮化矽層即中間層36。再者，亦可藉由氧化裝置將基材31之一部分氧化，而於基材31設置二氧化矽之層即中間層36。然後，於中間層36之塗佈面31a塗佈有機層32。再者，亦可省略中間層36之生成，而將有機層32塗佈於無機層35。
其次，利用研磨機，對基材31之無機層35進行研削(研磨)。藉此，調整基材31之厚度。然後，於無機層35之下表面12a附著作為DAF之第1接著層13。
其次，將附著了有機層32及第1接著層13之矽晶圓切開分離(切割)。藉此，圖1所示之板材12及第1接著層13作為一體之零件而獲得。
以上所說明之第1實施形態之半導體裝置10中，控制器14埋設於第1接著層13，該第1接著層13處於基板11之上表面11a與板材12之下表面12a之間，且附著於上表面11a與下表面12a。快閃記憶體15安裝於板材12之上表面12b。藉此，於FOD構造中，無論快閃記憶體15之大小或形狀如何，均能在基板11與板材12之間設置用以將控制器14掩埋之足夠量之第1接著層13，且能使快閃記憶體15穩定。
將板材12、第1接著層13、及快閃記憶體15掩埋之密封樹脂18附著於基板11之上表面11a及板材12之上表面12b。上表面12b由包含作為有機材料之聚醯亞胺樹脂之材料形成。因此，與上表面12b由無機材料形成之情形相比，密封樹脂18可更確實地附著於板材12之上表面12b。因此，例如，密封樹脂18自板材12剝離之情況得到抑制，從而抑制半導體裝置10之良率下降。
於朝下表面12a所朝向之方向觀察之俯視下，控制器14較板材12小，且處於板材12之側面12c之內側。藉此，控制器14更確實地埋設於第1接著層13，板材12與安裝於該板材12之快閃記憶體15穩定。
於朝下表面12a所朝向之方向觀察之俯視下，快閃記憶體15較板材12小，且處於板材12之側面12c之內側。即，藉由在較快閃記憶體15更大之板材12設置第1接著層13，即便快閃記憶體15較小，亦能將控制器14更確實地埋設於第1接著層13。因此，板材12與安裝於該板材12之快閃記憶體15穩定。
上表面12b之附著有密封樹脂18之部分(第2部分12bb)之面積大於側面12c之附著有密封樹脂18之部分之面積。即，附著有密封樹脂18之部分之面積較大之上表面12b由包含有機材料之材料形成。藉此，密封樹脂18能夠更確實地附著於板材12。
板材12具有：無機層35，其具有下表面12a，並且由矽般之無機材料形成；以及有機層32，其具有上表面12b並且由包含有機材料之材料形成。由於板材12之一部分由無機材料形成，故而容易將板材12之剛性設定得較高。
板材12具有位於無機層35與有機層32之間之中間層36。有機層32與中間層36連接之部分之拉伸強度，大於有機層32附著於無機層35之情形之有機層32與無機層35連接之部分之拉伸強度。藉此，抑制有機層32之剝離。
板材12具有中間層36，該中間層36位於無機層35與有機層32之間並且由包含氮化矽之材料形成。藉此，藉由氮化，可容易地於基材31設置中間層36，從而能夠抑制有機層32之剝離。
快閃記憶體15包含矽基板43，該矽基板43由包含作為無機材料之矽之材料形成。藉此，可使快閃記憶體15之矽基板43之製造與包含無機層35之基材31之製造局部共通化，從而抑制半導體裝置10之成本增大。
間隔片16設置於相鄰之兩個快閃記憶體15之間。密封樹脂18附著於間隔片16之側面16c。側面16c由包含作為有機材料之聚醯亞胺樹脂之材料形成。因此，與側面16c由無機材料形成之情形相比，密封樹脂18能夠更確實地附著於間隔片16之側面16c。
快閃記憶體15之上表面15b由包含聚醯亞胺樹脂之材料形成。藉此，可使快閃記憶體15之上表面15b之材料與板材12之上表面12b之材料共通化，從而抑制半導體裝置10之成本增大。
(第2實施形態) 以下，參照圖4對第2實施形態進行說明。再者，於以下實施形態之說明中，關於具有與已經說明之構成要素相同之功能之構成要素，有時標註與該已經敍述之構成要素相同之符號，進而省略說明。又，標註有相同符號之複數個構成要素全部之功能及性質未必均共通，亦可具有與各實施形態相應之不同之功能及性質。
圖4係概略性地表示第2實施形態之電子設備1之一部分之剖視圖。如圖4所示，第2實施形態之板材12由包含聚醯亞胺樹脂之材料形成。因此，下表面12a、上表面12b、及側面12c亦由包含聚醯亞胺樹脂之材料形成。
以上所說明之第2實施形態之半導體裝置10中，板材12由包含聚醯亞胺樹脂之材料形成。藉此，能夠藉由包含聚醯亞胺樹脂之材料容易地形成上表面12b。進而，由於側面12c亦由包含聚醯亞胺樹脂之材料形成，故而密封樹脂18能夠更確實地附著於板材12，而抑制例如密封樹脂18自板材12剝離。
以下，對第1及第2實施形態之變化例進行說明。該變化例中，板材12之有機層32或板材12由包含環氧樹脂之材料形成。環氧樹脂係第1有機材料之一例。因此，密封樹脂18由包含有機層32之材料即環氧樹脂之材料形成。
本變化例中，亦可為板材12之有機層32或板材12由包含聚醯亞胺樹脂之材料形成，且密封樹脂18亦由包含聚醯亞胺樹脂之材料形成。如此，於本變化例中，板材12之上表面12b或板材12之材料與密封樹脂18之材料包含共通之有機材料。
本變化例中，密封樹脂18由與板材12之上表面12b或板材12之材料相同之包含環氧樹脂或聚醯亞胺樹脂之材料形成。藉此，密封樹脂18能夠更確實地附著於板材12之上表面12b。進而，密封樹脂18之熱膨脹率與上表面12b之熱膨脹率接近，而抑制因熱膨脹及收縮引起之剝離。
以上所說明之複數個實施形態中，控制器14係第1電子零件之一例，快閃記憶體15係第2電子零件之一例。然而，第1電子零件及第2電子零件並不限於該例。例如，亦可如介面晶片般之其他電子零件為第1電子零件之一例。又，所積層之複數個第2電子零件並不限於例如快閃記憶體15，亦可包含複數種電子零件。
根據以上所說明之至少一個實施形態，第1電子零件埋設於接著層，該接著層處於基板之第1面與第1構件之第2面之間，且附著於第1面與第2面。第2電子零件安裝於第1構件之第3面。藉此，無論第2電子零件之大小如何，均能在基板與第1構件之間設置用以將第1電子零件掩埋之足夠量之接著層。
已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且能夠在不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請案] 本申請案享有以日本專利申請案2018-35714號(申請日：2018年2月28日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1‧‧‧電子設備5‧‧‧電路基板10‧‧‧半導體裝置11‧‧‧基板11a‧‧‧上表面11b‧‧‧下表面12‧‧‧板材12a‧‧‧下表面12b‧‧‧上表面12ba‧‧‧第1部分12bb‧‧‧第2部分12c‧‧‧側面13‧‧‧第1接著層14‧‧‧控制器15‧‧‧快閃記憶體15a‧‧‧下表面15b‧‧‧上表面15c‧‧‧側面16‧‧‧間隔片16a‧‧‧下表面16b‧‧‧上表面16c‧‧‧側面17‧‧‧第2接著層18‧‧‧密封樹脂21‧‧‧焊墊22‧‧‧焊盤31‧‧‧基材31a‧‧‧塗佈面32‧‧‧有機層35‧‧‧無機層36‧‧‧中間層41‧‧‧第1接合線43‧‧‧矽基板45‧‧‧第2接合線51‧‧‧第1快閃記憶體52‧‧‧第2快閃記憶體53‧‧‧第3快閃記憶體54‧‧‧第4快閃記憶體X‧‧‧軸Y‧‧‧軸Z‧‧‧軸
圖1係概略性地表示第1實施形態之電子設備之一部分之剖視圖。 圖2係表示第1實施形態之半導體裝置之一部分之剖視圖。 圖3係概略性地表示第1實施形態之半導體裝置之俯視圖。 圖4係概略性地表示第2實施形態之電子設備之一部分之剖視圖。
1‧‧‧電子設備
5‧‧‧電路基板
10‧‧‧半導體裝置
11‧‧‧基板
11a‧‧‧上表面
11b‧‧‧下表面
12‧‧‧板材
12a‧‧‧下表面
12b‧‧‧上表面
12c‧‧‧側面
13‧‧‧第1接著層
14‧‧‧控制器
15‧‧‧快閃記憶體
15a‧‧‧下表面
15b‧‧‧上表面
15c‧‧‧側面
16‧‧‧間隔片
16a‧‧‧下表面
16b‧‧‧上表面
16c‧‧‧側面
17‧‧‧第2接著層
18‧‧‧密封樹脂
21‧‧‧焊墊
22‧‧‧焊盤
41‧‧‧第1接合線
45‧‧‧第2接合線
51‧‧‧第1快閃記憶體
52‧‧‧第2快閃記憶體
53‧‧‧第3快閃記憶體
54‧‧‧第4快閃記憶體
X‧‧‧軸
Z‧‧‧軸

Claims (20)

  1. 一種半導體裝置，其具備：基板，其具有第1面；第1構件，其具有朝向上述第1面之第2面、及位於上述第2面之相反側並且由包含第1有機材料之材料形成之第3面；第1接著層，其處於上述第1面與上述第2面之間，附著於上述第1面與上述第2面，且未較上述第3面位於更上方；第1電子零件，其處於上述第1面與上述第2面之間，安裝於上述第1面，且埋設於上述第1接著層；第2電子零件，其安裝於上述第3面；以及樹脂，其將上述第1構件、上述第1接著層、及上述第2電子零件掩埋，且附著於上述第1面及上述第3面。
  2. 如請求項1之半導體裝置，其中於朝上述第2面所朝向之方向觀察之俯視下，上述第1電子零件小於上述第1構件，且處於上述第1構件之邊緣之內側。
  3. 如請求項1之半導體裝置，其中於朝上述第2面所朝向之方向觀察之俯視下，上述第2電子零件小於上述第1構件，且處於上述第1構件之邊緣之內側。
  4. 如請求項1之半導體裝置，其中 上述第1構件具有位於上述第2面與上述第3面之間之第4面，上述樹脂進而附著於上述第4面，上述第3面之附著有上述樹脂之部分之面積大於上述第4面之附著有上述樹脂之部分之面積。
  5. 如請求項1之半導體裝置，其中上述第1構件具有：無機構件，其具有上述第2面並且由無機材料形成；以及有機層，其具有上述第3面並且由包含上述第1有機材料之材料形成。
  6. 如請求項5之半導體裝置，其中上述第1構件具有位於上述無機構件與上述有機層之間之中間層，上述有機層附著於上述中間層，上述有機層與上述中間層連接之部分之拉伸強度，大於上述有機層附著於上述無機構件之情形之上述有機層與上述無機構件連接之部分之拉伸強度。
  7. 如請求項5之半導體裝置，其中上述第1構件具有中間層，該中間層位於上述無機構件與上述有機層之間，並且由包含上述無機材料之氧化物或氮化物之材料形成，上述有機層附著於上述中間層。
  8. 如請求項5之半導體裝置，其中上述第2電子零件包含由含有上述無機材料之材料形成之層。
  9. 如請求項8之半導體裝置，其中上述無機材料含有矽。
  10. 如請求項1之半導體裝置，其中上述第1構件由包含上述第1有機材料之材料形成。
  11. 如請求項1之半導體裝置，其進而具備埋設於上述樹脂之第2構件，上述第2電子零件具有經積層之複數個第3電子零件，上述第2構件具有：第5面，其處於上述複數個第3電子零件中相鄰之兩個之間，且安裝有上述複數個第3電子零件中之一個；第6面，其安裝有上述複數個第3電子零件中之另一個；以及第7面，其位於上述第5面與上述第6面之間，並且由包含第2有機材料之材料形成；上述樹脂進而附著於上述第7面。
  12. 如請求項11之半導體裝置，其進而具備複數個第2接著層，上述複數個第2接著層分別將上述複數個第3電子零件中之一個安裝於上述複數個第3電子零件中之另一個、上述第3面、或上述第2構件。
  13. 如請求項12之半導體裝置，其中上述第2接著層具有晶粒貼裝膜。
  14. 如請求項1之半導體裝置，其中上述第2電子零件之表面由包含上述第1有機材料之材料形成。
  15. 如請求項1之半導體裝置，其中上述樹脂由包含上述第1有機材料之材料形成。
  16. 如請求項1之半導體裝置，其中上述第1有機材料包含聚醯亞胺樹脂。
  17. 如請求項1之半導體裝置，其中上述第2電子零件具有快閃記憶體，上述第1電子零件具有構成為控制上述快閃記憶體之控制器。
  18. 如請求項1之半導體裝置，其中上述第1接著層具有晶粒貼裝膜。
  19. 如請求項1之半導體裝置，其進而具備第1接合線，該第1接合線將上述第1電子零件與上述基板電性連接，且埋設於上述第1接著層。
  20. 如請求項1之半導體裝置，其進而具備第2接合線，該第2接合線將上述第2電子零件與上述基板電性連接，且被上述樹脂掩埋。
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