JP2005347470A - 半導体パッケージ用中継基板、半導体サブパッケージおよび半導体装置 - Google Patents
半導体パッケージ用中継基板、半導体サブパッケージおよび半導体装置 Download PDFInfo
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- JP2005347470A JP2005347470A JP2004164489A JP2004164489A JP2005347470A JP 2005347470 A JP2005347470 A JP 2005347470A JP 2004164489 A JP2004164489 A JP 2004164489A JP 2004164489 A JP2004164489 A JP 2004164489A JP 2005347470 A JP2005347470 A JP 2005347470A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】 半導体チップマウント封止サブ基板100に設けた突起をパッケージ基板10上に接着している。この半導体チップマウント封止サブ基板100とパッケージ基板10との間に形成される空間に半導体ベアチップ31と32とを配備し、ワイヤリングを可能にしている。
【選択図】 図10
Description
日経エレクトロニクス2002,2−11 no.815 p108 「第1部 チップがダメならパッケージがある」
このとき、半導体パッケージ21及び半導体パッケージ22は、それぞれ半導体ベアチップ30及び半導体ベアチップ31を内蔵し、かつ封止樹脂81によってそれぞれ樹脂封止されている。但し、特開2002−40095に開示されている半導体装置をSIPに適用するにあたっては、半導体パッケージ21の電極40は、半導体パッケージ21を載置している半導体パッケージ22の電極41にワイヤ60によって接続されている。また、半導体パッケージ22の電極41とリードフレームとがワイヤ61によって接続されている。このように、特開2002−40095に開示されている樹脂封止パッケージ(半導体パッケージ21および半導体パッケージ22)は従来のベアチップに比べて、樹脂封止されているがゆえに、その取り扱いが簡単になり、選別試験に使用されるソケットやプローブ、テスターの操作に要求される繊細度は減る、という効果がある。
20‐半導体パッケージ
21‐半導体パッケージ
22‐半導体パッケージ
30‐半導体ベアチップ
31‐半導体ベアチップ
32‐半導体ベアチップ
33‐半導体ベアチップ
34‐半導体ベアチップ
40‐電極
41‐電極
50‐半導体チップマウントサブ基板
60‐ワイヤ
61‐ワイヤ
70‐インターポーザー
80‐封止樹脂
81‐封止樹脂
90‐スペーサー
100‐半導体チップマウント封止サブ基板
110‐試験用電極
120‐実装用電極
130‐内部電極
Claims (6)
- 複数の半導体チップを搭載する基板状またはフレーム状の基材と、前記基材に搭載した複数の半導体チップとを備えた半導体装置のパッケージ構造において、マウントすべき半導体チップの端子を接続する内部電極と、実装時に他の部品に接続される実装用電極と、試験時に試験装置の端子が接続される試験用電極と、前記内部電極と前記実装用電極および前記試験用電極とを電気的に接続する多層配線とを形成したサブ基板に半導体チップがマウントされてなる半導体チップマウントサブ基板を備え、前記半導体チップマウントサブ基板を他の半導体チップとともに前記基材に搭載し、これらの半導体チップマウントサブ基板と他の半導体チップを前記基材とともに樹脂封止したことを特徴とする半導体装置のパッケージ構造。
- 前記半導体チップマウントサブ基板は、前記基材に対する前記樹脂封止とは別に前記半導体チップマウントサブ基板とともに前記半導体チップマウントサブ基板に搭載した一つ以上の半導体チップを樹脂封止して成る請求項1に記載の半導体装置のパッケージ構造。
- 前記半導体チップマウントサブ基板とともに前記半導体チップマウントサブ基板に搭載した一つ以上の半導体チップを樹脂封止して成る前記半導体チップマウントサブ基板において、樹脂封止部分に突起を設けて成る請求項2に記載の半導体装置のパッケージ構造。
- 前記半導体チップマウントサブ基板に、突起を設けて成る請求項1に記載の半導体装置のパッケージ構造。
- 前記半導体チップマウントサブ基板の、前記実装用電極の配列ピッチと、前記試験用電極の配列ピッチとが異なることを特徴とした、請求項1、請求項2、請求項3、請求項4記載の半導体装置のパッケージ構造。
- 複数の半導体チップを搭載する基板状またはフレーム状の基材と、前記基材に搭載した複数の半導体チップとを備えた半導体装置のパッケージ構造において、マウントすべき半導体チップの端子を接続する内部電極と、実装時に他の部品に接続される実装用電極と、試験時に試験装置の端子が接続される試験用電極と、前記内部電極と前記実装用電極および前記試験用電極とを電気的に接続する多層配線とを形成したサブ基板に半導体チップがマウントされてなる半導体チップマウントサブ基板を備え、さらに、複数の電極と、前記電極を電気的に接続する多層配線とを形成したサブ基板を、前記半導体チップマウントサブ基板と他の半導体チップとともに前記基材に搭載し、これらの半導体チップマウントサブ基板と他の半導体チップを前記基材とともに樹脂封止したことを特徴とした、請求項1、請求項2、請求項3、請求項4、請求項5記載の半導体装置のパッケージ構造。
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JP2004164489A JP3842272B2 (ja) | 2004-06-02 | 2004-06-02 | インターポーザー、半導体チップマウントサブ基板および半導体パッケージ |
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JP2004164489A JP3842272B2 (ja) | 2004-06-02 | 2004-06-02 | インターポーザー、半導体チップマウントサブ基板および半導体パッケージ |
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JP2005336256A Division JP4388926B2 (ja) | 2005-11-21 | 2005-11-21 | 半導体装置のパッケージ構造 |
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JP2005347470A true JP2005347470A (ja) | 2005-12-15 |
JP3842272B2 JP3842272B2 (ja) | 2006-11-08 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007287820A (ja) * | 2006-04-14 | 2007-11-01 | Renesas Technology Corp | 電子装置及びその製造方法 |
JP2008147669A (ja) * | 2006-12-09 | 2008-06-26 | Stats Chippac Ltd | 積み重ねられた集積回路パッケージインパッケージシステム |
US8044498B2 (en) | 2006-07-12 | 2011-10-25 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
JP2020009983A (ja) * | 2018-07-12 | 2020-01-16 | キオクシア株式会社 | 半導体装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014027145A (ja) | 2012-07-27 | 2014-02-06 | Toshiba Corp | 半導体装置 |
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2004
- 2004-06-02 JP JP2004164489A patent/JP3842272B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007287820A (ja) * | 2006-04-14 | 2007-11-01 | Renesas Technology Corp | 電子装置及びその製造方法 |
US8044498B2 (en) | 2006-07-12 | 2011-10-25 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
JP2008147669A (ja) * | 2006-12-09 | 2008-06-26 | Stats Chippac Ltd | 積み重ねられた集積回路パッケージインパッケージシステム |
JP2020009983A (ja) * | 2018-07-12 | 2020-01-16 | キオクシア株式会社 | 半導体装置 |
JP7042713B2 (ja) | 2018-07-12 | 2022-03-28 | キオクシア株式会社 | 半導体装置 |
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JP3842272B2 (ja) | 2006-11-08 |
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