WO2005041296A1 - チップマウント用配線シート、シートマウントチップおよびシートマウントチップの製造方法 - Google Patents
チップマウント用配線シート、シートマウントチップおよびシートマウントチップの製造方法 Download PDFInfo
- Publication number
- WO2005041296A1 WO2005041296A1 PCT/JP2004/002342 JP2004002342W WO2005041296A1 WO 2005041296 A1 WO2005041296 A1 WO 2005041296A1 JP 2004002342 W JP2004002342 W JP 2004002342W WO 2005041296 A1 WO2005041296 A1 WO 2005041296A1
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- WIPO (PCT)
- Prior art keywords
- chip
- sheet
- test
- terminal
- semiconductor
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- the present invention relates to a sheet mount chip which is a semiconductor element suitable for a system "in” package (SIP: System in Package) and the like, a method for manufacturing the same, and a wiring sheet for chip mount for manufacturing the sheet mount chip. It is. Background art
- SIP System in Package
- a semiconductor chip 30 is mounted on a package substrate 10
- another semiconductor chip 40 is further mounted on the semiconductor chip 30.
- 0 and the package substrate 10 are wire-bonded with the wire W.
- This technology is described, for example, in Nikkei Electronics 2002, 2-11 no. 815 pl08 "Part 1: There is a package if the chip is useless.”
- the non-defective rate of a SIP in which a plurality of semiconductor chips are contained in one package is a synergistic value of the non-defective rate of each semiconductor chip.
- the semiconductor chip mounted on the SIP be a good chip that has been inspected in advance and confirmed to be good (known good chip, KGD: Known-Good-Die). Or, it was impossible or extremely difficult to perform all operation tests including high-temperature continuous operation test (Burn-in) with bare chips. For this reason, in the conventional SIP, a semiconductor chip which has been subjected to only a basic operation test in a wafer state is mounted, and there is a limit in improving the non-defective product rate.
- An object of the present invention is to provide a sheet mount chip capable of performing a complete operation test on a chip basis and a method of manufacturing the same. Disclosure of the invention
- the present invention relates to a wiring sheet for mounting a plurality of semiconductor chips, comprising: an internal terminal connected to the semiconductor chip mounted on the chip mounting portion; an external terminal connected to another component at the time of mounting; A test terminal to which a terminal of the device is connected, and an internal wiring for electrically connecting the internal terminal with the external terminal and the test terminal are provided for each semiconductor chip.
- the present invention is characterized in that the test terminals are formed outside the chip mount portion with respect to the external terminals.
- the present invention is characterized in that the test terminal is formed at an end of a sheet.
- the present invention is characterized in that the test terminal is common to a plurality of semiconductor chips.
- the chip mounting wiring sheet on which a semiconductor chip is mounted is cut out into a shape including a chip mount portion, an internal terminal and an external terminal, and not including at least a part of a test terminal for each semiconductor chip. It is characterized by having been formed.
- the present invention provides a procedure for mounting a semiconductor chip on the above-mentioned chip mounting wiring sheet, a procedure for connecting a terminal of a test apparatus to a test terminal and testing each semiconductor chip, and for each semiconductor chip, a chip mounting section. , A procedure for cutting into a shape that does not include the test terminal, including the internal terminal and the external terminal.
- the present invention provides a wiring sheet to be attached to a wafer on which a plurality of semiconductor chips are formed, wherein the internal terminals are electrically connected to pads of each semiconductor chip and are formed on the back surface of the attaching surface, An external terminal connected to other components during mounting, a test terminal formed outside the bonding range of the wafer or on the back surface of the bonding surface, and connected to a terminal of a test apparatus during a test; and an internal terminal. And an internal wiring for electrically connecting the external terminal and the test terminal.
- test terminal is formed at an end of a sheet and is common to a plurality of semiconductor chips.
- the present invention is characterized in that a wafer on which a semiconductor chip attached to the chip mounting wiring sheet is formed is cut for each half chip.
- the semiconductor chip is mounted on the wiring sheet for chip mounting, handling in a test device becomes easy, and various tests such as a Burn-i ⁇ test can be performed on the semiconductor chip. Can be performed. Therefore, a sheet mount chip separated from each semiconductor chip can be used as a KGD.
- test terminals by sharing test terminals with a plurality of semiconductor chips, when the test terminals are provided at the end of the sheet, the number of terminals can be reduced even on a sheet on which many semiconductor chips are mounted. it can.
- the wiring sheet for sheet mounting by attaching the wiring sheet for sheet mounting, it is possible to handle the test device as it is as an ueno. Can be determined. Therefore, a sheet mount chip that is separated for each semiconductor chip can be used as KGD.
- FIG. 1 is a view showing a structure of a wiring sheet for chip mounting according to an embodiment of the present invention.
- FIG. 2 is a flowchart illustrating a manufacturing process of a sheet mount chip and a SIP using the same chip mount wiring sheet.
- FIG. 3 is a diagram showing an example of a SIP manufactured in the manufacturing process.
- FIG. 4 is a diagram showing a structure of a wiring sheet for chip mounting according to another embodiment of the present invention.
- FIG. 5 is a view showing the structure of a wiring sheet for chip mounting and a sheet mounting chip according to another embodiment of the present invention.
- FIG. 6 is a cross-sectional view showing a configuration of a conventional semiconductor device.
- FIG. 1 is a diagram showing a chip mounting wiring sheet according to an embodiment of the present invention.
- This chip mounting wiring sheet is a sheet for mounting a plurality of semiconductor chips, electrically connecting them, and then separating them into individual semiconductor chips to manufacture sheet mount chips. Dashed patterns are formed on both sides. It is made of thin resin for possible interposers.
- FIG. 1B shows the chip mounting wiring sheet 200 before the sheet mount chip is separated.
- FIG. 2A is an enlarged view of a unit section 200 ′ corresponding to one semiconductor chip in the chip mount wiring sheet 200.
- the wiring sheet portion 20 at the center of the unit section 20 ' is cut off to form a wiring sheet portion of the sheet mounting chip 60 (see FIG. 3).
- a chip mount area 100 for mounting the semiconductor chip 50 is provided at the center of the wiring sheet section 20. Inside the chip mount area 100, an internal area for flip-chip connection is provided. Terminals (pads) 21 are formed.
- the semiconductor chip 50 is mounted on the chip mounting area 100.
- the terminal (bump) 51 of the semiconductor chip 50 is connected to the internal terminal 21.
- External terminals 22 connected to other components such as a lead frame and other semiconductor chips at the time of mounting are formed inside the wiring sheet portion 2O.
- the external terminal 22 in this embodiment is formed on the same surface as the chip mounting area 100 on which the semiconductor chip 50 is mounted and outside the chip mounting area 100, and the semiconductor chip 50 side Wire bonding connection with other parts.
- the pitch of the external terminals 22 is, for example, 150 / im pitch.
- the internal terminal 21 is provided outside the chip mounting area 100.
- the connection method with other components is bump connection, or when wire bonding connection with other components is performed on the surface opposite to the semiconductor chip 5 O, the external terminals 22 are connected to the semiconductor chip 50 ( Opposite to the surface of the chip mount area 100).
- test terminal 25 is formed outside the wiring sheet portion 20 within the range of the unit section 20 ′.
- the test terminals are terminals to which the test pins of the test device abut, and are formed at a pitch corresponding to the test pins.
- the pitch of the pitch is, for example, about 0.5 mm, and is generally formed larger than the pitch of the external terminals 22.
- the test terminals 25 are formed on the same surface as the chip mount area 100, but may be formed on the opposite surface. This may be determined according to the form of support of the chip mounting wiring sheet 200 during the test.
- the internal terminal 21, the external terminal 22 and the test terminal 25 are connected to each other by internal wirings 23 and 24 formed on the sheet surface or inside.
- Each unit section 20 ′ (chip) of the chip mounting wiring sheet 200 with the above configuration The semiconductor chip 50 is mounted on the chip mount area 100), wiring is performed, and various types of tests are performed by setting the semiconductor chip 50 in a sheet state in a test apparatus.
- This test is performed by setting the chip mounting wiring sheet 200 in a test apparatus.
- the test apparatus connects test pins to the test terminals 25 and performs various reliability tests and operation tests on each semiconductor chip.
- This reliability test is, for example, a high temperature bias test (Burn-in). Then, a non-defective product and a defective product of the semiconductor chip 50 (the sheet mount chip 60 before cutting) are determined.
- the chip mounting wiring sheet 200 is flexible, when the chip mounting wiring sheet 200 is set in a test apparatus and various tests are performed, the chip mounting wiring sheet 200 is placed on a supporting material for supporting the sheet. The sheet 200 may be placed and set on the test device.
- the sheet mount chip 60 is completed by cutting along the outline of the wiring sheet portion 20 indicated by the two-dot chain line in FIG. Among them, a chip mount chip as an inspected chip KGD can be obtained by selecting and excluding chips determined to be defective.
- the sheet mount chip 60 includes a chip mount area 100 on which the semiconductor chip 50 is mounted, an internal terminal 21 and an external terminal 22 from the unit section 20 ′. It is cut into a shape that does not include the test terminal 25. Therefore, in the end region P of the wiring sheet portion 20 cut out as a sheet mount chip, the end of the internal wiring 24 for connecting the external terminal 22 and the test terminal 25 is left. It is in the state of being set.
- FIG. 2 is a flow chart showing a manufacturing process of the sheet mount chip including the above test process.
- the semiconductor chip to be mounted on the chip mounting wiring sheet 200 is tested in a wafer state (S11). Then, the back surface of the wafer is polished and thinned to a predetermined thickness (S12), and the wafer is diced. It is separated into individual semiconductor chips 50 (S13). Of these semiconductor chips, the semiconductor chip 50 which was regarded as a non-defective product was mounted on the chip mounting area 100 of the wiring sheet 200 for chip mounting and subjected to necessary wiring (S14). Seal (S15). This resin encapsulation is for improving the handling in subsequent steps, and does not require mechanical strength.
- the above-described reliability test and operation test are performed on the chip-mounting semiconductor sheet before cutting, and the quality of each semiconductor chip is determined (S16). Thereafter, the area of each wiring sheet portion 20 is cut off (S17) to manufacture the sheet mount chip 60.
- S21 to S27 are flowcharts showing the steps of manufacturing the SIP using the sheet mount chip 60. According to this step, the SIP shown in FIG. 3 is manufactured.
- FIG. 1A is a plan view of the SIP
- FIG. 1B is a cross-sectional view of a main part thereof.
- a semiconductor chip 30 is die-bonded on the upper surface of a package substrate 10, and the above-mentioned sheet mount chip 60 is mounted thereon.
- the seat mount chip 60 has the semiconductor chip 50 mounted thereon. Unlike the embodiment shown in FIG. 1, the terminal 51 of the semiconductor chip 50 and the internal terminal 21 are connected by wire bonding, and the external terminal 22 is connected. Are formed only on one side of the wiring sheet portion 20.
- the sheet mount chip 60 is mounted by bonding the lower surface thereof (the lower surface of the chip mount wiring sheet 20) to the semiconductor chip 30. Separately, the semiconductor chip 40 is mounted on the semiconductor chip 30.
- a plurality of terminals 11 and 11 ' are arranged and formed.
- a plurality of solder poles 12 are arranged and formed on the lower surface of the package substrate 10. The terminals 11 and 11 'on the top of this package substrate 10 The surface and the solder poles 12 are electrically connected via a wiring layer inside the package substrate 10.
- the terminals arranged around the upper surface of the semiconductor chip 30 and the terminals 11 arranged on the upper surface of the package substrate 10 are wire-bonded by wires W31.
- the external terminals 22 of the sheet mount chip 60 are arranged in one line on one side of the wiring sheet part 20, but the arrangement of the external terminals is optimally designed according to the configuration of the SIP. What should I do?
- the external terminal 22 and the terminal 11 ′ of the package substrate 10 are wire-bonded with a wire W21.
- the existing semiconductor can be changed without changing the position, pitch, signal arrangement, etc. of the external connection terminals (pads) of the semiconductor chip. Electrical connection can be easily performed using the chip as it is.
- the semiconductor chip 40 is not designed with the sub-substrate because it is already designed to be used as the SIP together with the semiconductor chip 30.
- the terminal 41 on the upper surface of the semiconductor chip 40 and the terminal 31 formed on the upper surface of the semiconductor chip 30 are wire-bonded with a wire W43. Further, a wire W41 is wire-bonded between the predetermined terminal 41 'of the semiconductor chip 40 and the terminal 11' on the package substrate.
- FIG. 7A shows a state before the resin sealing of the upper portion of the package substrate 10 is performed. After the semiconductor chip is mounted, as shown in FIG. On the upper surface, the entirety of the semiconductor chips 30 and 40, the sheet mount chip 60, and the wires connecting them are sealed with a sealing resin 13 with resin.
- the semiconductor chip 30 is another semiconductor chip, and its size is, for example, 8.5 mm ⁇ 8.5 mm.
- the semiconductor chip 40 is another semiconductor chip.
- the semiconductor chip 50 on the sub-substrate 20 is, for example, 3 2 MX 3 2 It is a bit DRAM and its size is 3. OmmX 5.7mm.
- DRAM has the greatest opportunity to use general-purpose products, and is inexpensive and has a high defect rate. Therefore, by making the DRAM of the SIP into a sheet mount chip, it is possible to realize a drastic cost reduction and a reduction in the defective rate.
- the external length of the wire W21 is reduced by arranging the external terminals 22 on the wiring sheet portion 20 along the terminals 11 'on the package substrate 10.
- the semiconductor chip mounted on the package substrate 10 is first tested in a wafer state (S21). Thereafter, wafer polishing and wafer dicing are performed (S22 ⁇ S23), and each semiconductor chip 30 is mounted on the package substrate 10 (S24). After that, the above-mentioned seat mount chip 60, which is the KGD, is mounted (S25). Subsequently, the upper portion of the package substrate 10 is sealed with resin, and cut into individual package substrates (S26).
- step S27 a good semiconductor device is obtained.
- a test may be performed on a plurality of semiconductor devices before the package substrate is separated, and thereafter, the semiconductor device may be sealed with a resin and separated as a package substrate (S26 ').
- FIG. 4 is a diagram showing another embodiment of a chip mounting wiring sheet.
- a test terminal 25 for connecting this sheet to a test apparatus is formed at an end of the sheet, and no test terminal 25 is formed in each unit section 20 '.
- the chip mounting wiring sheet 200 a plurality of unit sections 20 'are arranged vertically and horizontally in an array, and a vertical wiring 240 connected to a test terminal 25 formed on the upper side of FIG. , Vertical The direction is formed through the rows of unit sections 20 '.
- the internal wiring 23 is connected to this vertical wiring 240, whereby the internal terminal 21 in each unit block 20 ′ is connected to the test terminal 25. It will be.
- a common power supply, a bias voltage, and a test signal are supplied to the semiconductor chips 50 of the plurality of unit sections 20 ′ arranged in the vertical direction.
- the test terminals 25 can be concentrated on one side of the end.
- independent test can be performed on a plurality of semiconductor chips by inputting multiplexed test signals to test signal lines.
- connection between the sheet mount chip and other components is described as being performed by wire bonding and flip chip connection.
- the wiring sheet portion is formed of a flexible sheet, and terminals are provided at both ends thereof.
- this terminal may be connected by crimping to the terminal on the other side to be connected.
- the semiconductor chips diced in chip units are mounted on the chip mounting wiring sheet 200.
- the semiconductor chips 50 are diced in a wafer state before dicing.
- a chip mounting wiring sheet 200 may be attached to the substrate, and an operation test and a reliability test may be performed in a wafer state.
- FIG. 5 is a view for explaining an embodiment in which a chip mount wiring sheet 200 is attached to the semiconductor chip 50 in the wafer state, tested, and then diced to produce a sheet mount chip.
- FIG. 7A is a diagram showing a state in which a chip-mount wiring sheet 200 is attached to the surface of a wafer 70 on which a plurality of semiconductor devices (semiconductor chips) 50 are formed.
- Figure (B) FIG. 3 is a side sectional view showing a state of dicing for each semiconductor chip.
- the chip mounting wiring sheet 200 has two wiring layers, and has, on the surface thereof, internal terminals 21 which are in contact with pads of the semiconductor chip 50 formed on the surface of the wafer 70. Is formed. Then, they are connected to mounting bumps, which are external electrodes 22 on the back surface of the sheet, via the two wiring layers.
- a test terminal 25 is formed on one side (the upper side in the figure) of the rectangular chip mount wiring sheet 20. The terminal 51 of each semiconductor chip 50 is connected to the test terminal 25 via the two wiring layers.
- the semiconductor chip 50 is bonded to the terminal 51 and the internal terminal 21 by aligning with the wafer 70 and pasting.
- test terminal 25 is set on the test apparatus, the test terminals 25 are connected to the electrodes of the test apparatus, and various tests including Burn-in are performed.
- the wafer is set on a dicer and diced, and only chips which are determined to be non-defective in the G / W process and which have been judged to be non-defective in the test by the above-described test apparatus are selected to be KGD sheet mount chips.
- test terminals 25 may be shared by a plurality of semiconductor chips 50.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003364389A JP2007019049A (ja) | 2003-10-24 | 2003-10-24 | チップマウント用配線シート、シートマウントチップおよびシートマウントチップの製造方法 |
JP2003-364389 | 2003-10-24 |
Publications (1)
Publication Number | Publication Date |
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WO2005041296A1 true WO2005041296A1 (ja) | 2005-05-06 |
Family
ID=34510107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2004/002342 WO2005041296A1 (ja) | 2003-10-24 | 2004-02-27 | チップマウント用配線シート、シートマウントチップおよびシートマウントチップの製造方法 |
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Country | Link |
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JP (1) | JP2007019049A (ja) |
WO (1) | WO2005041296A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08504036A (ja) * | 1993-09-30 | 1996-04-30 | アトメル・コーポレイション | エリアアレイ配線チップのtabテスト |
JPH09330961A (ja) * | 1996-06-10 | 1997-12-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2001176940A (ja) * | 1999-12-20 | 2001-06-29 | Sharp Corp | 半導体モジュールの製造方法 |
-
2003
- 2003-10-24 JP JP2003364389A patent/JP2007019049A/ja active Pending
-
2004
- 2004-02-27 WO PCT/JP2004/002342 patent/WO2005041296A1/ja not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08504036A (ja) * | 1993-09-30 | 1996-04-30 | アトメル・コーポレイション | エリアアレイ配線チップのtabテスト |
JPH09330961A (ja) * | 1996-06-10 | 1997-12-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2001176940A (ja) * | 1999-12-20 | 2001-06-29 | Sharp Corp | 半導体モジュールの製造方法 |
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Publication number | Publication date |
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JP2007019049A (ja) | 2007-01-25 |
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