JP4232613B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4232613B2 JP4232613B2 JP2003390502A JP2003390502A JP4232613B2 JP 4232613 B2 JP4232613 B2 JP 4232613B2 JP 2003390502 A JP2003390502 A JP 2003390502A JP 2003390502 A JP2003390502 A JP 2003390502A JP 4232613 B2 JP4232613 B2 JP 4232613B2
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Description
また、この発明は、ボンディングワイヤにより接続され、品質の信頼性を十分に向上することが可能な半導体構成体を能率良く製造することができる半導体装置の製造方法を提供することを目的とする。
図1はこの発明の第1実施形態としての半導体装置の断面図を示す。この半導体装置は、ガラス布基材エポキシ系樹脂等からなる平面矩形形状のベース板1を備えている。ベース板1の4辺部には複数の貫通孔2が設けられている。貫通孔2の近傍におけるベース板1の上下面には、貫通孔2に連続する貫通孔を有する銅箔からなる第1の上層接続パッド3および第1の下層接続パッド4が設けられている。
図14はこの発明の第2実施形態を説明するために示す第1の半導体構成体14の平面図である。まず、図1を参照して説明すると、第1の半導体構成体14は、平面正方形状の半導体基板13の上面4辺部に接続パッド14が配置されていても、再配線20の引き回しにより、接続パッド14に接続された再配線20の接続パッド部の配置位置を図1において左右方向の2辺部のみとすることができる。したがって、図14に示すように、柱状電極21上に設けられた表面処理層22の配置位置を左右方向の2辺部のみとすることができる。
図15はこの発明の第3実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す場合と異なる点は、第1の半導体構成体11は、銅からなる再配線20の接続パッド部上面に表面処理層22を設け、再配線20を含む保護膜17の上面にソルダーレジストからなる絶縁膜23をその上面が表面処理層22の上面と面一となるように設けた点と、第1の半導体構成体11上にベアチップ51を搭載した点である。
上記実施形態では、ベース板1上に2つの半導体構成体11、25を積層した場合について説明したが、これに限らず、3つ以上の半導体構成体を積層するようにしてもよい。ただし、半導体構成体のサイズは上に行くに従って漸次小さくする必要がある。また、半導体構成体とベアチップとは、搭載される位置に関係なく、完全な品質保証がなされないものを半導体構成体とすれば、残りは半導体構成体を用いてもベアチップを用いてもよい。
5 上下導通部
6 上層接続パッド
7 下層接続パッド
8 下層絶縁膜
10 半田ボール
11 第1の半導体構成体
14 接続パッド
20 再配線
21 柱状電極
22 表面処理層
23 封止膜(絶縁膜)
24 第1のボンディングワイヤ
24 第2の半導体構成体
27 表面処理層
28 第2のボンディングワイヤ
29 封止材
Claims (1)
- 複数の接続パッドを有する半導体基板と、前記半導体基板上に前記接続パッドに接続されて設けられた柱状電極と、前記柱状電極を除く部分を覆う絶縁膜とを備えた半導体構成体を、ベース板の接続パッドにワイヤボンディングする半導体装置の製造方法であって、前記柱状電極上に表面処理層を該表面処理層の上面が前記絶縁膜の上面と面一かそれよりも低くなるように形成する工程を有し、
前記柱状電極の周囲における前記半導体基板上に前記絶縁膜を形成した後に、前記柱状電極の上面が前記絶縁膜の上面より低くなるようにエッチングし、次いで、前記柱状電極の上面を含む前記絶縁膜の上面にスパッタ法により表面処理層形成用層を形成し、次いで、少なくとも前記絶縁膜の上面に形成された前記表面処理層形成用層を研磨して除去することにより、前記柱状電極の上面に前記表面処理層を形成することを特徴とする半導体装置の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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JP2003390502A JP4232613B2 (ja) | 2003-11-20 | 2003-11-20 | 半導体装置の製造方法 |
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JP2003390502A JP4232613B2 (ja) | 2003-11-20 | 2003-11-20 | 半導体装置の製造方法 |
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JP2005158768A JP2005158768A (ja) | 2005-06-16 |
JP4232613B2 true JP4232613B2 (ja) | 2009-03-04 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4896010B2 (ja) * | 2005-03-31 | 2012-03-14 | スパンション エルエルシー | 積層型半導体装置及びその製造方法 |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
DE102005041452A1 (de) * | 2005-08-31 | 2007-03-15 | Infineon Technologies Ag | Dreidimensional integrierte elektronische Baugruppe |
JP4851794B2 (ja) | 2006-01-10 | 2012-01-11 | カシオ計算機株式会社 | 半導体装置 |
WO2010106732A1 (ja) * | 2009-03-17 | 2010-09-23 | パナソニック株式会社 | 半導体装置 |
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