JP2014027145A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2014027145A JP2014027145A JP2012166936A JP2012166936A JP2014027145A JP 2014027145 A JP2014027145 A JP 2014027145A JP 2012166936 A JP2012166936 A JP 2012166936A JP 2012166936 A JP2012166936 A JP 2012166936A JP 2014027145 A JP2014027145 A JP 2014027145A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
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- H—ELECTRICITY
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
【解決手段】主面にパッド10Aを有するパッケージ基板10と、パッケージ基板10の主面上に搭載され、半導体チップを含み、パッド11Aを有する半導体パッケージ11と、半導体パッケージ11上に搭載された半導体チップ12と、パッケージ基板11が有するパッド10Aと、半導体パッケージ11が有するパッド11Aとの間に形成されたボンディングワイヤ16とを備える。半導体チップ12は、半導体パッケージ11上にフリップチップにより接続されている。
【選択図】図1
Description
第1実施形態は、半導体チップをパッケージ内に封止した半導体パッケージとベアの半導体チップとが積層された構造を有する。
第2実施形態では、パッケージ基板上に、半導体パッケージ、第1の半導体チップ、第2の半導体チップが積層された半導体装置について説明する。
第3実施形態では、パッケージ基板上に、半導体パッケージ、第1の半導体チップ、第2の半導体チップが順に積層され、第2の半導体チップは第1の半導体チップにフリップチップにより接続された半導体装置について説明する。
第4実施形態では、パッケージ基板上に半導体パッケージが配置され、半導体パッケージ上に第1の半導体チップがフリップチップにより接続された半導体装置について説明する。
Claims (5)
- 第1主面に第1のパッドを有するパッケージ基板と、
前記パッケージ基板の前記第1主面上に搭載され、半導体チップを含み、第2のパッドを有する半導体パッケージと、
前記半導体パッケージ上に搭載された第1の半導体チップと、
前記パッケージ基板が有する前記第1のパッドと、前記半導体パッケージが有する前記第2のパッドとの間に形成された第1のボンディングワイヤと、
を具備し、
前記第1の半導体チップは、前記半導体パッケージ上にフリップチップにより接続されていることを特徴とする半導体装置。 - 第1主面に第1のパッドを有するパッケージ基板と、
前記パッケージ基板の前記第1主面上に搭載され、半導体チップを含み、第2のパッドを有する半導体パッケージと、
前記半導体パッケージ上に搭載された第1の半導体チップと、
前記パッケージ基板が有する前記第1のパッドと、前記半導体パッケージが有する前記第2のパッドとの間に形成された第1のボンディングワイヤと、
を具備することを特徴とする半導体装置。 - 前記半導体パッケージは、複数の半導体チップを有することを特徴とする請求項1または2に記載の半導体装置。
- 前記半導体パッケージは、前記パッケージ基板上に接着材にて固着されていることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記第1の半導体チップは第3のパッドを有し、前記半導体パッケージは第4のパッドを有し、
前記第3のパッドと前記第4のパッドとの間に形成された第2のボンディングワイヤをさらに具備することを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
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JP2012166936A JP2014027145A (ja) | 2012-07-27 | 2012-07-27 | 半導体装置 |
US13/830,778 US8723334B2 (en) | 2012-07-27 | 2013-03-14 | Semiconductor device including semiconductor package |
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JP2012166936A JP2014027145A (ja) | 2012-07-27 | 2012-07-27 | 半導体装置 |
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Cited By (1)
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003298001A (ja) * | 2002-03-29 | 2003-10-17 | Fujitsu Ltd | 電子部品パッケージ |
JP2006216911A (ja) * | 2005-02-07 | 2006-08-17 | Renesas Technology Corp | 半導体装置およびカプセル型半導体パッケージ |
JP2007005800A (ja) * | 2005-06-20 | 2007-01-11 | Stats Chippac Ltd | スタックドチップスケール半導体パッケージを有するモジュール |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010064907A (ko) * | 1999-12-20 | 2001-07-11 | 마이클 디. 오브라이언 | 와이어본딩 방법 및 이를 이용한 반도체패키지 |
US6521881B2 (en) * | 2001-04-16 | 2003-02-18 | Kingpak Technology Inc. | Stacked structure of an image sensor and method for manufacturing the same |
US7049691B2 (en) | 2002-10-08 | 2006-05-23 | Chippac, Inc. | Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package |
JP3842272B2 (ja) | 2004-06-02 | 2006-11-08 | 株式会社Genusion | インターポーザー、半導体チップマウントサブ基板および半導体パッケージ |
JP2006049569A (ja) * | 2004-08-04 | 2006-02-16 | Sharp Corp | スタック型半導体装置パッケージおよびその製造方法 |
US8120156B2 (en) * | 2006-02-17 | 2012-02-21 | Stats Chippac Ltd. | Integrated circuit package system with die on base package |
JP4758871B2 (ja) | 2006-11-14 | 2011-08-31 | 財団法人福岡県産業・科学技術振興財団 | 半導体装置の配線方法 |
KR20090043898A (ko) | 2007-10-30 | 2009-05-07 | 삼성전자주식회사 | 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003298001A (ja) * | 2002-03-29 | 2003-10-17 | Fujitsu Ltd | 電子部品パッケージ |
JP2006216911A (ja) * | 2005-02-07 | 2006-08-17 | Renesas Technology Corp | 半導体装置およびカプセル型半導体パッケージ |
JP2007005800A (ja) * | 2005-06-20 | 2007-01-11 | Stats Chippac Ltd | スタックドチップスケール半導体パッケージを有するモジュール |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7186829B1 (ja) | 2021-06-21 | 2022-12-09 | 三菱電機株式会社 | 制御装置および制御装置の製造方法 |
JP2023001438A (ja) * | 2021-06-21 | 2023-01-06 | 三菱電機株式会社 | 制御装置および制御装置の製造方法 |
US11765817B2 (en) | 2021-06-21 | 2023-09-19 | Mitsubishi Electric Corporation | Control device and manufacturing method of control device |
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