CN111146192A - 使用集成接口和硅中介层的图形处理单元与高带宽存储器集成 - Google Patents

使用集成接口和硅中介层的图形处理单元与高带宽存储器集成 Download PDF

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Publication number
CN111146192A
CN111146192A CN201911066850.0A CN201911066850A CN111146192A CN 111146192 A CN111146192 A CN 111146192A CN 201911066850 A CN201911066850 A CN 201911066850A CN 111146192 A CN111146192 A CN 111146192A
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interposer
semiconductor device
substrate
device assembly
processing unit
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CN201911066850.0A
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C·H·育
O·R·费伊
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请涉及使用集成接口和硅中介层的图形处理单元与高带宽存储器集成。一种半导体装置组合件，其包含连接到衬底的第一侧的中介层的第二侧。多个互连件可连接到所述衬底的第二侧。第一和第二半导体装置直接连接到所述中介层的所述第一侧。所述中介层被配置成使所述第一半导体装置和所述第二半导体装置能够经由所述中介层彼此通信。所述中介层可以是包含互补型金属氧化物半导体电路的硅中介层。所述第一半导体装置可以是处理单元，且所述第二半导体装置可以是存储器装置，其可以是高带宽存储器装置。一种制造半导体装置组合件的方法包含将存储器装置和处理单元两者直接附接到中介层的第一侧，以及将所述中介层的第二侧连接到衬底。

Description

使用集成接口和硅中介层的图形处理单元与高带宽存储器 集成
技术领域
本文中所描述的实施例涉及半导体装置组合件和制造半导体装置组合件的方法，所述半导体装置组合件具有直接连接到中介层的处理单元和存储器装置，所述中介层连接到例如印刷电路板等衬底。所述中介层可以是具有互补型金属氧化物半导体(CMOS)电路的硅中介层。处理单元可以是图形处理单元(GPU)，且存储器装置可以是高带宽存储器装置。
背景技术
高带宽存储器通常是包含动态随机存取存储器(DRAM)的堆叠的高性能随机存取存储器(RAM)接口，所述DRAM的堆叠具有穿过DRAM堆叠的硅穿孔(through silicon vias，TSV)。高带宽存储器通常封装于特定配置中以使高带宽存储器能够由例如(但不限于)图形卡等另一装置使用。
图6展示先前半导体装置组合件400的侧视示意图，其包含由爱达荷州博伊西市(Boise，Idaho)的Micron Technology公司提供的多个混合存储器立方体(HMC)430。HMC包含彼此堆叠的多个存储器单元，通常四(4)个到八(8)个，且使用TSV来互连存储器单元。HMC包含作为单独裸片集成的存储器控制器。HMC的底部表面上的微凸块可用于将HMC连接到另一装置，例如(但不限于)图形卡。
半导体装置组合件400包含衬底或印刷电路板(PCB)410，其具有第一或顶部侧411和与第一侧411相对的第二或底部侧412。硅中介层420连接到衬底410的第一侧411。中介层420具有第一或顶部侧421和与第一侧421相对的第二或底部侧422。衬底410的第二侧412上的多个互连件401可用于将半导体装置组合件400连接到另一装置，如所属领域的一般技术人员将了解。半导体装置组合件400可包含半导体装置组合件400的每一组件之间的多个互连元件(未图示)，如所属领域的一般技术人员将了解。
GPU 440直接连接到中介层420的第一侧421。半导体装置组合件400包含至少一个HMC 430。举例来说，四个HMC 430可连接到半导体装置组合件400。然而，HMC 430不直接连接到中介层420的第一侧421。事实上，每一HMC 430连接到控制器或接口裸片450。接着，由HMC 430和控制器裸片450构成的组合件连接到中介层420。半导体装置组合件400需要每一HMC 430和中介层420之间的控制器裸片450，从而增加了半导体装置组合件400的成本和/或复杂性。
可能存在额外缺陷和缺点。
发明内容
本公开的各个实施例涉及半导体装置、半导体装置组合件、半导体封装、半导体装置封装，以及制造和/或操作半导体装置的方法。
本公开的实施例是一种半导体装置组合件，其包括具有第一侧和第二侧的衬底以及具有第一侧和第二侧的中介层，中介层的第二侧连接到衬底的第一侧。半导体装置组合件包含连接到衬底的第二侧的多个互连件，以及直接连接到中介层的第一侧的第一半导体装置。半导体装置组合件包含直接连接到中介层的第一侧的第二半导体装置，其中中介层被配置成使第一半导体装置和第二半导体装置能够经由中介层彼此通信。
本公开的实施例是一种半导体装置组合件，其包括具有第一侧和第二侧的衬底以及具有第一侧和第二侧的硅中介层，中介层的第二侧连接到衬底的第一侧。硅中介层具有CMOS电路。半导体装置组合件包含直接连接到中介层的第一侧的GPU，以及直接连接到中介层的第一侧的多个存储器装置，其中硅中介层被配置成使GPU和所述多个存储器装置能够经由硅中介层彼此通信。
本公开的实施例是一种制造半导体装置组合件的方法。所述方法包括将存储器装置直接附接到中介层的第一侧上，以及将处理单元直接附接到中介层的第一侧上。所述方法包括将中介层的第二侧附接到衬底的第一侧，其中处理单元和存储器装置被配置成经由中介层彼此通信。
附图说明
图1是半导体装置组合件的实施例的侧视示意图。
图2是半导体装置组合件的实施例的俯视示意图。
图3是半导体装置组合件的实施例的横截面示意图。
图4是制造半导体装置组合件的方法的实施例的流程图。
图5是制造半导体装置组合件的方法的实施例的流程图。
图6是先前半导体装置组合件的侧视示意图。
图7是制造半导体装置组合件的先前方法的流程图。
虽然本公开容许各种修改和替代形式，但具体实施例已经在图中借助于实例展示且将在本文中详细描述。然而，应理解，本公开并不希望限于所公开的特定形式。实际上，意图是涵盖属于如由所附权利要求书界定的本公开的范围内的所有修改、等效物和替代物。
具体实施方式
在本公开中，论述了许多具体细节以提供对本公开的实施例的透彻且启发性描述。所属领域的一般技术人员将认识到，可在并无具体细节中的一或多个的情况下实践本公开。可能未展示和/或可能未详细描述常常与半导体装置和半导体装置封装相关联的众所周知的结构和/或操作，以免混淆本公开的其它方面。一般来说，应理解，除了本文中所公开的那些具体实施例之外的各种其它装置、系统和/或方法也可在本公开的范围内。
术语“半导体装置组合件”可以指一或多个半导体装置、半导体装置封装和/或衬底的组合件，所述衬底可包含中介层、支撑件和/或其它合适的衬底。半导体装置组合件可制造为但不限于离散封装形式、条带或矩阵形式和/或晶片面板形式。术语“半导体装置”通常是指包含半导体材料的固态装置。半导体装置可包含例如半导体衬底、晶片、面板，或与晶片或衬底分开的裸片。半导体装置在本文中可指代一种半导体裸片，但半导体装置不限于半导体裸片。
如本文中所使用，术语“竖直”、“横向”、“上部”和“下部”可指代图式中所展示的特征在半导体装置和/或半导体装置组合件中的相对方向或位置。举例来说，“上部”或“最上部”可指代比另一特征更接近页面顶部定位的特征。然而，这些术语应被广义地解释为包含具有例如颠倒或倾斜定向等其它定向的半导体装置和/或半导体装置组合件，其中顶部/底部、上方/下方、高于/低于、向上/向下和左边/右边可取决于定向而互换。
图1是半导体装置组合件100的实施例的侧视示意图。半导体装置组合件100包含衬底110，其具有第一或顶部侧111和与第一侧111相对的第二或底部侧112。衬底110可为但不限于层压衬底，例如印刷电路板(PCB)。中介层120连接到衬底110的第一侧111。中介层120具有第一或顶部侧121和与第一侧121相对的第二或底部侧122。
第一半导体装置140直接连接到中介层120的第一侧121。同样，第二半导体装置130直接连接到中介层120的第一侧121。第一半导体装置140可以是处理单元，例如(但不限于)GPU或中央处理单元(CPU)。第二半导体装置130可以是存储器装置。中介层120可以是硅中介层。CMOS处理可能已应用于硅中介层以使中介层120能够被配置成实现经由硅中介层120在第一半导体装置140和第二半导体装置130之间的通信。中介层120上的CMOS处理在中介层120内形成CMOS晶体管栅极，其充当用于第一半导体装置140、第二半导体装置130和/或外部装置之间的数据传送的缓冲器，所述外部装置经由所述多个互连件101连接到半导体装置组合件100。CMOS晶体管栅极还可充当用以控制第一半导体装置140、第二半导体装置130和/或外部装置之间的数据传送的逻辑，所述外部装置经由所述多个互连件101连接到半导体装置组合件100。
在一实施例中，第二半导体装置130可为但不限于高带宽存储器装置。如本文中所使用，高带宽存储器装置是任选地包含基底裸片的DRAM裸片与存储器控制器的堆叠，它们通过硅穿孔(TSV)互连，且在底侧上具有微凸块，即由爱达荷州博伊西市的MicronTechnology公司提供的HMC等。
图2是半导体装置组合件100的实施例的俯视示意图。半导体装置组合件100包含具有第一或顶部侧111的衬底110。衬底110可为但不限于层压衬底，例如PCB。中介层120连接到衬底110的第一侧111。中介层120具有第一或顶部侧121。第一半导体装置140直接连接到中介层120的第一侧121。同样，多个第二半导体装置130直接连接到中介层120的第一侧121。第一半导体装置140可以是处理单元，例如(但不限于)GPU，且第二半导体装置130可以是高带宽存储器装置。中介层120可以是硅中介层。CMOS处理可能已应用于硅中介层以使中介层120能够被配置成实现经由硅中介层120在第一半导体装置140和第二半导体装置130之间的通信。
图3是半导体装置组合件100的实施例的横截面示意图。半导体装置组合件100包含一或多个高带宽存储器装置130。高带宽存储器装置130是电连接在一起的存储器单元或裸片131A-131F的堆叠，如获得本公开的益处的所属领域的一般技术人员将理解。出于说明性目的展示存储器单元131A-131F的数目，且其可取决于应用而变化，如所属领域的一般技术人员将理解。高带宽存储器装置130通过多个互连件103直接连接到中介层120。处理单元140也通过多个互连件104直接连接到中介层120。
中介层120可以是硅中介层，且包含第一或顶部侧121和第二或底部侧122。CMOS处理可应用于如本文所论述的中介层120，如CMOS层125示意性地指示。中介层120的CMOS层125包含CMOS晶体管栅极，如获得本公开的益处的所属领域的一般技术人员将理解。出于说明性目的展示CMOS层125的大小、形状、位置和/或配置，且其可变化，如获得本公开的益处的所属领域的一般技术人员将理解。
中介层120的一部分可包含后段工艺(BEOL)层123。BEOL层123可包括交替的电介质层123A和导电层123B。BEOL层123提供中介层120内的布线层，且将高带宽存储器装置130和处理单元140电连接到延伸穿过中介层120的多个TSV 124，如所属领域的一般技术人员将理解。所述多个TSV 124将高带宽存储器装置130和处理单元140连接到中介层120的第二侧122上的多个互连件102。互连件102实现到衬底110(其可以是PCB)的电连接。衬底110包含第一或顶部侧111和第二或底部侧112。衬底110的第二侧112上的多个互连件101使半导体装置组合件100能够连接到另一装置，如获得本公开的益处的所属领域的一般技术人员将理解。
图4是制造半导体装置组合件的方法200的实施例的流程图。方法200包括在210处将存储器装置直接附接到中介层的第一表面上。方法200包含在220处将处理单元直接附接到中介层的第一表面上。在230处，方法200包含将中介层的第二表面附接到衬底的第一表面，其中处理单元和存储器装置被配置成经由中介层彼此通信。
方法200可包含在205处在将存储器装置直接附接到中介层之前将CMOS处理应用于中介层。方法200可包含在215处将第二存储器装置直接附接到中介层的第一表面。多个存储器装置可直接附接到中介层的第一表面。存储器装置可以是高带宽存储器装置。在220处，处理单元可以是GPU。
图5是制造半导体装置组合件的方法300的实施例的流程图。方法300包含在310处提供具有附接到晶片的多个处理单元的所述晶片，且单分所述晶片以产生多个个别处理单元。所述处理单元可以是图形处理单元。在320处，方法300包含将多个半导体装置附接到中介层晶片上。半导体装置可以是存储器装置，且确切地说可以是高带宽存储器装置。方法300包含在330处将多个个别处理单元附接到中介层晶片。处理单元结合一或多个半导体装置附接到中介层晶片。
方法300包含在340处将中介层晶片单分为各自含有至少一个处理单元和至少一个半导体装置的多个单元。方法300包含在350处提供衬底，以及在360处将个别单元附接到衬底上，以形成半导体装置组合件。所述个别单元是由340处中介层晶片的单分形成的单元。方法300包含在370处模制和/或碾磨衬底的部分，以较好地实现焊球到衬底的部分的附接和/或大体防止硅受到外部应力和/或环境的影响。方法300包含在380处将多个焊球附接到衬底。半导体装置组合件接着可连接到另一装置，例如(但不限于)图形卡。
制造半导体装置组合件的方法300实现使用比当前方法少的步骤产生多个半导体装置组合件。制造半导体装置组合件的方法300使如本文关于图7展示的制造半导体装置组合件的先前过程或方法呈流线型。
图7是制造半导体装置组合件的先前方法500的流程图。方法500包含在510处提供处理器晶片，以及在515处单分处理器晶片以产生多个个别处理单元。方法500需要在520处将例如高带宽存储器装置等多个半导体装置附接到控制器或接口晶片，以及在525处单分控制器晶片以提供附接到控制器裸片的个别半导体装置。
方法500包含在530处提供中介层晶片，以及在540处将中介层晶片单分为个别裸片。方法500包含在550处提供衬底，以及在555处将中介层裸片附接到衬底上。在中介层裸片附接到衬底之后，方法500包含在560处将附接有半导体装置的控制器裸片附接到中介层裸片上。半导体装置组合件可包含多个半导体装置。每一半导体装置在520处附接到控制器晶片，且在525处当控制器晶片单分时将附接到控制器裸片。每一半导体装置接着将需要在560处经由附接的控制器裸片附接到中介层裸片。方法500包含在565处将个别处理单元附接到中介层裸片上。方法500包含在570处模制和/或碾磨衬底的部分，以较好地实现焊球到衬底的部分的附接和/或大体防止硅受到外部应力和/或环境的影响。方法500包含在580处将多个焊球附接到衬底。半导体装置组合件接着可连接到另一装置，例如(但不限于)图形卡。
尽管已经关于某些实施例描述了本公开，但所属领域的一般技术人员清楚的其它实施例，包含并不提供本文中所阐述的所有特征和优点的实施例，同样在本公开的范围内。本公开可涵盖本文中未明确地展示或描述的其它实施例。因此，本公开的范围仅参考所附权利要求书和其等效物界定。

Claims (24)

1.一种半导体装置组合件，其包括：
衬底，其具有第一侧和第二侧；
中介层，其具有第一侧和第二侧，所述中介层的所述第二侧连接到所述衬底的所述第一侧；
多个电互连件，其连接到所述衬底的所述第二侧；
第一半导体装置，其直接连接到所述中介层的所述第一侧；以及
第二半导体装置，其直接连接到所述中介层的所述第一侧，其中所述中介层被配置成使所述第一半导体装置和所述第二半导体装置能够经由所述中介层彼此通信。
2.根据权利要求1所述的半导体装置组合件，其中所述中介层为由硅构成的衬底。
3.根据权利要求2所述的半导体装置组合件，其中所述衬底包括层压衬底。
4.根据权利要求3所述的半导体装置组合件，其中所述中介层进一步包括互补型金属氧化物半导体电路。
5.根据权利要求4所述的半导体装置组合件，其中所述多个互补型金属氧化物半导体电路提供用于所述第一半导体装置和所述第二半导体装置之间的数据传送的缓冲器。
6.根据权利要求5所述的半导体装置组合件，其中所述多个互补型金属氧化物半导体电路提供用以控制所述第一半导体装置和所述第二半导体装置之间的数据传送的逻辑。
7.根据权利要求4所述的半导体装置组合件，其中所述第一半导体装置为处理单元。
8.根据权利要求7所述的半导体装置组合件，其中所述处理单元进一步包括图形处理单元GPU或中央处理单元CPU。
9.根据权利要求8所述的半导体装置组合件，其中所述第二半导体装置为存储器装置。
10.根据权利要求9所述的半导体装置组合件，其中所述存储器装置进一步包括高带宽存储器装置。
11.根据权利要求9所述的半导体装置组合件，其进一步包括直接连接到所述中介层的所述第一侧的第三半导体装置，其中所述第三半导体装置为存储器装置，且其中所述中介层被配置成使所述GPU或CPU和所述第三半导体装置能够经由所述中介层彼此通信。
12.根据权利要求11所述的半导体装置组合件，其中所述中介层实现所述层压衬底和所述GPU或CPU之间的通信，且实现所述层压衬底和所述存储器装置之间的通信。
13.一种半导体装置组合件，其包括：
衬底，其具有第一侧和第二侧；
硅中介层，其具有第一侧和第二侧，所述中介层的所述第二侧连接到所述衬底的所述第一侧，所述硅中介层具有互补型金属氧化物半导体电路；
图形处理单元GPU或中央处理单元CPU，其直接连接到所述中介层的所述第一侧；以及
多个存储器装置，其直接连接到所述中介层的所述第一侧，其中所述硅中介层被配置成使所述GPU或CPU和所述多个存储器装置能够经由所述硅中介层彼此通信。
14.根据权利要求13所述的半导体装置组合件，其中所述互补型金属氧化物半导体电路提供用于所述GPU或CPU和所述多个存储器装置之间的数据传送的缓冲器。
15.根据权利要求14所述的半导体装置组合件，其中所述衬底为印刷电路板。
16.根据权利要求15所述的半导体装置组合件，其中所述多个存储器装置包括至少两个高带宽存储器装置。
17.一种制造半导体装置组合件的方法，其包括：
将存储器装置直接附接到中介层的第一侧上；
将处理单元直接附接到所述中介层的所述第一侧上；以及
将所述中介层的第二侧附接到衬底的第一侧，其中所述处理单元和所述存储器装置被配置成经由所述中介层彼此通信。
18.根据权利要求17所述的方法，其包括在将所述存储器装置直接附接到所述中介层的所述第一侧上之前将互补型金属氧化物半导体处理应用于所述中介层。
19.根据权利要求18所述的方法，其包括将第二存储器装置直接附接到所述中介层的所述第一侧，且其中所述衬底包括印刷电路板。
20.一种制造半导体装置组合件的方法，其包括：
将多个半导体装置附接到中介层晶片的第一侧上；
将多个个别处理单元附接到所述中介层晶片的所述第一侧上；
处理所述中介层晶片以形成各自包括至少一个半导体装置和个别处理单元的多个个别半导体装置组合件；以及
将个别半导体装置组合件的第二侧附接到衬底的第一侧。
21.根据权利要求20所述的方法，其包括在将所述多个半导体装置附接到中介层晶片的第一侧上之前将互补型金属氧化物半导体处理应用于所述中介层晶片。
22.根据权利要求21所述的方法，其包括提供具有连接到晶片的一侧的所述多个图形处理单元的所述晶片，以及处理所述晶片以形成所述多个个别处理单元。
23.根据权利要求22所述的方法，其中所述个别处理单元包括图形处理单元或中央处理单元。
24.根据权利要求23所述的方法，将多个焊球附接到所述衬底的第二侧。
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