CN108074919B - 堆叠式半导体封装件 - Google Patents

堆叠式半导体封装件 Download PDF

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CN108074919B
CN108074919B CN201710963144.0A CN201710963144A CN108074919B CN 108074919 B CN108074919 B CN 108074919B CN 201710963144 A CN201710963144 A CN 201710963144A CN 108074919 B CN108074919 B CN 108074919B
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semiconductor package
semiconductor
semiconductor chips
redistribution
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CN108074919A (zh
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李俊镐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种堆叠式半导体封装件，其具有各种尺寸的各种类型的半导体芯片并且能够小型化。堆叠式半导体封装件包括基体基底层和设置在基体基底层的顶表面上的子半导体封装件。子半导体封装件包括：多个子半导体芯片，彼此分隔开；子模层，填充多个子半导体芯片之间的空间，以围绕多个子半导体芯片的侧表面。堆叠式半导体封装件包括堆叠在子半导体封装件上的至少一个主半导体芯片，至少一个主半导体芯片通过第一电连接构件电连接到基体基底层。

Description

堆叠式半导体封装件
本申请要求于2016年11月10日在韩国知识产权局提交的第10-2016-0149557号韩国专利申请的优先权的权益，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本公开涉及一种堆叠式半导体封装件，更具体地，涉及一种具有具备各种尺寸的多个半导体芯片的堆叠式半导体封装件。
背景技术
随着电子工业的快速发展，电子装置已经被制造为尺寸缩减的且轻量的，并且具有高容量。因此，已经开发出包括多个半导体芯片的半导体封装件。此外，已经开发出其中的每个包括具有各种尺寸的各种类型的半导体芯片的半导体封装件。期望这些半导体封装件继续减小尺寸和重量。
发明内容
公开的实施例提供一种堆叠式半导体封装件，所述堆叠式半导体封装件具有具备各种面积的各种类型的半导体芯片并能够小型化。
根据发明构思的一方面，一种堆叠式半导体封装件包括：基体基底层；子半导体封装件，设置在基体基底层的顶表面上。子半导体封装件包括：多个子半导体芯片，彼此水平地分隔开；子模层，填充所述多个子半导体芯片之间的空间，以围绕所述多个子半导体芯片的侧表面；再分配结构，设置在所述多个子半导体芯片的有源表面上以及子模层上，再分配结构包括电连接到基体基底层的再分配焊盘以及被构造为将所述多个子半导体芯片中的至少一些与再分配焊盘连接的再分配导电层。堆叠式半导体封装件包括堆叠在子半导体封装件上的至少一个主半导体芯片，所述至少一个主半导体芯片通过第一电连接构件电连接到基体基底层。
根据发明构思的另一方面，一种堆叠式半导体封装件包括：子半导体封装件，所述子半导体封装件包括水平地彼此分隔开的多个子半导体芯片、填充所述多个子半导体芯片之间的空间的子模层以及包括再分配焊盘和再分配导电层的再分配结构，再分配导电层被构造为将所述多个子半导体芯片中的至少一些与再分配焊盘连接，再分配结构位于所述多个子半导体芯片的有源表面上以及子模层上；多个主半导体芯片，每个主半导体芯片具有与子半导体封装件的面积相同的面积，所述多个主半导体芯片以阶梯形式堆叠在子半导体封装件上。
根据发明构思的另一方面，一种堆叠式半导体封装件包括基体封装件基底和设置在基体封装件基底上的子半导体封装件。子半导体封装件包括：多个第一半导体芯片，彼此水平地分隔开，当从平面图观察时，其中的至少两个第一半导体芯片具有彼此不同的面积；子模层，填充所述第一半导体芯片之间的空间；子封装件基底，设置在所述多个第一半导体芯片和子模层上。所述堆叠式半导体封装件还至少包括设置在子半导体封装件上的第二半导体芯片。当从平面图观察时，所述第二半导体芯片具有比所述多个第一半导体芯片中的每个的面积大的面积。所述堆叠式半导体封装件还包括覆盖子半导体封装件和第二半导体芯片的模层。从平面图观察时，子半导体封装件可以具有与第二半导体芯片的面积相同的面积。
附图说明
通过下面结合附图的详细描述，将更清楚地理解各种实施例，其中：
图1A和图1B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图2A和图2B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图3A和图3B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图4A和图4B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图5A和图5B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图6A和图6B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图7A和图7B是根据实施例的堆叠式半导体封装件的部分的剖视图和平面布局；
图8A至图8F是根据实施例的制造子半导体封装件的方法的顺序工艺操作的剖视图；
图9是根据实施例的制造子半导体封装件的方法的剖视图；
图10A至图10C是根据实施例的制造子半导体封装件的方法的顺序工艺操作的剖视图；
图11是根据实施例的制造子半导体封装件的方法的剖视图；
图12是根据实施例的系统的框图。
具体实施方式
在附图中，为了清楚起见，可以夸大层和区域的尺寸和相对尺寸。同样的标号始终指示同样的元件。虽然不同的附图示出示例性实施例的变型，但是这些附图未必意图彼此互相排斥。相反，如从下面详细描述的上下文中将看出的，当将附图及其描述作为整体考虑时，不同附图中描绘和描述的某些特征可以与其它附图的其它特征结合以产生各种实施例。
将理解的是，尽管这里可以使用术语第一、第二、第三等描述各种元件、组件、区域、层和/或部分，但这些元件、组件、区域、层和/或部分不应受这些术语的限制。除非上下文另外指出，否则这些术语仅用于将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开，例如如命名惯例一样。因此，在不脱离本发明的教导的情况下，下面在说明书的一个部分中讨论的第一元件、组件、区域、层或部分可以在说明书的另一部分中或在权利要求书中被称为第二元件、组件、区域、层或部分。另外，在某些情况下，即使术语在说明书中不使用“第一”、“第二”等来描述，它在权利要求中也仍可以被称作“第一”或“第二”，以便将要保护的不同的元件彼此区分开。
将理解的是，当元件被称作“连接”或“结合”到另一元件或者“在”另一元件“上”时，它可以直接连接或结合到所述另一元件、或者在所述另一元件上，或者可以存在中间元件。相反，当元件被称作“直接连接”或“直接结合”到另一元件、或者“接触”另一元件或与另一元件“接触”时，不存在中间元件。用于描述元件之间关系的其它词语应该以类似的方式来解释(例如，“在……之间”与“直接在……之间”，“相邻的”与“直接相邻的”等)。
将参照以理想示意图方式的平面图和/或剖视图来描述这里所描述的实施例。因此，可以根据制造技术和/或公差来修改示例性视图。因此，所公开的实施例不限于图中所示的实施例，而是包括基于制造工艺形成的构造的修改。因此，图中例示的区域可以具有示意性质，图中所示的区域的形状可以例示发明的方面不限于其的元件的区域的特定形状。
为了易于描述，在这里可以使用诸如“在……下面”、“在……下方”、“下面的”、“在……上方”、“上面的”等的空间相对术语来描述如附图中所示的一个元件或特征与另一元件或特征的关系。将理解的是，除了附图中描绘的方位之外，空间相对术语还意图包含装置在使用或操作中的不同方位。例如，如果图中的装置被翻转，则被描述为在其它元件或特征“下方”或“下面”的元件随后将被定位为在所述其它元件或特征“上方”。因此，术语“在……下方”可以包括上方和下方两种方位。装置可被另外定位(例如，旋转90度或者在其它方位)，并且相应地解释这里使用的空间相对描述语。
当涉及方位、布局、位置、形状、尺寸、数量或其它计量时，如这里所使用的诸如“相同”、“相等”、“平面”或“共面”的术语并不一定意味着精确相同的方位、布局、位置、形状、尺寸、数量或其它计量，而是意图包含例如由于制造工艺而可能发生的可接受的变化内的几乎相同的方位、布局、位置、形状、尺寸、数量或其它计量。除非上下文或其它陈述另有指示，否则这里可以使用术语“基本上”来强调这一含义。例如，被描述为“基本上相同”、“基本上相等”或“基本上平面”的项可以精确相同、相等或平面，或者可以在例如由于制造工艺而可能发生的可接受的变化内的相同、相等或平面。
如这里所使用的，被描述为“电连接”的项被构造为使得电信号可以从一项传递到另一项。因此，物理地连接到无源电绝缘组件(例如，印刷电路板的预浸料层、连接两个器件的电绝缘粘合剂、电绝缘底部填充物或模层等)的无源导电组件(例如，布线、焊盘、内部电线等)不与该组件电连接。此外，通过一个或更多个无源元件(诸如，以布线、焊盘、内部电线、通孔等为例)将彼此“直接电连接”的项电连接。如此，直接电连接的组件不包括通过有源元件(诸如晶体管或二极管)电连接的组件。直接电连接的元件可以直接物理连接并直接电连接。
图1A和图1B是根据实施例的堆叠式半导体封装件1的部分的剖视图和平面布局。
参照图1A和图1B，堆叠式半导体封装件1可以包括子半导体封装件100以及堆叠在子半导体封装件100上的至少一个主半导体芯片200，所述子半导体封装件100可以设置在基体基底层10(也被描述为基体基底、封装件基底或基体封装件基底)上并具有多个子半导体芯片(例如，第一子半导体芯片110、第二子半导体芯片120和第三子半导体芯片130)以及堆叠在子半导体封装件100上的至少一个主半导体芯片(例如，被描述为一个或更多个主半导体芯片200或者主半导体芯片200)。在不同的实施例中，子半导体芯片中的每个可以被描述为“第一半导体芯片”，使得子半导体封装件100可以包括多个“第一半导体芯片”，主半导体芯片200中的每个可以被描述为“第二半导体芯片”。该示例中的术语“第一”和“第二”可以互换并且仅用于命名的目的，并且这些术语可以应用于这里描述的其它实施例。
如这里所使用的，主半导体芯片和子半导体芯片可以不指在它们之间具有主要与从属的关系或者一个芯片位于另一个芯片顶上或下方。相反，具有相对大面积的半导体芯片将被称作主半导体芯片，而具有相对小面积(例如，与主半导体芯片相比)的半导体芯片将被称作子半导体芯片。例如，堆叠式半导体封装件1可以包括主半导体芯片200以及多个子半导体芯片110、120和130，所述主半导体芯片200是在包括在堆叠式半导体封装件1中的半导体芯片中的具有最大面积的一个半导体芯片或多个半导体芯片，所述子半导体芯片110、120和130具有比主半导体芯片200小的面积(面积是从平面图观察到的)。
基体基底层10可以是例如印刷电路板(PCB)、陶瓷基底、插入件或再分配层。在一些实施例中，基体基底层10可以是其上堆叠有多个基体层12的多层PCB。在一些实施例中，多个基体层12中的每个可以包括从由酚醛树脂、环氧树脂和聚酰亚胺组成的组中选择的至少一种材料。例如，多个基体层12中的每个可以包括从由阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧/聚苯醚、双马来酰亚胺三嗪(BT)、聚酰胺短纤席材(Thermount)、氰酸酯、聚酰亚胺和液晶聚合物组成的组中选择的至少一种材料。
多个顶部连接焊盘(例如，第一顶部连接焊盘14a和第二顶部连接焊盘14b)可以设置在基体基底层10的顶表面上，多个底部连接焊盘14c可以设置在基体基底层10的底表面上。这里描述的装置或基底的各种焊盘可以是分别连接到装置或基底的内部布线的导电端子，并且可以在装置或基底的内部布线和/或内部电路与外部源之间传输信号和/或电源电压，或者将信号和/或电源电压传输到另一个装置或基底。例如，半导体芯片的芯片焊盘可以电连接到半导体芯片的集成电路和与半导体芯片连接的装置并且在半导体芯片的集成电路和与半导体芯片连接的装置之间传输电源电压和/或信号。各种焊盘可以设置在装置或基底的外部表面上或外部表面附近，并且通常可以具有平面表面积(通常大于它们连接到的内部布线的相应的表面积)，以促进与另一端子(诸如凸块或焊球和/或内部或外部布线)的连接。
内部互连件和多个导电过孔可以形成在基体基底层10中，以将顶部连接焊盘14a和14b与底部连接焊盘14c连接。内部互连件可以分别处于多个基体层12之间，多个导电过孔可以分别穿透多个基体层12。在一些实施例中，互连图案还可以设置在基体基底层10的顶表面和底表面中的至少一个上，并且可以将顶部连接焊盘14a和14b和/或底部连接焊盘14c与导电过孔连接。
顶部连接焊盘14a和14b、底部连接焊盘14c、内部互连件和/或互连图案可以包括例如电解沉积(ED)铜箔、轧制退火(RA)铜箔、不锈钢箔、铝箔、超薄铜箔、溅射铜和铜合金。导电过孔可以包括例如铜、镍或铍铜。
第一阻焊层16a和第二阻焊层16b可以分别形成在基体基底层10的顶表面和底表面上。第一阻焊层16a可以暴露顶部连接焊盘14a和14b并且覆盖多个基体层12的顶表面。第二阻焊层16b可以暴露底部连接焊盘14c并覆盖多个基体层12的底表面。外部连接端子18可以粘附到设置在基体基底层10的底表面上的底部连接焊盘14c。外部连接端子18可以是例如焊球或凸块。外部连接端子18可以将堆叠式半导体封装件1与外部设备电连接。
设置在基体基底层10的顶表面上的第一顶部连接焊盘14a和第二顶部连接焊盘14b可以包括连接到子半导体封装件100的多个第一顶部连接焊盘14a和连接到主半导体芯片200的多个第二顶部连接焊盘14b。在一些实施例中，顶部连接焊盘14a和14b中的一些可以共同连接到子半导体封装件100和主半导体芯片200。
多个第一顶部连接焊盘14a和多个第二顶部连接焊盘14b可以分别设置为与基体基底层10的顶表面的不同侧相邻。
包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以包括例如硅(Si)。可替换地，包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以包括半导体元素(例如，锗(Ge))或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和磷化铟(InP)的化合物半导体。可替换地，包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以具有绝缘体上硅(SOI)结构。例如，包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以包括埋置氧化物(BOX)层。包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以包括导电区域，例如，掺杂的阱。包括在子半导体芯片110、120和130和/或主半导体芯片200中的半导体基底可以包括各种隔离结构中的一种，诸如浅沟槽隔离(STI)结构。子半导体芯片110、120、130和主半导体芯片200中的不同的半导体芯片可以包括由相同材料和结构形成的半导体基底，或者可以包括由不同材料和结构形成的半导体基底。
子半导体芯片110、120和130和/或主半导体芯片200均可以构成包括各种类型的独立装置的半导体装置。多个独立装置可以包括各种微电子装置，例如，金属氧化物半导体场效应晶体管(MOSFET)(例如，互补金属氧化物半导体(CMOS)晶体管)、系统大规模集成(LSI)、图像传感器(例如，CMOS成像传感器(CIS))、微机电系统(MEMS)、有源装置和/或无源装置。多个独立装置可以电连接到包括在子半导体芯片110、120和130和/或主半导体芯片200中的每个中的半导体基底的导电区域。每个半导体装置还可以包括导电互连件或导电插塞，所述导电互连件或导电插塞被构造为电连接多个独立装置中的至少两个，或者将多个独立装置与包括在第一子半导体芯片110、第二子半导体芯片120和第三子半导体芯片130和/或主半导体芯片200中的半导体基底的导电区域电连接。此外，多个独立装置中的每个可以通过绝缘膜与其它相邻的独立装置电隔离。
在一些实施例中，子半导体封装件100可以包括至少一个第一子半导体芯片110、第二子半导体芯片120和第三子半导体芯片130。虽然图1A和图1B示出了子半导体封装件100包括四个第一子半导体芯片110的情况，但是发明构思不限于此。例如，子半导体封装件100可以包括一个第一子半导体芯片110或者两个或六个第一子半导体芯片110。
所述至少一个第一子半导体芯片110可以是例如易失性存储器半导体芯片(诸如动态随机存取存储器(DRAM)半导体芯片)。然而，发明构思不限于此。例如，在一些实施例中，至少一个第一子半导体芯片110可以是高带宽存储器(HBM)DRAM半导体芯片。
第二子半导体芯片120可以是例如用于主半导体芯片200的控制器半导体芯片。第二子半导体芯片120可以在主机与主半导体芯片200之间提供接口和协议。第二子半导体芯片120可以提供诸如并行高级技术附件(PATA)、串行高级技术附件(SATA)、小型计算机系统接口(SCSI)或外围组件快速接口(PCIe)的标准协议，以在主半导体芯片200与主机之间提供接口。此外，第二子半导体芯片120可以执行磨损均衡操作、垃圾收集操作、坏块管理操作以及纠错码(ECC)操作，以支持主半导体芯片200。
第三子半导体芯片130可以是例如集成无源装置(IPD)或虚设半导体芯片。在一些实施例中，可以设置多个第三子半导体芯片130。多个第三子半导体芯片130可以包括多个IPD和多个虚设半导体芯片。可替换地，多个第三子半导体芯片130可以包括至少一个IPD和至少一个虚设半导体芯片。IPD可以包括设置在半导体基底上的电阻器和电容器。可选地，IPD还可以包括设置在半导体基底上的二极管和/或电感器。例如，IPD或虚设半导体芯片可以不用作逻辑和/或存储器装置。在一些实施例中，子半导体封装件100可以不包括第三子半导体芯片130。
子半导体封装件100可以包括第一子半导体芯片110、第二子半导体芯片120和第三子半导体芯片130、被构造为围绕多个子半导体芯片110、120和130的子模层140以及设置在多个子半导体芯片110、120和130的有源表面上与子模层140上的再分配结构150。
在子半导体封装件100中，多个子半导体芯片110、120和130可以彼此分隔开(例如，水平地分隔开)，并且子半导体芯片110、120和130之间的空间可以填充有子模层140。子模层140可以包括例如环氧模塑化合物(EMC)。在一些实施例中，子模层140可以暴露多个子半导体芯片110、120和130中的每个的顶表面和底表面，并且可以仅围绕和/或覆盖多个子半导体芯片110、120和130中的每个的侧表面。在一些实施例中，子模层140的面向再分配结构150的顶表面可以与多个子半导体芯片110、120和130中的每个的有源表面共面。在一些实施例中，子模层140的背离再分配结构150的底表面可以与多个子半导体芯片110、120和130中的每个的非有源表面共面。
再分配结构150可以形成在多个子半导体芯片110、120和130的有源表面和子模层140的顶表面上。再分配结构150可以包括再分配导电层152、多个再分配焊盘154和再分配绝缘层156。
再分配导电层152可以将多个子半导体芯片110、120和130中的至少一些与再分配焊盘154连接。例如，再分配导电层152可以将多个子半导体芯片110、120和130中的除了虚设半导体芯片以外的子半导体芯片与再分配焊盘154电连接。
在一些实施例中，再分配导电层152可以包括具有至少一个层的再分配图案层和具有连接到再分配图案层的至少一个层的再分配过孔层。再分配导电层152可以包括例如铜、镍或诸如铍铜的铜合金。
再分配焊盘154可以通过再分配导电层152电连接到多个子半导体芯片110、120和130中的至少一些。再分配焊盘154可以包括例如铜或铜合金，并且可以不被再分配绝缘层156覆盖而是被暴露于子半导体封装件100的外部。再分配焊盘154可以设置在子半导体封装件100的顶表面的与子半导体封装件100的顶表面的一侧相邻的部分上。
多个再分配焊盘154中的至少一些或多个再分配焊盘154中的至少一些的部分在垂直于基体基底层10的主表面的方向上可以不与多个子半导体芯片110、120和130叠置。例如，多个再分配焊盘154中的至少一些或多个再分配焊盘154中的至少一些的部分可以在垂直于基体基底层10的主表面的方向上与子模层140叠置。例如，一些再分配焊盘154可以形成在子模层140上方以与子模层140竖直地叠置，而不与多个子半导体芯片110、120或130中的任何一个竖直地叠置。其它的再分配焊盘154可以形成在子模层140和多个子半导体芯片110、120或130中的一个的组合上方，以与子模层140和多个子半导体芯片110、120或130中的一个竖直地叠置。因此，子半导体封装件100可以是扇出晶圆级封装(FOWLP)型半导体封装件。
再分配绝缘层156可以形成在子半导体芯片110、120和130的有源表面上以及子模层140上，可以覆盖再分配导电层152并且可以暴露再分配焊盘154。再分配绝缘层156例如根据再分配导电层152的结构可以是单层或多层结构。再分配绝缘层156可以包括例如氧化物、氮化物或氮氧化物。在一些实施例中，再分配绝缘层156的形成可以包括用包括环氧树脂或聚酰亚胺的树脂材料(例如，可光成像电介质(PID)材料)涂覆子半导体芯片110、120和130的有源表面以及子模层140，并固化包括环氧树脂或聚酰亚胺的树脂材料，或者可以包括将诸如味之素构建膜(ABF)的构建膜粘附到子半导体芯片110、120和130的有源表面和子模层140。
子半导体封装件100可以粘附到基体基底层10的顶表面，使得多个子半导体芯片110、120和130的有源表面和再分配结构150面向上方，即，背离基体基底层10。子半导体封装件100可以例如通过第一晶粒键合膜410粘附到基体基底层10的顶表面。
主半导体芯片200可以粘附到子半导体封装件100的顶表面。例如，多个主半导体芯片200可以以阶梯形式堆叠。在一个实施例中，主半导体芯片200均可以是非易失性存储器芯片。主半导体芯片200可以是例如NAND闪速存储器、电阻式随机存取存储器(RRAM)、磁阻RAM(MRAM)、相变RAM(PRAM)或铁电RAM(FRAM)。当存在多个主半导体芯片200时，每个主半导体芯片可以是相同的类型和/或尺寸，并且可以是相同的芯片。此外，如各种附图所示(参见下面的各种实施例)，至少一个主半导体芯片至少在一侧上可以悬突于另一个主半导体芯片之上和/或可以悬突于子半导体封装件之上。
虽然图1A和图1B示出了两个主半导体芯片(例如，第一主半导体芯片210和第二主半导体芯片220)以阶梯形式堆叠的情况，但是发明构思不限于此。例如，至少三个主半导体芯片200可以以阶梯形式堆叠。多个主半导体芯片210和220可以以阶梯形式堆叠，以暴露形成在主半导体芯片210和220的有源表面上的多个布线连接焊盘(例如，第一布线连接焊盘212和第二布线连接焊盘222)。
多个主半导体芯片210和220中的最下面的主半导体芯片(例如，第一主半导体芯片210)可以通过第二晶粒键合膜422粘附到子半导体封装件100的顶表面。第一主半导体芯片210可以以阶梯形式粘附到子半导体封装件100的顶表面，以暴露子半导体封装件100的多个再分配焊盘154。第二主半导体芯片220可以通过第三晶粒键合膜424粘附到第一主半导体芯片210的顶表面。
在朝向基体基底层10的主表面的方向上，由子半导体封装件100和第一主半导体芯片210形成的阶梯结构的阶梯上升所横移的方向可以不同于由多个主半导体芯片210和220形成的阶梯结构的阶梯上升所横移的方向。在一些实施例中，在朝向基体基底层10的主表面的方向上，由子半导体封装件100和第一主半导体芯片210形成的阶梯结构的阶梯上升所横移的方向可以垂直于由多个主半导体芯片210和220形成的阶梯结构的阶梯上升所横移的方向。因此，由子半导体封装件100和第一主半导体芯片210形成的阶梯结构的阶梯可以在第一方向上爬升，由多个主半导体芯片210和220形成的阶梯结构的阶梯可以在第二方向上爬升。第一方向可以与第二方向垂直。
在一些实施例中，子半导体封装件100的多个再分配焊盘154不与多个主半导体芯片210和220在垂直于基体基底层10的主表面的方向上(例如，竖直地)叠置。
子半导体封装件100可以通过被构造为将再分配焊盘154与第一顶部连接焊盘14a连接的第一电连接构件310电连接到基体基底层10。第一电连接构件310可以是例如键合布线。
多个主半导体芯片210和220可以通过被构造为将第一布线连接焊盘212和第二布线连接焊盘222与第二顶部连接焊盘14b连接的第二电连接构件320电连接到基体基底层10。第二电连接构件320可以顺序地连接第二主半导体芯片220的第二布线连接焊盘222、第一主半导体芯片210的第一布线连接焊盘212以及PCB 10的第二顶部连接焊盘14b。第二电连接构件320可以是例如键合布线。
主模层500可以形成在基体基底层10上并覆盖子半导体封装件100、主半导体芯片200以及第一电连接构件310和第二电连接构件320。
包括在堆叠式半导体封装件1中的子半导体芯片110、120和130可以被包括子模层140和主模层500的双模层围绕，主半导体芯片200可以被作为单模层的主模层500围绕。
子半导体封装件100可以具有第一厚度t1、第一长度L1和第一宽度W1。多个主半导体芯片210和220中的每个可以具有第二厚度t2、第二长度L2和第二宽度W2。在一些实施例中，第一长度L1可以等于第二长度L2，第一宽度W1可以等于第二宽度W2。因此，子半导体封装件100可以具有与多个主半导体芯片210和220中的每个的面积相同的面积。
在一些实施例中，第一厚度t1可以等于第二厚度t2。因此，子半导体封装件100可以具有与多个主半导体芯片210和220中的每个的体积相同的体积。
在一些实施例中，第一至第三晶粒键合膜410、422和424可具有基本相同的厚度，例如，第三厚度t11。
子半导体封装件100可以通过包括在再分配结构150中的多个再分配焊盘154电连接到基体基底层10，子半导体封装件100可以具有与多个主半导体芯片210和220中的每个的面积相同的面积。因此，子半导体封装件100和多个主半导体芯片210和220可以全部作为具有相同面积的半导体芯片来处理并且可以堆叠。
因此，根据本实施例的堆叠式半导体封装件1及其制造方法可以不涉及复杂的连接路径和复杂的堆叠工艺，以形成包括具有不同面积的多个半导体芯片(例如，多个子半导体芯片110、120和130以及多个主半导体芯片210和220中的每个)的单个堆叠式半导体封装件。应当注意的是，如这里所描述的，半导体芯片是指在其上形成有集成电路的晶粒，并且不应被解释为与封装件相同。封装件包括至少一个半导体芯片、其上设置有所述至少一个半导体芯片的封装件基底以及围绕和/或覆盖封装件基底的至少一部分及所述至少一个半导体芯片的模层或包密剂。
具体地，可以通过使用制造堆叠式半导体封装件的简单方法来形成堆叠式半导体封装件1。所述方法可以包括将子半导体封装件100粘附到基体基底层10的顶表面上，在子半导体封装件100上顺序地堆叠多个主半导体芯片210和220以及形成包括键合布线的第一电连接构件310和第二电连接构件320。
此外，作为具有相对小面积的半导体芯片的多个子半导体芯片110、120和130可以包括在具有以相对简单的排列设置的多个再分配焊盘154的子半导体芯片100中。因此，可以防止当在不同的连接路径中堆叠具有不同面积的半导体芯片时可能发生的堆叠式半导体封装件的厚度的增加。因此，可以形成具有相对小厚度的堆叠式半导体封装件1。
因此，由于堆叠式半导体封装件1易于形成，所以可以简化堆叠式半导体封装件1的制造工艺，可以改善堆叠式半导体封装件1的可靠性，并且可以减小堆叠式半导体封装件1的厚度。
图2A和图2B是根据实施例的堆叠式半导体封装件2的部分的剖视图和平面布局。将省略图2A和图2B的与图1A和图1B中的描述相同的描述。
参照图2A和图2B，堆叠式半导体封装件2可以设置在基体基底层10上。堆叠式半导体封装件2可以包括具有多个子半导体芯片(例如，子半导体芯片110、120和130)的子半导体封装件100a和堆叠在子半导体封装件100a上的多个主半导体芯片(例如，主半导体芯片210和220)。
包括在子半导体封装件100a中的再分配结构150a可以包括再分配导电层152、多个再分配焊盘154a和再分配绝缘层156。多个再分配焊盘154a可以分别设置在子半导体封装件100a的与子半导体封装件100a的顶表面的两个相对侧相邻的部分上。
子半导体封装件100a可以通过第一晶粒键合膜410粘附到基体基底层10的顶表面。随后，可以形成第一电连接构件310以将子半导体封装件100a的再分配焊盘154a与基体基底层10的多个第一顶部连接焊盘14a连接。多个第一顶部连接焊盘14a可以对应于子半导体封装件100a的多个再分配焊盘154a，并且可以分别设置在基体基底层10的顶表面的与子半导体封装件100a的两个侧表面相邻的部分上。
多个主半导体芯片200可以粘附到子半导体封装件100a的顶表面。多个主半导体芯片200可以以阶梯形式堆叠。
多个主半导体芯片210和220中的最下面的主半导体芯片(例如，第一主半导体芯片210)可以通过第二晶粒键合膜422a粘附到子半导体封装件100a的顶表面。第一主半导体芯片210可以粘附到子半导体封装件100a的顶表面，并且在垂直于基体基底层10的主表面的方向上与子半导体封装件100a叠置。因此，第二晶粒键合膜422a可以覆盖子半导体封装件100a的整个顶表面，使得子半导体封装件100a的外边缘与第一主半导体芯片210的外边缘竖直地对齐。因此，第二晶粒键合膜422a可以覆盖再分配焊盘154a和包括键合布线的第一电连接构件310的埋置部分。
第二主半导体芯片220可以通过第三晶粒键合膜424粘附到第一主半导体芯片210的顶表面。第二主半导体芯片220可以堆叠在第一主半导体芯片210上并且与第一主半导体芯片210一起形成阶梯，以暴露形成在第一主半导体芯片210的有源表面上的多个第一布线连接焊盘212。
包括在图1A和图1B所示的堆叠式半导体封装件1中的第二晶粒键合膜422可以具有第三厚度t11，包括在图2A和图2B所示的堆叠式半导体封装件2中的第二晶粒键合膜422a可以具有大于第三厚度t11的第四厚度t12。此外，包括在堆叠式半导体封装件2中的第一晶粒键合膜410和第三晶粒键合膜424可以具有小于第四厚度t12的第三厚度t11。因此，第二晶粒键合膜422a可以比第一晶粒键合膜410和第三晶粒键合膜424厚。
在图1A和图1B所示的堆叠式半导体封装件1中，子半导体封装件100的多个再分配焊盘154可以设置在子半导体封装件100的与子半导体封装件100的顶表面的一侧相邻的部分上，使得多个再分配焊盘154被第二晶粒键合膜422和第一主半导体芯片210暴露。
相比之下，在图2A和图2B所示的堆叠式半导体封装件2中，虽然子半导体封装件100a的多个再分配焊盘154a被第二晶粒键合膜422a和第一主半导体芯片210覆盖，但是第二晶粒键合膜422a可以具有作为相对大的厚度的第四厚度t12。因此，多个再分配焊盘154a可以分别设置在子半导体封装件100a的与子半导体封装件100a的顶表面的两个相对侧相邻的部分上。
尽管堆叠式半导体封装件2具有比图1A和图1B所示的堆叠式半导体封装件1大第四厚度t12与第三厚度t11之差那么多的厚度，但是与包括在堆叠式半导体封装件1中的子半导体封装件100相比，包括在堆叠式半导体封装件2中的子半导体封装件100a可以具有更大数量的再分配焊盘154a。因此，堆叠式半导体封装件2可以以高速处理大量信号。
图3A和图3B是根据实施例的堆叠式半导体封装件3的部分的剖视图和平面布局。将省略图3A和图3B的与图1A至图2B中的描述相同的描述。
参照图3A和图3B，堆叠式半导体封装件3可以包括子半导体封装件100b以及堆叠在子半导体封装件100b上的多个主半导体芯片(例如，第一主半导体芯片210和第二主半导体芯片220)，所述子半导体封装件100b设置在基体基底层10上并具有多个子半导体芯片(例如，子半导体芯片110、120和130)。
在朝向基体基底层10的主表面的方向上，由子半导体封装件100b和第一主半导体芯片210形成的阶梯结构的阶梯上升的方向可以不同于由第一主半导体芯片210和第二主半导体芯片220形成的阶梯结构的阶梯上升的方向。在一些实施例中，在朝向基体基底层10的主表面的方向上，由子半导体封装件100b和第一主半导体芯片210形成的阶梯结构的阶梯上升的方向可以为可与子半导体封装件100b和第一主半导体芯片210的顶表面的边的方向形成锐角的方向。
因此，子半导体封装件100b的顶表面的与邻接在子半导体封装件100b的顶表面的一个角上的两个侧部相邻的部分可以被多个主半导体芯片210和220暴露。
再分配结构150b可以包括再分配导电层152、多个再分配焊盘154、再分配绝缘层156和多个虚设焊盘158。多个虚设焊盘158可以不电连接到包括在子半导体封装件100b中的多个子半导体芯片110、120和130的电路，而是可以在再分配结构150b中被电浮置。由于虚设焊盘158相对于子半导体封装件100b的子半导体芯片110、120和130中的任何一个的内部电路浮置，因此，这些虚设焊盘158可以被称作浮置焊盘。
子半导体封装件100b的顶表面的被多个主半导体芯片210和220暴露的部分中，多个再分配焊盘154可以形成在暴露的部分的与子半导体封装件100b的顶表面的一侧相邻的部分上，多个虚设焊盘158可以形成在暴露的部分的与子半导体封装件100b的顶表面的另一侧相邻的部分上。具体地，多个虚设焊盘158可以在由多个主半导体芯片210和220形成的阶梯结构的阶梯下降的方向上形成在子半导体封装件100b的顶表面的与子半导体封装件100的一侧相邻的部分上。多个再分配焊盘154可以在与由多个主半导体芯片210和220形成的阶梯结构的阶梯下降的方向不同的方向上形成在子半导体封装件100b的顶表面的与子半导体封装件100b的一侧相邻的部分上。
被构造为将多个主半导体芯片210和220与基体基底层10连接的第二电连接构件320a可以穿过虚设焊盘158。第二电连接构件320a可以顺序地连接第二主半导体芯片220的第二布线连接焊盘222、第一主半导体芯片210的第一布线连接焊盘212、子半导体封装件100b的虚设焊盘158以及基体基底层10的第二顶部连接焊盘14b。
如参照图1A所描述的，子半导体封装件100b的厚度可以等于多个主半导体芯片210和220中的每个的厚度。因此，在竖直方向上，第二主半导体芯片220的第二布线连接焊盘222与第一主半导体芯片210的第一布线连接焊盘212之间的距离、第一主半导体芯片210的第一布线连接焊盘212与子半导体封装件100b的虚设焊盘158之间的距离、子半导体封装件100b的虚设焊盘158与基体基底层10的第二顶部连接焊盘14b之间的距离可以彼此基本相等。
因此，包括被构造为连接第二布线连接焊盘222、第一布线连接焊盘212、虚设焊盘158和第二顶部连接焊盘14b的键合布线的第二电连接构件320a的路径可以易于形成和简化。结果，多个主半导体芯片210和220与基体基底层10之间的电连接的可靠性可以改善。
图4A和图4B是根据实施例的堆叠式半导体封装件4的部分的剖视图和平面布局。将省略图4A和图4B的与图1A至图3B中的描述相同的描述。
参照图4A和图4B，堆叠式半导体封装件4可以包括子半导体封装件100c以及堆叠在子半导体封装件100c上的多个主半导体芯片(例如，主半导体芯片210和220)，所述子半导体封装件100c设置在基体基底层10上并具有多个子半导体芯片110、120和130。子半导体封装件100c和多个主半导体芯片210和220中的每个可以具有阶梯在相同的方向上上升的阶梯结构。
包括在子半导体封装件100c中的再分配结构150c可以包括再分配导电层152、多个再分配焊盘154a、再分配层156和虚设焊盘158。多个再分配焊盘154a可以分别设置在基体基底层10的顶表面的与子半导体封装件100c的顶表面的两个相对侧相邻的部分上。多个虚设焊盘158可以设置在子半导体封装件100c的顶表面的与子半导体封装件100c的顶表面的另一侧相邻的部分上。
与图2A和图2B所示的子半导体封装件100a一样，子半导体封装件100c可以通过多个第一电连接构件310电连接到基体基底层10，所述多个第一电连接构件310被构造为将子半导体封装件100c的再分配焊盘154a与基体基底层10的第一顶部连接焊盘14a连接。第二晶粒键合膜422a可以覆盖多个再分配焊盘154a并埋置第一电连接构件310的连接到多个再分配焊盘154a并且包括键合布线的相应的部分。在一些实施例中，虽然未示出，但是多个再分配焊盘154a中的一些可以设置为与虚设焊盘158相邻，并且可以不被第二晶粒键合膜422a覆盖。
如图3A和图3B所示，被构造为将主半导体芯片200与基体基底层10电连接的第二电连接构件320a可以穿过子半导体封装件100c的虚设焊盘158。第二电连接构件320a可以顺序地连接第二主半导体芯片220的第二布线连接焊盘222、第一主半导体芯片210的第一布线连接焊盘212、子半导体封装件100c的虚设焊盘158以及基体基底层10的第二顶部连接焊盘14b。
图5A和图5B是根据实施例的堆叠式半导体封装件5的部分的剖视图和平面布局。将省略图5A和图5B的与图1A至图4B中的描述相同的描述。
参照图5A和图5B，堆叠式半导体封装件5可以包括子半导体封装件100d以及堆叠在子半导体封装件100d上的多个主半导体芯片(例如，主半导体芯片210和220)，所述子半导体封装件100d设置在基体基底层10a上并具有多个子半导体芯片(例如，子半导体芯片110、120和130)。子半导体封装件100d和多个主半导体芯片210和220可以具有阶梯在相同方向上上升的阶梯结构。
基体基底层10a的多个第二顶部连接焊盘14b可以设置为与基体基底层10a的顶表面的一侧相邻。多个第一顶部连接焊盘14a可以在基体基底层10a的顶表面上设置在多个第二顶部连接焊盘14b与子半导体封装件100d的一个侧表面之间。
子半导体封装件100d的再分配结构150d可以包括再分配导电层152、多个再分配焊盘154b和再分配绝缘层156。多个主半导体芯片210和220可以以阶梯形式堆叠在子半导体封装件100d上，以暴露多个再分配焊盘154b。
在堆叠式半导体封装件5中，子半导体封装件100d的多个再分配焊盘154b可以设置在子半导体封装件100d的顶表面的一部分上，多个主半导体芯片210和220的多个布线连接焊盘212和222可以设置在多个主半导体芯片210和220的相应的部分上。在这种情况下，子半导体封装件100d的顶表面的所述一部分与多个主半导体芯片210和220的设置有多个再分配焊盘154b和多个布线连接焊盘212和222的相应的部分可以与基体基底层10a的同一侧相邻。
子半导体封装件100d可以通过被构造为将再分配焊盘154b与第一顶部连接焊盘14a连接的第一电连接构件310而电连接到基体基底层10a。多个主半导体芯片210和220可以通过被构造为将布线连接焊盘212和222与第二顶部连接焊盘14b连接的第二电连接构件320而电连接到PCB 10a。第二电连接构件320可以顺序地连接第二主半导体芯片220的第二布线连接焊盘222、第一主半导体芯片210的第一布线连接焊盘212和基体基底层10a的第二顶部连接焊盘14b。
在堆叠式半导体封装件5中，第一电连接构件310和第二电连接构件320可以形成为与基体基底层10a的同一侧相邻。因此，可以使形成堆叠式半导体封装件5中的第一电连接构件310和第二电连接构件320所需的面积最小化。结果，可以减小堆叠式半导体封装件5的面积。
图6A和图6B是根据实施例的堆叠式半导体封装件6的部分的剖视图和平面布局。将省略图6A和图6B的与图1A至图5B中的描述相同的描述。
参照图6A和图6B，堆叠式半导体封装件6可以包括子半导体封装件100e以及堆叠在子半导体封装件100e上的多个主半导体芯片(例如，主半导体芯片210和220)，所述子半导体封装件100e可设置在基体基底层10b上并具有多个子半导体芯片(例如，子半导体芯片110、120和130)。
子半导体封装件100e可以粘附到基体基底层10b的顶表面，使得多个子半导体芯片110、120和130的有源表面和再分配结构150e面向下，即，面向基体基底层10b。再分配结构150e可以包括再分配导电层152、多个再分配焊盘154e和再分配绝缘层156。子半导体封装件100e可以通过设置在多个再分配焊盘154e与多个第一顶部连接焊盘14a之间的多个连接凸块350电连接到并且粘附到基体基底层10b。例如，子半导体封装件100e可以通过使用倒装芯片技术粘附到基体基底层10b的顶表面。
一个或更多个主半导体芯片200可以粘附到子半导体封装件100e的顶表面。多个主半导体芯片200可以以阶梯形式堆叠。
多个主半导体芯片210和220中的下主半导体芯片(例如，第一主半导体芯片210)可以通过第二晶粒键合膜422粘附到子半导体封装件100e的顶表面。第一主半导体芯片210可以粘附到子半导体封装件100e的顶表面，并且在垂直于基体基底层10b的主表面的方向上与子半导体封装件100e叠置。因此，第二晶粒键合膜422可以覆盖子半导体封装件100e的整个顶表面。
子半导体封装件100e可以通过使用倒装芯片技术而作为粘附到基体基底层10b的顶表面的半导体芯片来处理。因此，由于多个再分配焊盘154e随意地设置在子半导体封装件100e的底表面上，所以可以使对多个再分配焊盘154e的数量的限制最小化。因此，堆叠式半导体封装件6可以以高速处理大量信号。
此外，由于子半导体封装件100e具有与多个主半导体芯片210和220中的每个的面积相同的面积，所以可以容易地将多个主半导体芯片210和220堆叠在子半导体封装件100e上。此外，设置在下侧的子半导体封装件100e可以稳定地支撑堆叠在上侧的主半导体芯片200。此外，由于子半导体封装件100e稳定地支撑堆叠在子半导体封装件100e上的主半导体芯片200，所以可以可靠地形成被构造为将多个主半导体芯片210和220与基体基底层10b电连接的电连接构件320。
图7A和图7B是根据实施例的堆叠式半导体封装件7的部分的剖视图和平面布局。将省略图7A和图7B的与图1A至图6B中的描述相同的描述。
参照图7A和图7B，堆叠式半导体封装件7可以包括子半导体封装件100f以及堆叠在子半导体封装件100f上的多个主半导体芯片210和220，所述子半导体封装件100f可设置在基体基底层10b上并具有多个子半导体芯片110、120和130。
子半导体封装件100f可以包括第一再分配结构150e和第二再分配结构160，第一再分配结构150e可以形成在多个子半导体芯片110、120和130的有源表面上及子模层140上，第二再分配结构160可以形成在多个子半导体芯片110、120和130的非有源表面上以及子模层140上。
由于子半导体封装件100f的第一再分配结构150e具有与参照图6A和图6B描述的子半导体封装件100e的再分配结构150e相同的结构，所以将省略其详细描述。
子半导体封装件100f的第二再分配结构160可以包括多个虚设再分配焊盘164和虚设再分配绝缘层166。虽然第二再分配结构160通过使用与形成第一再分配结构150e的方法相似的方法形成，但是第二再分配结构160不包括连接到包括在子半导体封装件100f中的多个子半导体芯片110、120和130的额外的再分配图案。
虚设再分配绝缘层166可以形成在多个子半导体芯片110、120和130的非有源表面上以及子模层140上，并且覆盖多个子半导体芯片110、120、130的非有源表面和子模层140。虚设再分配绝缘层166可以包括例如氧化物、氮化物或氮氧化物。在一些实施例中，虚设再分配绝缘层166的形成可以包括用包括环氧树脂或聚酰亚胺的树脂材料(例如PID)涂覆子半导体芯片110、120和130的非有源表面及子模层140并固化包括环氧树脂或聚酰亚胺的树脂材料，或者包括将诸如ABF的构建膜粘附到子半导体芯片110、120和130的非有源表面和子模层140。
多个虚设再分配焊盘164不与包括在子半导体封装件100f中的多个子半导体芯片110、120和130的内部电路电连接，而是在第二再分配结构160中被电浮置。
关于子半导体封装件100f的顶表面的被多个主半导体芯片210和220暴露的部分，多个再分配焊盘164可以形成在暴露的部分的与子半导体封装件100f的顶表面的一侧相邻的部分上。具体地，多个虚设再分配焊盘164可以形成在子半导体封装件100f的顶表面的与子半导体封装件100f由多个主半导体芯片210和220形成的阶梯结构的阶梯下降所处的一侧相邻的部分上。
被构造为将多个主半导体芯片210和220与基体基底层10b连接的第二电连接构件320a可以穿过虚设再分配焊盘164。第二电连接构件320a可以顺序地连接第二主半导体芯片220的第二布线连接焊盘222、第一主半导体芯片210的第一布线连接焊盘212、子半导体封装件100e的虚设再分配焊盘164和基体基底层10b的第二顶部连接焊盘14b。
图8A至图8F是根据实施例的制造子半导体封装件的方法的顺序工艺操作的剖视图。具体地，图8A至图8F是制造包括在图1A和图1B所示的堆叠式半导体封装件1中的子半导体封装件100的方法的顺序工艺操作的剖视图。
参照图8A，可以在第一支撑基底50上设置多个子半导体芯片(例如，子半导体芯片110、120和130)。可以在第一支撑基底50上设置多个子半导体芯片110、120和130，使得子半导体芯片110、120和130的有源表面面朝上。可以使子半导体芯片110、120和130彼此分开地设置在第一支撑基底50上(例如，在水平方向上，以在它们之间具有一定的空间)。在一些实施例中，第一支撑基底50可以是半导体晶圆。
可以通过第一分离膜60将多个子半导体芯片110、120和130粘附到第一支撑基底50的顶表面。第一分离膜60可以包括单层或包含分别粘附到骨架层的两个表面的分离层的多层结构。骨架层可以包括例如热塑性聚合物。分离层可以包括例如丙烯酸和硅酮的共聚物。
参照图8B，可以在第一支撑基底50上形成子模层140并且子模层140可以填充多个子半导体芯片110、120和130之间的相应的空间。子模层140可以不覆盖多个子半导体芯片110、120和130中的每个的顶表面，而是仅围绕多个子半导体芯片110、120和130中的每个的侧表面。子模层的顶表面可以与子半导体芯片110、120和130的顶表面共面。
参照图8C，可以在多个子半导体芯片110、120和130的有源表面上以及子模层140上形成再分配结构150。
再分配结构150可以包括再分配导电层152、多个再分配焊盘154和再分配绝缘层156。
再分配导电层152可以包括具有至少一个层的再分配图案层和具有被构造为将多个子半导体芯片110、120和130的至少部分连接到再分配图案层和再分配焊盘154的至少一个层的再分配过孔层。再分配焊盘154可以通过再分配导电层152电连接到多个子半导体芯片110、120和130中的至少一些。可以在多个子半导体芯片110、120和130的有源表面上以及在子模层140上形成再分配绝缘层156，并且再分配绝缘层156可以覆盖再分配导电层152并暴露多个再分配焊盘154。再分配绝缘层156可以根据再分配导电层152的结构包括单层或多层结构。
可以通过使用形成再分配结构的典型方法来形成再分配结构150，所述方法已在半导体制造工艺中使用或可在半导体制造工艺中使用。因此，将省略形成再分配结构150的详细工艺。
在形成再分配结构150之后，可以去除第一分离膜60和第一支撑基底50。
参照图8D，可以将包括图8C所示的包括再分配结构150的所得结构粘附到第二支撑基底52的顶表面并使第二分离膜62在它们之间，使得再分配结构150可面向第二分离膜62。第二支撑膜52和第二分离膜62可以分别类似于第一支撑膜50和第一分离膜60，因此将省略其详细描述。
参照图8E，可以可选地从多个子半导体芯片110、120和130的非有源表面去除多个子半导体芯片110、120、130和子模层140的部分。因此，可以减小包括子半导体芯片110、120和130及子模层140的结构的厚度。
参照图8F，可以将包括多个子半导体芯片110、120和130及子模层140的结构分成多个子半导体封装件100。在这种情况下，再分配结构150可以用作封装件基底，并且可以被描述为子封装件基底。
此外，可以通过使用参照图8A至图8F描述的方法来制造包括在图2A、图2B、图5A和图5B所示的堆叠式半导体封装件2和5中的子半导体封装件100a和100d。
图9是根据实施例的制造子半导体封装件的方法的剖视图。具体地，图9是包括在图3A和图3B所示的堆叠式半导体封装件3中的子半导体封装件100d的制造方法的剖视图。
参照图9，如参照图8A和图8B所描述的，在将多个子半导体芯片110、120和130设置在支撑基底50上之后，可以形成子模层140以填充多个子半导体芯片110、120和130之间的相应的空间。
随后，如参照图8C所描述的，可以在多个子半导体芯片110、120和130的有源表面上及子模层140上形成再分配结构150b。再分配结构150b可以包括再分配导电层152、多个再分配焊盘154、再分配绝缘层156和多个虚设焊盘158。
在一些实施例中，可以在形成多个再分配焊盘154期间形成多个虚设焊盘158。多个虚设焊盘158可以不电连接到多个子半导体芯片110、120和130的内部电路，而是可以在再分配结构150b中被电浮置。
此后，可以参照图8D至图8F的描述形成子半导体封装件100b。
另外，可以参照根据图9所描述的方法制造包括在图4A和图4B所示的堆叠式半导体封装件4中的子半导体封装件100c。
图10A至图10C是根据实施例的制造子半导体封装件的方法的顺序工艺操作的剖视图。具体地，图10A至图10C是图6A和图6B所示的堆叠式半导体封装件6中包括的子半导体封装件100e和连接凸块350的制造方法的顺序工艺操作的剖视图。
参照图10A，如图8A至图8C所描述的，在将多个子半导体芯片110、120和130设置在支撑基底50上之后，可以形成子模层140以填充多个子半导体芯片110、120和130之间的相应的空间。可以在多个子半导体芯片110、120和130的有源表面上及子模层140上形成再分配结构150e。
此后，可以在再分配焊盘154e上形成连接凸块350。
在形成连接凸块350之后，可以去除第一分离膜60和第一支撑基底50。
参照图10B，可以将包括图10A所示的连接凸块350的所得结构粘附到第二支撑结构52的顶表面并使第二分离膜62a在它们之间，使得再分配结构150e可以面向第二分离膜62a。
参照图10C，可以可选地从多个子半导体芯片110、120和130的非有源表面去除多个子半导体芯片110、120、130和子模层140的部分。因此，可以减小包括多个子半导体芯片110、120和130及子模层140的结构的厚度。
随后，可以以与参照图8F所描述的方式相同的方式形成子半导体封装件100e。
图11是根据实施例的制造子半导体封装件的方法的剖视图。具体地，图11是制造包括在图7A和图7B所示的堆叠式半导体封装件7中的子半导体封装件100f的方法的剖视图。
参照图11，在执行参照图10A至图10C所描述的方法之后，可以在多个子半导体芯片110、120和130的非有源表面上及子模层140上形成第二再分配结构160。第二再分配结构160可以包括多个虚设再分配焊盘164和虚设再分配绝缘层166。多个虚设再分配焊盘164可以不电连接到多个子半导体芯片110、120和130的内部电路，而是可以被电浮置在第二再分配结构160中。
随后，可以以与参考图8F所描述的方式相同的方式形成子半导体封装件100f。
图12是根据实施例的系统1100的框图。
参照图12，系统1100可以包括可通过公共总线1160彼此通信的处理器1130(例如，中央处理单元(CPU))、随机存取存储器(RAM)1140、用户接口1150和调制解调器1120。
系统1100的元件可以通过公共总线1160向存储装置1110发送信号以及从存储装置1110接收信号。存储装置1110可以包括闪速存储器1111和存储器控制器1112。闪速存储器1111可以存储数据并且具有非易失性特性，从而即使电源中断，存储在闪速存储器1111中的数据也仍然可以被保留。存储装置1110和RAM 1140可以包括参照图1A至图11描述的堆叠式半导体封装件1、2、3、4、5、6和7中的任何一种。
因此，因为存储装置1110和RAM 1140可以通过使用单个堆叠式半导体封装件实施在一起，所以根据本实施例的系统1100可以被缩小尺寸并具有高容量。此外，可以简化制造堆叠式半导体封装件以形成存储装置1110和RAM1140两者的工艺。此外，堆叠式半导体封装件的可靠性可以改善，并且可以减小堆叠式半导体封装件的厚度。因此，根据本实施例的系统1100可以被缩小尺寸并且在可靠性方面得到改善。
虽然已经参照本公开的实施例具体示出和描述了发明构思，但是应当理解的是，在不脱离权利要求的精神和范围的情况下，可以在形式和细节上做出各种改变。

Claims (20)

1.一种堆叠式半导体封装件，所述堆叠式半导体封装件包括：
基体基底层；
子半导体封装件，设置在所述基体基底层的顶表面上，所述子半导体封装件包括：
多个子半导体芯片，彼此水平地分隔开，
子模层，填充所述多个子半导体芯片之间的空间，以围绕所述多个子半导体芯片的侧表面，以及
再分配结构，设置在所述多个子半导体芯片的有源表面上以及所述子模层上，所述再分配结构包括电连接到所述基体基底层的再分配焊盘以及被构造为将所述多个子半导体芯片中的至少一些与所述再分配焊盘连接的再分配导电层；以及
多个主半导体芯片，沿竖直方向以阶梯形式顺序地堆叠在所述子半导体封装件上并且具有布线连接焊盘，
其中，在所述竖直方向上，由所述子半导体封装件和所述多个主半导体芯片中的最下面的主半导体芯片形成的第一阶梯结构的阶梯上升所横移的第一方向，不同于由所述多个主半导体芯片形成的第二阶梯结构的阶梯上升所横移的第二方向，
所述布线连接焊盘设置在所述多个主半导体芯片中的每个的顶表面的沿所述第二方向的一侧处，并且在所述竖直方向上彼此不叠置，
所述再分配焊盘设置在所述子半导体封装件的顶表面的沿与所述第二方向垂直的第三方向的一侧处，并且在所述竖直方向上不与所述多个主半导体芯片叠置，并且
所述多个主半导体芯片通过第一电连接构件沿所述第二方向电连接到所述基体基底层。
2.根据权利要求1所述的堆叠式半导体封装件，其中，从平面图看所述子半导体封装件具有与所述多个主半导体芯片中的每个主半导体芯片的面积相同的面积。
3.根据权利要求2所述的堆叠式半导体封装件，其中，所述子半导体封装件粘附到所述基体基底层的所述顶表面，使得所述多个子半导体芯片的有源表面背离所述基体基底层，
所述子半导体封装件通过第二电连接构件沿所述第三方向电连接到所述基体基底层其中，所述第一电连接构件和所述第二电连接构件是键合布线。
4.根据权利要求1所述的堆叠式半导体封装件，其中，所述第一方向与所述第三方向相同。
5.根据权利要求1所述的堆叠式半导体封装件，其中，所述第一方向与所述第三方向形成锐角。
6.根据权利要求5所述的堆叠式半导体封装件，其中，所述再分配结构还包括：
虚设焊盘，设置在所述子半导体封装件的所述顶表面的沿所述第二方向的一侧处。
7.根据权利要求1所述的堆叠式半导体封装件，所述堆叠式半导体封装件还包括：
晶粒键合膜，位于所述子半导体封装件与所述最下面的主半导体芯片之间。
8.根据权利要求6所述的堆叠式半导体封装件，其中，所述第一电连接构件顺序地连接所述布线连接焊盘、所述虚设焊盘和所述基体基底层。
9.根据权利要求1所述的堆叠式半导体封装件，其中，所述子半导体封装件在所述竖直方向上具有与至少所述最下面的主半导体芯片的厚度相同的厚度。
10.一种堆叠式半导体封装件，所述堆叠式半导体封装件包括：
子半导体封装件，所述子半导体封装件包括：多个子半导体芯片，彼此水平地分隔开；子模层，填充所述多个子半导体芯片之间的空间；再分配结构，包括再分配焊盘和再分配导电层，所述再分配导电层被构造为将所述多个子半导体芯片中的至少一些与所述再分配焊盘连接，所述再分配结构位于所述多个子半导体芯片的有源表面上以及所述子模层上；以及
多个主半导体芯片，沿竖直方向以阶梯形式顺序地堆叠在所述子半导体封装件上并且具有布线连接焊盘，
其中，在所述竖直方向上，由所述子半导体封装件和所述多个主半导体芯片中的最下面的主半导体芯片形成的第一阶梯结构的阶梯上升所横移的第一方向，不同于由所述多个主半导体芯片形成的第二阶梯结构的阶梯上升所横移的第二方向，
所述布线连接焊盘设置在所述多个主半导体芯片中的每个的顶表面的沿所述第二方向的一侧处，并且在所述竖直方向上彼此不叠置，
所述再分配焊盘设置在所述子半导体封装件的顶表面的沿与所述第二方向垂直的第三方向的一侧处，并且在所述竖直方向上不与所述多个主半导体芯片叠置，并且
所述多个主半导体芯片中的每个具有与所述子半导体封装件的面积相同的面积。
11.根据权利要求10所述的堆叠式半导体封装件，其中，从俯视图观察时，所述多个主半导体芯片中的每个主半导体芯片具有比所述多个子半导体芯片中的每个子半导体芯片的面积大的面积。
12.根据权利要求10所述的堆叠式半导体封装件，其中，所述子模层的面向所述再分配结构的表面与所述多个子半导体芯片的所述有源表面共面。
13.根据权利要求10所述的堆叠式半导体封装件，所述堆叠式半导体封装件还包括基体基底层，所述基体基底层具有使所述子半导体封装件粘附到的顶表面，其中，电连接到所述子半导体封装件的第一顶部连接焊盘和电连接到所述多个主半导体芯片的第二顶部连接焊盘位于所述基体基底层的所述顶表面上，
其中，所述第一顶部连接焊盘和所述第二顶部连接焊盘与所述基体基底层的所述顶表面的不同侧相邻。
14.一种堆叠式半导体封装件，所述堆叠式半导体封装件包括：
基体封装件基底；
子半导体封装件，设置在所述基体封装件基底上，所述子半导体封装件包括：
多个第一半导体芯片，彼此水平地分隔开，当从平面图观察时，所述多个第一半导体芯片中的至少两个具有彼此不同的面积；
子模层，填充所述第一半导体芯片之间的空间；以及
子封装件基底，设置在所述多个第一半导体芯片和所述子模层上并且具有再分配焊盘；
多个第二半导体芯片，沿竖直方向以阶梯形式顺序地设置在所述子半导体封装件上并且具有布线连接焊盘，当从平面图观察时，所述第二半导体芯片具有比所述多个第一半导体芯片中的每个第一半导体芯片的面积大的面积；以及
模层，覆盖所述子半导体封装件和所述第二半导体芯片，
其中，在所述竖直方向上，由所述子半导体封装件和所述多个第二半导体芯片中的最下面的第二半导体芯片形成的第一阶梯结构的阶梯上升所横移的第一方向，不同于由所述多个第二半导体芯片形成的第二阶梯结构的阶梯上升所横移的第二方向，
所述布线连接焊盘设置在所述多个第二半导体芯片中的每个的顶表面的沿所述第二方向的一侧处，并且在所述竖直方向上彼此不叠置，
所述再分配焊盘设置在所述子半导体封装件的顶表面的沿与所述第二方向垂直的第三方向的一侧处，并且在所述竖直方向上不与所述多个第二半导体芯片叠置，并且
当从平面图观察时，所述子半导体封装件具有与所述第二半导体芯片相同的面积。
15.根据权利要求14所述的堆叠式半导体封装件，其中，所述子封装件基底是包括所述再分配焊盘和再分配导电层的再分配结构，
所述再分配导电层被构造为将所述多个第一半导体芯片中的至少一些与所述再分配焊盘连接。
16.根据权利要求15所述的堆叠式半导体封装件，其中，所述基体封装件基底包括用于连接到所述再分配焊盘的顶部连接焊盘。
17.根据权利要求16所述的堆叠式半导体封装件，其中，所述基体封装件基底包括用于连接到所述布线连接焊盘的附加顶部连接焊盘。
18.根据权利要求14所述的堆叠半导体封装件，其中，所述子半导体封装件设置在所述基体封装件基底与所述第二半导体芯片之间。
19.根据权利要求14所述的堆叠式半导体封装件，其中，所述第一方向与所述第三方向相同。
20.根据权利要求14所述的堆叠式半导体封装件，其中，所述第一方向与所述第三方向形成锐角。
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