JP5078808B2 - 半導体装置の製造方法 - Google Patents
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- JP5078808B2 JP5078808B2 JP2008225828A JP2008225828A JP5078808B2 JP 5078808 B2 JP5078808 B2 JP 5078808B2 JP 2008225828 A JP2008225828 A JP 2008225828A JP 2008225828 A JP2008225828 A JP 2008225828A JP 5078808 B2 JP5078808 B2 JP 5078808B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
11 搭載基板
12 貫通電極
13−1、13−2 半導体チップ
14 バンプ
15 支持基板
16 接着剤
17 樹脂
18 半導体チップ
19 ワイヤ
20 半導体装置
21 シリコン基板
22 半導体チップ
23 マイクロバンプ
24 樹脂
25 プリント基板
26 ワイヤ
Claims (3)
- 複数の半導体チップを含む半導体装置の製造方法であって、
搭載基板及び支持基板を準備する基板準備ステップと、
前記基板準備ステップの後に前記搭載基板の下面に少なくとも1つの半導体チップを搭載する下面搭載ステップと、
前記下面搭載ステップの後に前記搭載基板の下面に搭載された前記半導体チップを接着剤で前記支持基板の片面に固定するチップ固定ステップと、
前記チップ固定ステップの後に前記搭載基板の下面に搭載された前記半導体チップを樹脂で封止する樹脂封止ステップと、
前記樹脂封止ステップの後に前記搭載基板の上面に少なくとも1つの半導体チップを搭載する上面搭載ステップと、
を含むことを特徴とする半導体装置の製造方法。 - 前記搭載基板の上面から下面にかけて貫通電極を形成する電極形成ステップを更に含み、
前記下面搭載ステップ及び前記上面搭載ステップは、前記半導体チップの表面の電極パッドと前記貫通電極とが電気的に接続されるように前記半導体チップを前記搭載基板に搭載することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記基板準備ステップにおける前記搭載基板は同一ウエハ上に形成されている複数の搭載基板のうちの1つであり、
前記下面搭載ステップの後に前記ウエハを個片化して前記搭載基板を得る基板個片化ステップを更に含むことを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008225828A JP5078808B2 (ja) | 2008-09-03 | 2008-09-03 | 半導体装置の製造方法 |
US12/550,754 US20100055834A1 (en) | 2008-09-03 | 2009-08-31 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008225828A JP5078808B2 (ja) | 2008-09-03 | 2008-09-03 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010062292A JP2010062292A (ja) | 2010-03-18 |
JP5078808B2 true JP5078808B2 (ja) | 2012-11-21 |
Family
ID=41726056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008225828A Active JP5078808B2 (ja) | 2008-09-03 | 2008-09-03 | 半導体装置の製造方法 |
Country Status (2)
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US (1) | US20100055834A1 (ja) |
JP (1) | JP5078808B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101817159B1 (ko) | 2011-02-17 | 2018-02-22 | 삼성전자 주식회사 | Tsv를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법 |
KR20130007049A (ko) * | 2011-06-28 | 2013-01-18 | 삼성전자주식회사 | 쓰루 실리콘 비아를 이용한 패키지 온 패키지 |
JP2018037465A (ja) * | 2016-08-29 | 2018-03-08 | ウシオ電機株式会社 | 半導体パッケージおよびその製造方法 |
KR102605617B1 (ko) * | 2016-11-10 | 2023-11-23 | 삼성전자주식회사 | 적층 반도체 패키지 |
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JP2001203318A (ja) * | 1999-12-17 | 2001-07-27 | Texas Instr Inc <Ti> | 複数のフリップチップを備えた半導体アセンブリ |
JP4570809B2 (ja) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
US6507115B2 (en) * | 2000-12-14 | 2003-01-14 | International Business Machines Corporation | Multi-chip integrated circuit module |
JP4586273B2 (ja) * | 2001-01-15 | 2010-11-24 | ソニー株式会社 | 半導体装置構造 |
JP2003023135A (ja) * | 2001-07-06 | 2003-01-24 | Sharp Corp | 半導体集積回路装置 |
SG104293A1 (en) * | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
TWI268581B (en) * | 2002-01-25 | 2006-12-11 | Advanced Semiconductor Eng | Stack type flip-chip package including a substrate board, a first chip, a second chip, multiple conductive wire, an underfill, and a packaging material |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
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TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
DE10360708B4 (de) * | 2003-12-19 | 2008-04-10 | Infineon Technologies Ag | Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben |
JP4587676B2 (ja) * | 2004-01-29 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | チップ積層構成の3次元半導体装置 |
JP4580671B2 (ja) * | 2004-03-29 | 2010-11-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2006210566A (ja) * | 2005-01-27 | 2006-08-10 | Akita Denshi Systems:Kk | 半導体装置 |
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JP3895756B1 (ja) * | 2005-11-30 | 2007-03-22 | 株式会社システム・ファブリケーション・テクノロジーズ | 半導体装置 |
US7279795B2 (en) * | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
DE102006016345A1 (de) * | 2006-04-05 | 2007-10-18 | Infineon Technologies Ag | Halbleitermodul mit diskreten Bauelementen und Verfahren zur Herstellung desselben |
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-
2008
- 2008-09-03 JP JP2008225828A patent/JP5078808B2/ja active Active
-
2009
- 2009-08-31 US US12/550,754 patent/US20100055834A1/en not_active Abandoned
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Publication number | Publication date |
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JP2010062292A (ja) | 2010-03-18 |
US20100055834A1 (en) | 2010-03-04 |
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