CN105428334A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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Publication number
CN105428334A
CN105428334A CN201510582282.5A CN201510582282A CN105428334A CN 105428334 A CN105428334 A CN 105428334A CN 201510582282 A CN201510582282 A CN 201510582282A CN 105428334 A CN105428334 A CN 105428334A
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Prior art keywords
naked chip
random access
access memory
dynamic random
chip
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Granted
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CN201510582282.5A
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CN105428334B (zh
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林子闳
杨明宗
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明公开了一种半导体封装结构。其包括第一半导体封装和堆叠于第一半导体封装上的第二半导体封装；第一半导体封装包括第一半导体祼芯片，具有第一连接垫；第一通孔，设置于第一半导体祼芯片之上且耦接至第一连接垫；以及第一动态随机存取存储器祼芯片，安装于第一半导体祼芯片之上且耦接至第一通孔；第二半导体封装包括：主体，具有祼芯片接触面和位于祼芯片接触面对面的凸块接触面；以及第二动态随机存取存储器祼芯片，安装于祼芯片接触面之上且由接合线耦接至主体；第一动态随机存取存储器祼芯片的I/O引脚的数量不同于第二动态随机存取存储器祼芯片的I/O引脚的数量。本发明实施例，具有低成本、高带宽、低功耗和快速转变等优点。

Description

半导体封装结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体封装结构(packageassembly)，例如混合的DRAM(DynamicRandomAccessMemory，动态随机存取存储器)封装结构。
背景技术
POP(Package-on-Package，叠层封装)结构是一种用于垂直地组合分开的SOC(System-On-Chip，片上系统)和存储器封装的集成电路封装方法。使用标准界面(standardinterface)来安装(如堆叠)两个或更多的封装于彼此的顶上，从而在该两个或更多的封装之间路由信号。POP封装结构允许设备具有更高的元件密度，该设备例如为移动电话、个人数字助理(PersonalDigitalAssistant，PDA)和数码相机。
对于具有增强集成水平和改进了性能、带宽、延迟、功率、重量和形状因子(formfactor)的存储器应用，信号垫与接地垫的比率在改善耦合效应中变得重要。
如此，期望创新的半导体封装结构。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装结构，具有更好的性能。
本发明实施例提供了一种半导体封装结构，包括：第一半导体封装和堆叠于所述第一半导体封装上的第二半导体封装；
所述第一半导体封装，包括：
第一半导体祼芯片，所述第一半导体祼芯片上具有第一连接垫；
第一通孔，设置于所述第一半导体祼芯片之上，并且耦接至所述第一连接垫；以及
第一动态随机存取存储器祼芯片，安装于所述第一半导体祼芯片之上，并且耦接至所述第一通孔；
所述第二半导体封装，包括：
主体，具有祼芯片接触面和位于所述祼芯片接触面对面的凸块接触面；以及
第二动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量。
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量大于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
其中，所述第一动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述第一动态随机存取存储器祼芯片。
其中，所述第一半导体封装进一步包括：
重分布层结构，所述重分布层结构上具有第一导电迹线；
其中，所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片耦接于所述第一导电迹线。
其中，所述第一动态随机存取存储器祼芯片位于所述第一半导体祼芯片和所述重分布层结构之间。
其中，所述第一半导体封装结构进一步包括：
模塑料，围绕所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片，并且与所述重分布层结构、所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片接触；以及
第一导电结构，设置在所述重分布层结构中远离所述第一半导体祼芯片的表面之上，并且所述第一导电结构耦接至所述第一导电迹线。
其中，所述第二半导体封装通过第二通孔耦接至所述第一导电迹线，所述第二通孔穿过位于所述第二半导体封装和所述重分布层结构之间的所述模塑料。
其中，所述第二通孔围绕所述第一半导体祼芯片。
其中，所述第一半导体祼芯片通过第三通孔耦接至所述第一导电迹线，所述第三通孔穿过所述第一半导体祼芯片和所述重分布层结构之间的所述模塑料。
其中，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
其中，进一步包括：基底，其中所述第一和第二半导体封装通过导电结构安装于所述基底之上。
本发明提供了一种半导体封装结构，包括：第一半导体封装和堆叠于所述第一半导体封装上的第二半导体封装；
所述第一半导体封装，包括：
半导体祼芯片，所述半导体祼芯片之上具有连接垫；以及
第一通孔，设置在所述半导体祼芯片之上，并且耦接至所述连接垫；
所述第二半导体封装，包括：
主体，具有祼芯片接触面和位于所述祼芯片接触面对面的凸块接触面；以及
第一动态随机存取存储器祼芯片，安装于所述凸块接触面之上，并且耦接至所述主体；以及
第二动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量。
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量大于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
其中，所述第一动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述第一动态随机存取存储器祼芯片。
其中，所述第一半导体封装进一步包括：
第一重分布层结构，所述第一重分布层结构上具有第一导电迹线；其中，所述半导体祼芯片耦接于所述第一导电迹线。
其中，所述第一半导体封装进一步包括：
第一模塑料，围绕所述半导体祼芯片，并且与所述第一重分布层结构和所述半导体祼芯片接触；以及
第一导电结构，设置在所述第一重分布层结构中远离所述半导体祼芯片的表面上，其中所述第一导电结构耦接至所述第一导电迹线。
其中，所述第二半导体封装进一步包括：
第二模塑料，设置在所述主体的凸块接触面之上，并且围绕所述第一动态随机存取存储器祼芯片；以及
第二重分布层结构，位于所述第二模塑料之上，并且所述第二重分布层结构上具有第二导电迹线；
其中，所述第一动态随机存取存储器祼芯片位于所述主体和所述第二重分布层结构之间，并且耦接至所述第二导电迹线。
其中，所述第二半导体封装通过第二通孔耦接至所述第一导电迹线，所述第二通孔穿过位于所述第二半导体封装和所述第一重分布层结构之间的所述第一模塑料。
其中，所述第二通孔围绕所述半导体祼芯片。
其中，所述第二动态随机存取存储器祼芯片通过第三通孔耦接至所述第二重分布层结构，所述第三通孔穿过位于所述主体和所述第二重分布层结构之间的所述第二模塑料。
其中，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
其中，所述第二半导体封装通过第二导电结构安装于所述第一半导体封装之上，所述第二导电结构位于所述第二重分布层结构之上并且耦接所述第二重分布层结构。
其中，进一步包括：基底，所述第一和第二半导体封装通过第一导电结构安装于所述基底之上。
本发明提供了一种半导体封装结构，包括：片上系统封装和堆叠于所述片上系统封装上的动态随机存取存储器封装；
所述片上系统封装包括：
逻辑祼芯片，所述逻辑祼芯片上具有第一连接垫；
第一重分布层结构，耦接至所述逻辑祼芯片；以及
模塑料，围绕所述逻辑祼芯片，并且与所述第一重分布层结构和所述逻辑祼芯片接触；
所述动态随机存取存储器封装包括：
主体，具有祼芯片接触面和在所述祼芯片接触面对面的凸块接触面；以及
动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述片上系统封装和所述动态随机存取存储器封装之一进一步包括：嵌于其中的额外的动态随机存取存储器祼芯片；
其中，所述额外的动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述额外的动态随机存取存储器祼芯片。
其中，所述动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述额外的动态随机存取存储器祼芯片的输入/输出引脚的数量；
或者，所述额外的动态随机存取存储器祼芯片的输入/输出引脚数量大于所述动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
其中，所述片上系统封装进一步包括：
第一通孔，位于所述逻辑祼芯片之上，并且耦接至所述第一连接垫。
其中，所述动态随机存取存储器祼芯片封装通过第二通孔耦接至所述片上系统封装中的第一重分布层结构；
所述第二通孔穿过位于所述动态随机存取存储器封装和所述第一重分布层结构之间的所述模塑料。
其中，所述第二通孔围绕所述逻辑祼芯片。
其中，所述额外的动态随机存取存储器祼芯片嵌入于所述片上系统封装中，并且耦接所述第一通孔和所述第一重分布层结构。
其中，所述模塑料与所述额外的动态随机存取存储器祼芯片接触。
其中，所述逻辑祼芯片通过第三通孔耦接至所述重分布层结构，所述第三通孔穿过所述逻辑祼芯片和所述第一重分布层结构之间的所述模塑料。
其中，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
其中，所述动态随机存取存储器封装还包括：
第二重分布层结构，位于所述凸块接触面之上。
其中，所述额外的动态随机存取存储器祼芯片设置在所述主体和所述第二重分布层之间。
其中，进一步包括：基底，所述第一和第二半导体封装通过导电结构安装在所述基底之上。
本发明实施例的有益效果是：
本发明实施例，由于提供了使用POP半导体封装结构集成的第一动态随机存取存储器和第二动态随机存取存储器，因此同时具有第一动态随机存取存储器封装和第二动态随机存取存储器封装的优点，例如低成本、高带宽、低功耗和快速转变等。
附图说明
图1是根据本发明一实施例的半导体封装结构的横截面示意图，该半导体封装结构包括：混合的SOC封装和堆叠在该混合的SOC封装之上的DRAM封装。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异作为区分组件的方式，而是以组件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
本发明将参考特定的实施例和具体的附图进行描述，但是本发明并不限制于该特定的实施例和附图，并且本发明仅由权利要求书进行限制。描述的附图仅是原理图并且不具有限制含义。在附图中，出于说明目的而夸大了某些元件的尺寸，并且附图并非是按比例绘制。附图中的尺寸和相对尺寸并不对应本发明实践中的真实尺寸。
图1是根据本发明一实施例的半导体封装结构500a的横截面示意图，该半导体封装结构500a包括：混合的SOC封装300a和堆叠在该混合的SOC封装300a上的DRAM封装400a。在一些实施例中，半导体封装结构500a可以是POP半导体封装结构。半导体封装结构500a包括：安装于基底200上的至少两个垂直堆叠的晶圆级(wafer-level)半导体封装。在这个实施例中，该垂直堆叠的晶圆级半导体封装包括：混合的SOC封装300a和垂直堆叠于该混合的SOC封装300a之上的DRAM封装400a。
如图1所示，基底200(例如印刷电路版(PrintedCircuitBoard，PCB))可以由PP(polypropylene，聚丙烯)形成。需要注意的是：基底200可以为单层或多层结构。多个连接垫(pad)和/或导电迹线(conductivetrace)(均未图示)设置于基底200的祼芯片接触面202之上。在一个实施例中，导电迹线可以包括：信号迹线部分或接地迹线部分，用于SOC封装300a和DRAM封装400a的输入/输出(I/O)连接。另外，SOC封装300a直接安装于导电迹线之上。在一些其它实施例中，连接垫设置于芯片接触面202之上，并且连接至导电迹线的不同端。SOC封装300a直接安装于连接垫上。
如图1所示，混合的SOC封装300a通过接合工艺(bondingprocess)安装于基底200的祼芯片接触面202之上。混合的SOC封装300a是通过导电结构322安装于基底200之上。混合的SOC封装300a可以是包含SOC祼芯片302、DRAM祼芯片600和RDL(redistributionlayer，重分布层)结构316的三维(3D)半导体封装。例如，SOC祼芯片302可以包括：逻辑祼芯片，该逻辑祼芯片包括如下至少一项：CPU(centralprocessingunit，中央处理单元)、GPU(graphicprocessingunit，图像处理单元)和DRAM控制器。DRAM祼芯片600可以包括：宽I/O(WideI/O)DRAM祼芯片，垂直地堆叠于SOC祼芯片302之上。在本实施例中，通过TSV(ThroughSiliconvia，硅通孔)技术装配混合的SOC封装300a中的DRAM祼芯片600。混合的SOC封装300a中的SOC祼芯片302和DRAM祼芯片600由通孔(诸如通孔308，310)互相连接和/或连接至RDL结构316。需要注意的是：SOC祼芯片302的数量和DRAM祼芯片600的数量并不限制于公开的实施例。
如图1所示，SOC祼芯片302具有后表面302a和前表面302b。通过倒装芯片技术装配SOC祼芯片302。SOC祼芯片302的后表面302a接近或者对齐于混合的SOC封装300a的顶部表面324。SOC祼芯片302的连接垫304设置于前表面302b之上，以电性连接至SOC祼芯片302的电路(未示出)。在一些实施例中，连接垫304属于SOC祼芯片302的互连结构(未示出)的最顶层金属层。SOC祼芯片302的连接垫304与对应的通孔308接触。
如图1所示，DRAM祼芯片600堆叠于SOC祼芯片302的前表面302b之上。DRAM祼芯片600通过设置于SOC祼芯片302之上的通孔308耦接至SOC祼芯片302的连接垫304。DRAM祼芯片600可以包括：穿过DRAM祼芯片600而形成的TSV内连结构602。排列为阵列的TSV内连结构602可用于从DRAM祼芯片600向SOC祼芯片302和/或基底200传送I/O信号、接地信号或功率信号。TSV内连结构602可以设计为符合引脚布置规则，例如JEDEC(JointElectronDeviceEngineeringCouncil，固态技术协会)的宽I/O存储器规范。需要注意的是，阵列中的TSV内连结构的数量由DRAM祼芯片600和安装于其上的SOC祼芯片302的设计而定义，并且不限制公开的范围。通孔308耦接至TSV内连结构602。
如图1所示，混合的SOC封装300a进一步包括：模塑料(moldingcompound)312，围绕在SOC祼芯片302和DRAM祼芯片600的周围并且填充SOC祼芯片302和DRAM祼芯片600周围的任何间隙。模塑料312与SOC祼芯片302和DRAM祼芯片600接触。模塑料312也覆盖SOC祼芯片302的前表面302b。在一些实施例中，模塑料312可以由非导电材料形成，例如环氧树脂、树指、可塑聚合物(moldablepolymer)，等等。在该模塑料312基本上为液体时使用，然后通过化学反应固化，例如在环氧树脂或者树脂中。在一些其它实施例中，模塑料312可以是紫外的(ultraviolet，UV)或者热固化的聚合物，该聚合物作为能够设置在SOC祼芯片302和DRAM祼芯片600附近的凝胶或者可塑固体，然后通过UV工艺或者热固化工艺使该聚合物固化。模塑料312以模型固化。
如图1所示，混合的SOC封装300a进一步包括：RDL结构316，设置于DRAM祼芯片600和SOC祼芯片302之上，以便于DRAM祼芯片600位于SOC祼芯片302和RDL结构316之间。RDL结构316可以与模塑料312和DRAM祼芯片600的TSV内连结构602接触。在一些实施例中，RDL结构316可以具有一个或多个设置于一个或多个IMD(intermetaldielectric，内部金属介电)层317中的导电迹线318。导电迹线318是电性连接至对应的RDL接触垫320。RDL接触垫320暴露于阻焊层321的开口处。但是，需要注意的是：图1所示的导电迹线318的数量、IMD层317的数量和RDL接触垫320的数量仅是举例，并不用于限制本发明。
如图1所示，混合的SOC封装300a进一步包括：导电结构322，设置于RDL结构316的远离DRAM祼芯片600和SOC祼芯片302的表面。导电结构322通过RDL接触垫320耦接于导电迹线318。在一些实施例中，导电结构可以包括：导电凸块结构(例如铜凸块或焊料凸块结构)、导电柱结构、导电线结构或者导电胶结构。
如图1所示，DRAM祼芯片600使用TSV内连结构602和通孔308来连接SOC祼芯片302的连接垫304和RDL结构316的导电迹线318。另外，通孔310穿过SOC祼芯片302和RDL结构316之间的模塑料312，SOC祼芯片302的连接垫306通过该通孔310耦接至RDL结构316的导电迹线318。通孔310围绕DRAM祼芯片600。
如图1所示，设计导电迹线318自SOC祼芯片302的连接垫304和306以及DRAM祼芯片600的TSV内连结构602中的一个或多个扇出(fanout)，以提供SOC祼芯片302、DRAM祼芯片600和RDL接触垫320之间的电性连接。因此，RDL接触垫320可以具有比SOC祼芯片302的连接垫304和306以及DRAM祼芯片600的TSV内连结构602更大的接合间距(bondpitch)，该具有更大接合间距的RDL接触垫320适用于球栅阵列或者另外的封装安装系统。
如图1所示，DRAM封装400a通过接合工艺堆叠在混合的SOC封装300a之上。在一个实施例中，DRAM封装400a是具有符合管脚布置规则(如JEDECLPDDRI/O存储器规范)的LPDDRDRAM(low-powerdoubledatarateDRAM，低功耗双倍速率DRAM)封装。DRAM封装400a包括：主体418和至少一个LPDDRDRAM祼芯片，例如堆叠于主体418之上的三个LPDDRDRAM祼芯片402、404和406。主体418具有祼芯片接触面420和相对于祼芯片接触面420的凸块接触面422。在一些实施例中，宽I/ODRAM祼芯片的I/O引脚数量设计为不同于每个LPDDRDRAM祼芯片402、404和406的I/O引脚数量。在一个实施例中，宽I/ODRAM祼芯片600的I/O引脚数量大于每个LPDDRDRAM祼芯片402、404和406的I/O引脚数量的8倍。在本实施例中，如图1所示，有三个LPDDRDRAM祼芯片402、404和406安装于主体418的祼芯片接触面420之上。LPDDRDRAM祼芯片404通过粘贴(未示出)堆叠于LPDDRDRAM祼芯片402之上，以及LPDDRDRAM祼芯片406通过粘贴(paste)堆叠于LPDDRDRAM祼芯片404之上。LPDDRDRAM祼芯片402、404和406可以由接合线耦接至主体418，例如接合线414和416，具体的接合线414的两端分别连接金属垫424和LPDDRDRAM祼芯片402的连接垫408，接合线416的两端分别连接金属垫426和LPDDRDRAM祼芯片406的连接垫410。但是，堆叠的DRAM设备的数量不限制于公开的实施例。可选地，图1所示的三个LPDDRDRAM祼芯片402、404和406可以一个挨一个地(sidebyside)的布置。如此，LPDDRDRAM祼芯片402、404和406可以通过粘贴而安装于主体418的祼芯片接触面420上。主体418可以包括：电路428和金属垫424、426和430。金属垫424和426设置于电路428接近于祼芯片接触面420的顶部之上。金属垫430设置在电路428接近于凸块接触面422的底部之上。多个导电结构432设置于主体418的凸块接触面422之上，DRAM封装400a的电路428与RDL结构316的导电迹线318通过该多个导电结构432内部连接。在一些实施例中，导电结构432可以包括：导电凸块结构(如铜凸块或者焊料凸块结构)、导电柱结构、导电线结构或者导电胶结构。在一些实施例中，通孔314穿过混合的SOC封装300a中的DRAM封装400a和RDL结构316之间的模塑料312，DRAM封装400a通过该通孔314耦接至RDL结构316的导电迹线318。通孔314围绕SOC祼芯片302和DRAM祼芯片600。
在一个实施例中，如图1所示，DRAM封装400a进一步包括：模塑料412，覆盖主体418的祼芯片接触面420，并且包封(encapsulating)LPDDRDRAM祼芯片402、404和406和接合线414和416。
图2是根据本发明另一实施例的半导体封装结构500b的横截面示意图，该半导体封装结构500b包括：SOC封装300b和堆叠在该SOC封装300b之上的混合的DRAM封装400b。出于简洁，不再重复下文实施例中相同或者类似于参考图1所描述的先前实施例中的元件。半导体封装结构500a和半导体封装结构500b之间的不同在于：半导体封装结构500b包括：纯的SOC封装300b和垂直地堆叠于该SOC封装300b上的混合的DRAM封装400b。
如图2所示，SOC封装300b为包含SOC祼芯片302和RDL结构316的半导体封装。该SOC封装300b不包括任何集成于其中的DRAM祼芯片。SOC封装300b中的SOC祼芯片302由通孔(如通孔310)连接至RDL结构316。SOC祼芯片302的连接垫304与对应的通孔310接触。需要注意的是，SOC祼芯片302的数量不限制于公开的实施例。
如图2所示，混合的DRAM封装400b通过接合工艺堆叠在SOC封装300b之上。混合的DRAM封装400b为三维半导体封装，该三维半导体封装包括：堆叠在TSVDRAM封装之上的线接合DRAM封装。在本实施例中，混合的DRAM封装400b为LPDDRDRAM/宽I/ODRAM混合封装，该LPDDRDRAM/宽I/ODRAM混合封装包括：LPDDRDRAM祼芯片，符合特定引脚布置规则(如JEDECLPDDRI/O存储器规范)；以及宽I/ODRAM祼芯片，符合其它特定的引脚布置规则(如JEDEC宽I/O存储器规范)。混合的DRAM封装400b包括：主体418、堆叠于主体418之上的至少一个LPDDRDRAM祼芯片和堆叠于主体418之上的至少一个宽I/ODRAM祼芯片。在如图2所示的一些实施例中，存在三个LPDDRDRAM祼芯片402、404和406安装于主体418的祼芯片接触面420之上。LPDDRDRAM祼芯片404通过粘贴堆叠于LPDDRDRAM祼芯片402之上，以及LPDDRDRAM祼芯片406通过粘贴(未示出)堆叠在LPDDRDRAM祼芯片404之上。LPDDRDRAM祼芯片402、404和406由接合线耦接至主体418，例如接合线414和416。但是，堆叠的LPDDRDRAM祼芯片的数量不限制于公开的实施例。可选地，图2所示的三个LPDDRDRAM祼芯片402、404和406可以一个挨一个地设置。如此，LPDDRDRAM祼芯片402、404和406可以通过粘贴安装于主体418的祼芯片接触面420上。
在一个实施例中，如图2所示，主体418可以包括：电路(未示出)和金属垫424、426和430。金属垫424和426设置于电路428的顶部，该顶部靠近祼芯片接触面420。金属垫430设置在电路中的底部，该底部靠近凸块接触面430。接合线414的两端分别连接金属垫424和LPDDRDRAM祼芯片402的连接垫408，接合线416的两端分别连接金属垫426和LPDDRDRAM祼芯片406的连接垫410。
在一个实施例中，如图2所示，混合的DRAM封装400b进一步包括：模塑料412，该模塑料412覆盖主体418的祼芯片接触面420，并且包封LPDDRDRAM祼芯片402、404和406和接合线414和416。
如图2所示，混合的DRAM封装400b进一步包括：至少一个宽I/ODRAM祼芯片，例如两个嵌入于其中的宽I/ODRAM祼芯片600a和600b。在这个实施例中，两个宽I/ODRAM祼芯片600a和600b安装在凸块接触面422之上并且耦接至主体418的金属垫430。宽I/ODRAM祼芯片600a和600b一个挨一个地布置。但是，宽I/ODRAM祼芯片的数量和布置方式不限制于公开的实施例。宽I/ODRAM祼芯片600a和600b可以包括：对应的分别穿过宽I/ODRAM祼芯片600a和600b而形成的TSV内连结构602a和602b。布置为阵列的TSV内连结构602a和602b可用于从宽I/ODRAM祼芯片600a和600b向LPDDRDRAM祼芯片402、404和406和/或基底200传送I/O信号、接地信号或者功率信号。TSV内连结构602a和602b可以设计为符合引脚布置规则(如JEDEC宽I/O存储器规范)。需要注意的是：阵列中的TSV内连结构的数量由用于宽I/ODRAM祼芯片600a和600b以及安装于其上的LPDDRDRAM祼芯片402、404和406的设计而定，并且不限制公开的范围。TSV内连结构602a和602b耦接至主体418的金属垫430。在一些实施例中，宽I/ODRAM祼芯片600a和600b的I/O引脚数量设计为不同于任一LPDDRDRAM祼芯片402、404和406的I/O引脚数量。在一个实施例中，宽I/ODRAM祼芯片600a和600b的I/O引脚数量大于任一LPDDRDRAM祼芯片402、404和406的I/O引脚数量的8倍。
如图2所示，混合的DRAM封装400b进一步包括：模塑料442，设置于主体418的凸块接触面422之上。该模塑料442围绕宽I/ODRAM祼芯片600a和600b，并且填充宽I/ODRAM祼芯片600a和600b周围的任何空隙。模塑料442与宽I/ODRAM祼芯片600a和600b接触。
如图2所示，混合的DRAM封装400b进一步包括：RDL结构440，位于主体418的凸块接触面422之上。RDL结构440也设置在LPDDRDRAM祼芯片402、404和406和宽I/ODRAM祼芯片600a和600b之上。宽I/ODRAM祼芯片600a和600b位于主体418和RDL结构440之间。RDL结构440可以与模塑料442和宽I/ODRAM祼芯片600a和600b的TSV内连结构602a和602b接触。RDL结构440可以具有一个或多个导电迹线448，该一个或多个导电迹线448设置于一个或多个IMD层446中。导电迹线448电性连接至对应的RDL接触垫450。但是，需要注意的是：图2所示的导电迹线448的数量，IMD层446的数量和RDL接触垫450的数量仅是示例而不是本发明的限制。
如图2所示，通孔444穿过主体418的凸块接触面422和RDL结构440之间的模塑料442，LPDDRDRAM祼芯片402、404和406可以通过该通孔444耦接至RDL结构440的RDL接触垫450。通孔444围绕该宽I/ODRAM祼芯片600a和600b。
如图2所示，多个导电结构452设置于RDL结构440的RDL接触垫450之上，DRAM封装400b的导电迹线448通过该多个导电结构452与SOC封装300b的RDL结构316的导电迹线318内连。在一些实施例中，导电结构452可以包括：导电凸块结构(如铜凸块或者焊料凸块结构)、导电柱结构、导电线结构或者导电胶结构。在一些实施例中，通孔314穿过DRAM封装400b和SOC封装300b的RDL结构316之间的模塑料，DRAM封装400b的导电结构452由该通孔314耦接至SOC封装300b的RDL结构316。通孔314围绕SOC祼芯片302。
实施例提供了半导体封装结构500a和500b。半导体封装结构500a和500b中的任一提供了使用POP半导体封装结构集成的LPDDRDRAM和宽I/ODRAM混合存储器。POP半导体封装结构500a包括：SOC(或宽I/O)DRAM混合封装300a和堆叠于其上的LPDDRDRAM封装400a。POP半导体封装结构500b包括：纯的SOC封装300b和堆叠于其上的LPDDR/宽I/ODRAM混合封装400b。半导体封装结构500a和500b具有LPDDRDRAM封装结构的优点(诸如成本效应、快速转变，等等)以及宽I/ODRAM封装结构的优点(诸如高带宽，低功耗，等等)。半导体封装结构500a和500b可以满足成本效应、高带宽、低功耗和快速转变的需求。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (35)

1.一种半导体封装结构，其特征在于，包括：第一半导体封装和堆叠于所述第一半导体封装上的第二半导体封装；
所述第一半导体封装，包括：
第一半导体祼芯片，所述第一半导体祼芯片上具有第一连接垫；
第一通孔，设置于所述第一半导体祼芯片之上，并且耦接至所述第一连接垫；以及
第一动态随机存取存储器祼芯片，安装于所述第一半导体祼芯片之上，并且耦接至所述第一通孔；
所述第二半导体封装，包括：
主体，具有祼芯片接触面和位于所述祼芯片接触面对面的凸块接触面；以及
第二动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量。
2.如权利要求1所述的半导体封装结构，其特征在于，
所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量大于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
3.如权利要求1所述的半导体封装结构，其特征在于，所述第一动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述第一动态随机存取存储器祼芯片。
4.如权利要求1所述的半导体封装结构，其特征在于，所述第一半导体封装进一步包括：
重分布层结构，所述重分布层结构上具有第一导电迹线；
其中，所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片耦接于所述第一导电迹线。
5.如权利要求4所述的半导体封装结构，其特征在于，所述第一动态随机存取存储器祼芯片位于所述第一半导体祼芯片和所述重分布层结构之间。
6.如权利要求4所述的半导体封装结构，其特征在于，所述第一半导体封装结构进一步包括：
模塑料，围绕所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片，并且与所述重分布层结构、所述第一半导体祼芯片和所述第一动态随机存取存储器祼芯片接触；以及
第一导电结构，设置在所述重分布层结构中远离所述第一半导体祼芯片的表面之上，并且所述第一导电结构耦接至所述第一导电迹线。
7.如权利要求6所述的半导体封装结构，其特征在于，所述第二半导体封装通过第二通孔耦接至所述第一导电迹线，所述第二通孔穿过位于所述第二半导体封装和所述重分布层结构之间的所述模塑料。
8.如权利要求7所述的半导体封装结构，其特征在于，所述第二通孔围绕所述第一半导体祼芯片。
9.如权利要求6所述半导体封装结构，其特征在于，所述第一半导体祼芯片通过第三通孔耦接至所述第一导电迹线，所述第三通孔穿过所述第一半导体祼芯片和所述重分布层结构之间的所述模塑料。
10.如权利要求9所述的半导封装结构，其特征在于，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
11.如权利要求1所述的半导体封装结构，其特征在于，进一步包括：基底，其中所述第一和第二半导体封装通过导电结构安装于所述基底之上。
12.一种半导体封装结构，其特征在于，包括：第一半导体封装和堆叠于所述第一半导体封装上的第二半导体封装；
所述第一半导体封装，包括：
半导体祼芯片，所述半导体祼芯片之上具有连接垫；以及
第一通孔，设置在所述半导体祼芯片之上，并且耦接至所述连接垫；
所述第二半导体封装，包括：
主体，具有祼芯片接触面和位于所述祼芯片接触面对面的凸块接触面；以及
第一动态随机存取存储器祼芯片，安装于所述凸块接触面之上，并且耦接至所述主体；以及
第二动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量。
13.如权利要求12所述的半导体封装结构，其特征在于，
所述第一动态随机存取存储器祼芯片的输入/输出引脚的数量大于所述第二动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
14.如权利要求12所述的半导体封装结构，其特征在于，所述第一动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述第一动态随机存取存储器祼芯片。
15.如权利要求12所述的半导体封装结构，其特征在于，所述第一半导体封装进一步包括：
第一重分布层结构，所述第一重分布层结构上具有第一导电迹线；其中，所述半导体祼芯片耦接于所述第一导电迹线。
16.如权利要求15所述的半导体封装结构，其特征在于，所述第一半导体封装进一步包括：
第一模塑料，围绕所述半导体祼芯片，并且与所述第一重分布层结构和所述半导体祼芯片接触；以及
第一导电结构，设置在所述第一重分布层结构中远离所述半导体祼芯片的表面上，其中所述第一导电结构耦接至所述第一导电迹线。
17.如权利要求16所述的半导体封装结构，其特征在于，所述第二半导体封装进一步包括：
第二模塑料，设置在所述主体的凸块接触面之上，并且围绕所述第一动态随机存取存储器祼芯片；以及
第二重分布层结构，位于所述第二模塑料之上，并且所述第二重分布层结构上具有第二导电迹线；
其中，所述第一动态随机存取存储器祼芯片位于所述主体和所述第二重分布层结构之间，并且耦接至所述第二导电迹线。
18.如权利要求17所述的半导体封装结构，其特征在于，所述第二半导体封装通过第二通孔耦接至所述第一导电迹线，所述第二通孔穿过位于所述第二半导体封装和所述第一重分布层结构之间的所述第一模塑料。
19.如权利要求18所述的半导体封装结构，其特征在于，所述第二通孔围绕所述半导体祼芯片。
20.如权利要求17所述的半导体封装结构，其特征在于，所述第二动态随机存取存储器祼芯片通过第三通孔耦接至所述第二重分布层结构，所述第三通孔穿过位于所述主体和所述第二重分布层结构之间的所述第二模塑料。
21.如权利要求20所述的半导体封装结构，其特征在于，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
22.如权利要求17所述的半导体封装结构，其特征在于，所述第二半导体封装通过第二导电结构安装于所述第一半导体封装之上，所述第二导电结构位于所述第二重分布层结构之上并且耦接所述第二重分布层结构。
23.如权利要求12所述的半导体封装，其特征在于，进一步包括：基底，所述第一和第二半导体封装通过第一导电结构安装于所述基底之上。
24.一种半导体封装结构，其特征在于，包括：片上系统封装和堆叠于所述片上系统封装上的动态随机存取存储器封装；
所述片上系统封装包括：
逻辑祼芯片，所述逻辑祼芯片上具有第一连接垫；
第一重分布层结构，耦接至所述逻辑祼芯片；以及
模塑料，围绕所述逻辑祼芯片，并且与所述第一重分布层结构和所述逻辑祼芯片接触；
所述动态随机存取存储器封装包括：
主体，具有祼芯片接触面和在所述祼芯片接触面对面的凸块接触面；以及
动态随机存取存储器祼芯片，安装于所述祼芯片接触面之上，并且由接合线耦接至所述主体；
其中，所述片上系统封装和所述动态随机存取存储器封装之一进一步包括：嵌于其中的额外的动态随机存取存储器祼芯片；
其中，所述额外的动态随机存取存储器祼芯片具有硅通孔内连结构，所述硅通孔内连结构穿过所述额外的动态随机存取存储器祼芯片。
25.如权利要求24所述的半导体封装结构，其特征在于，
所述动态随机存取存储器祼芯片的输入/输出引脚的数量不同于所述额外的动态随机存取存储器祼芯片的输入/输出引脚的数量；
或者，所述额外的动态随机存取存储器祼芯片的输入/输出引脚数量大于所述动态随机存取存储器祼芯片的输入/输出引脚的数量的8倍。
26.如权利要求24所述的半导体封装结构，其特征在于，所述片上系统封装进一步包括：
第一通孔，位于所述逻辑祼芯片之上，并且耦接至所述第一连接垫。
27.如权利要求24所述的半导体封装结构，其特征在于，所述动态随机存取存储器祼芯片封装通过第二通孔耦接至所述片上系统封装中的第一重分布层结构；
所述第二通孔穿过位于所述动态随机存取存储器封装和所述第一重分布层结构之间的所述模塑料。
28.如权利要求27所述的半导体封装结构，其特征在于，所述第二通孔围绕所述逻辑祼芯片。
29.如权利要求26所述的半导体封装结构，其特征在于，所述额外的动态随机存取存储器祼芯片嵌入于所述片上系统封装中，并且耦接所述第一通孔和所述第一重分布层结构。
30.如权利要求29所述的半导体封装结构，其特征在于，所述模塑料与所述额外的动态随机存取存储器祼芯片接触。
31.如权利要求29所述的半导体封装结构，其特征在于，所述逻辑祼芯片通过第三通孔耦接至所述重分布层结构，所述第三通孔穿过所述逻辑祼芯片和所述第一重分布层结构之间的所述模塑料。
32.如权利要求31所述的半导体封装结构，其特征在于，所述第三通孔围绕所述第一动态随机存取存储器祼芯片。
33.如权利要求24所述的半导体封装结构，其特征在于，所述动态随机存取存储器封装还包括：
第二重分布层结构，位于所述凸块接触面之上。
34.如权利要求33所述的半导体封装结构，其特征在于，所述额外的动态随机存取存储器祼芯片设置在所述主体和所述第二重分布层之间。
35.如权利要求24所述半导体封装结构，其特征在于，进一步包括：基底，所述第一和第二半导体封装通过导电结构安装在所述基底之上。
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