CN105977220B - 半导体封装组件 - Google Patents

半导体封装组件 Download PDF

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Publication number
CN105977220B
CN105977220B CN201610135933.0A CN201610135933A CN105977220B CN 105977220 B CN105977220 B CN 105977220B CN 201610135933 A CN201610135933 A CN 201610135933A CN 105977220 B CN105977220 B CN 105977220B
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moulding compound
redistribution layer
semiconductor chip
layer structure
semiconductor package
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CN105977220A (zh
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林子闳
萧景文
彭逸轩
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供半导体封装组件，半导体封装组件包含半导体芯片，第一模塑料覆盖半导体芯片的背面，重布层结构设置于半导体芯片的正面上，半导体芯片与重布层结构耦合，第二模塑料设置于半导体芯片的正面上且内嵌于重布层结构，被动组件设置于第二模塑料上且与半导体芯片耦合。

Description

半导体封装组件
技术领域
本发明是有关于半导体封装组件，特别是有关于具有被动组件的半导体封装组件。
背景技术
为了确保电子产品与通讯装置的微缩化与多功能性，需要小尺寸的半导体封装以支撑多接脚连接、高速和高功能性。多功能性半导体封装通常需要将被动组件整合于其中。然而，传统的半导体封装难以提供多余的区域让被动组件安装于其上。
因此，需要创新的半导体封装组件。
发明内容
本揭露的一些实施例提供半导体封装组件，其包含半导体芯片，第一模塑料覆盖半导体芯片的背面，重布层结构设置于半导体芯片的正面上，其中半导体芯片与重布层结构耦合，第二模塑料设置于半导体芯片的正面上，且内嵌于重布层结构，以及被动组件设置于第二模塑料上，且与半导体芯片耦合。
本揭露的另一些实施例提供半导体封装组件，其包含半导体芯片，第一模塑料设置于半导体芯片的第一表面上，重布层结构设置于半导体芯片的相对于第一表面的第二表面上，第二模塑料设置于半导体芯片的第二表面上，且内嵌于重布层结构，其中第二模塑料经由重布层结构与第一模塑料隔开，以及被动组件设置于第二模塑料上，且与半导体芯片耦合。
本揭露的另一些实施例提供半导体封装组件，其包含半导体芯片，第一模塑料与半导体芯片的第一表面接触，重布层结构覆盖半导体芯片相对于第一表面的第二表面的第一部分，第二模塑料覆盖半导体芯片的第二表面的第二部分，且内嵌于重布层结构，以及被动组件覆盖半导体芯片的第二表面的第二部分，其中第二模塑料设置于半导体芯片与被动组件之间。
附图说明
本发明能藉由阅读以下说明书的详细说明并配合所附
图式说明之范例而完全理解，其中：
图1-4显示了根据某些实施例，半导体封装组件的剖面示意图。
其中，符号说明如下：
200～基座；
202～芯片附着表面；
300～半导体芯片；
302～正面；
302a、302b～部分；
304～背面；
306、322～侧壁表面；
308、328～接垫；
310～重布线结构；
312、314、321a、321b～表面；
316～导线；
318～金属间介电层；
320～第二模塑料；
324～导电凸块；
326～焊料；
330～被动组件；
332～导电结构；
350a、350b、350c、350d～半导体封装；
360～第一模塑料；
500a、500b、500c、500d～半导体封装组件。
具体实施方式
以下描述用以实施本揭露的实施例。然而，此描述仅是用以说明本揭露的原理，且并非用以限制本揭露的范围。本揭露的范围以申请专利范围决定。
以下的揭露内容提供许多不同的实施例或范例以及图式，然而，这些仅是用以说明本揭露的原理，且并非用以限制本揭露的范围。本揭露的范围是以申请专利范围决定。本揭露的图式仅为说明之用，且并非用以限定本揭露的范围。在图式中，为了清楚说明本揭露，部分组件的尺寸可能被放大且并未照实际比例绘制。此尺寸以及相对的尺寸并未对应实施本揭露时的实际尺寸。
图1显示根据某些实施例，半导体封装组件(semiconductor package assembly)500a的剖面示意图。在一些实施例，半导体封装组件500a为晶圆级(wafer-level)半导体封装组件，例如，覆晶(flip-chip)半导体封装组件。为清楚地显示半导体封装组件的被动组件和导电结构的排列方式，而放大被动组件和导电结构的尺寸。
如图1所示，半导体封装组件500a包含至少一安装于基座(base)200上的晶圆级半导体封装(semiconductor package)350a。在此实施例，晶圆级半导体封装350a包含系统芯片(system-on-chip,SOC)封装。
如图1所示，基座200例如为印刷电路板(printed circuit board,PCB)，可由聚丙烯(polypropylene,PP)制成。应该注意的是基座200可为单层或多层结构。多个接垫(未绘示)及/或导线(未绘示)设置于基座200的芯片附着(die-attach)表面202上。在一实施例，导线可包含电源段(power segment)，信号线段(signal trace segment)或接地线段(ground trace segment)，其用来作为晶圆级半导体封装350a的输入/输出(input/output,I/O)连接。此外，晶圆级半导体封装350a直接安装于导线上。在其它一些实施例，接垫设置于芯片附着表面202上，并连接至导线的不同的终端。接垫为用来让晶圆级半导体封装350a直接安装于其上。
如图1所示，晶圆级半导体封装350a通过接合制程(bonding process)安装于基座200的芯片附着表面202上。晶圆级半导体封装350a经由导电结构332安装于基座200上。晶圆级半导体封装350a包含半导体芯片300及重布层(redistribution layer,RDL)结构310。半导体芯片300例如为系统芯片(SOC)，可包含含有中央处理单元(central processingunit,CPU)、图形处理单元(graphics processing unit,GPU)、动态随机存取内存(dynamicrandom access memory,DRAM)控制器或上述组合的逻辑芯片。
如图1所示，半导体芯片300的接垫308设置于正面302以电性连接于半导体芯片300的电路(未绘示)。在一些实施例，接垫308属于半导体芯片300的内联机结构(未绘示)的最上面的(uppermost)金属层。应该注意的是，整合于半导体封装组件500a内的半导体芯片300的数目并不限定于本发明实施例所揭露的样态。
如图1所示，晶圆级半导体封装350a更包含覆盖且围绕半导体芯片300的第一模塑料(molding compound)360。第一模塑料360设置于半导体芯片300的背面304和侧壁表面306上，且与半导体芯片300的背面304和侧壁表面306接触。在一些实施例，第一模塑料360可由非导电性材料制成，例如环氧化物(epoxy)、树脂(resin)、可塑性聚合物(moldablepolymer)或相似的材料。可在大体上为液态时涂布第一模塑料360，并经由化学反应固化第一模塑料360，例如成为环氧化物或树脂。在其它一些实施例，第一模塑料360可为紫外光(UV)或热固化聚合物的胶体或具延展性的固体，而能环绕地设置在半导体芯片300周围，且可经由UV或热固化制程来固化。第一模塑料360可使用模具(未绘示)固化。在其它一些实施例，第一模塑料360可由底部填充层取代。
如图1所示，晶圆级半导体封装350a更包含重布层(RDL)结构310设置于半导体芯片300的正面302上。重布层结构310具有相对的表面312及表面314。此外，重布层结构310可具有一或多个导线316设置于一或多层的金属间介电(inter-metal dielectric,IMD)层318内。半导体芯片300连接至靠近表面314中央部分的导线316。第一模塑料360覆盖重布层结构310的表面314。此外，第一模塑料360与围绕表面314中央部分的周边部分接触。然而，应该注意的是，如图1所示的导线316的数目及重布层结构310的金属间介电层318的数目仅为一示例，且本发明并不将其限定。
如图1所示，晶圆级半导体封装350a更包含设置于重布层结构310的远离半导体芯片300的表面312上的导电结构332。导电结构332经由设置于导线316上且靠近表面312的接垫328与导线316耦合。此外，导电结构332经由重布层结构310与第一模塑料360隔开。换句话说，导电结构332未接触于第一模塑料360。在一些实施例，导电结构332可包含导电凸块结构，例如铜凸块或焊料凸块结构、导电柱结构、导电线结构或导电胶(paste)结构。
如图1所示，晶圆级半导体封装350a更包含设置于半导体芯片300的正面302的第二模塑料320。第二模塑料320包含靠近半导体芯片300的表面321a及相对于表面321a的表面321b。在一些实施例，重布层结构310及第二模塑料320各别覆盖半导体芯片300的正面302的不同部份。例如，重布层结构310覆盖半导体芯片300的正面302的部分302a。第二模塑料320覆盖半导体芯片300的正面302的部分302b。部分302a与部分302b相邻。此外，第二模塑料320内嵌于重布层结构310。在一些实施例，第二模塑料320的侧壁表面322被重布层结构310围绕。此外，第二模塑料320经由半导体芯片300和重布层结构310与第一模塑料360隔开。在一些实施例，第二模塑料320的材料与制造过程可相似于第一模塑料360的材料与制造过程。
如图1所示，晶圆级半导体封装350a更包含被动组件330(例如解耦合电容器(decoupling capacitor))设置于第二模塑料320上，例如，在一些实施例，被动组件330可包含被动组件芯片或分离的被动组件，例如，多层陶瓷芯片电容器(multilayer ceramicchip capacitor,MLCC)组件或整合式被动组件(integrated passive device,IPD)。在一些实施例，如图1所示，被动组件330及导电结构332设置于靠近重布层结构310的远离半导体芯片300的表面312上。在此实施例，被动组件330与第二模塑料320间的界面(即第二模塑料320的表面321b)与重布层结构310的远离半导体芯片300的表面312对齐。
在一些实施例，如图1所示，被动组件330经由导电凸块324和焊料326与半导体芯片300耦合。导电凸块324穿过第二模塑料320而形成。此外，导电凸块324与被动组件330的终端(未绘示)接触。焊料326设置在对应的导电凸块324与半导体芯片300的对应的接垫308之间，并且与对应和导电凸块324与半导体芯片300的对应的接垫308接触。在一些实施例，导电凸块324及焊料326被第二模塑料320围绕。因此，导电凸块324及焊料326通过第二模塑料320与重布层结构310电性隔离。在一些实施例，导电凸块324可包含铜凸块或铜柱。在一些实施例，被动组件330未使用重布层结构310的导线316与半导体芯片300耦合。因此，可减低被动组件330与半导体芯片300之间的导电路径的长度(例如，此实施例的导电凸块324和对应焊料326的长度)以增进半导体封装组件500a的信号完整性/电源完整性(signalintegrity/power integrity,SI/PI)的效能。
在一些实施例，如图1所示，被动组件330的厚度(高度)被设计成小于导电结构332的直径。具有细薄轮廓的被动组件330可利于让晶圆级半导体封装350a的导电结构332实施表面安装技术(surface-mount technology,SMT)重新加工(rework)制程。
图2显示根据某些实施例，半导体封装组件500b的剖面示意图。在此所述与之前图1相同或相似的实施例的组件为简洁目的而省略。
如图2所示，半导体封装组件500b与图1所示的半导体封装组件500a之间的其中一个不同处在于半导体封装350b的被动组件330的一部分内嵌于重布层结构310内。在此实施例，被动组件330与第二模塑料320间的界面(即第二模塑料320的表面321b)位于半导体封装组件500b的晶圆级半导体封装350b的重布层结构310的相对的表面312与表面314之间。
在此实施例，如图2所示，被动组件330在重布层结构310的表面312上的厚度(高度)小于导电结构332的直径。具有细薄轮廓的被动组件330可利于让晶圆级半导体封装350b的导电结构332实施表面安装技术(SMT)重新加工制程。
图3显示根据某些实施例，半导体封装组件500c的剖面示意图。在此所述与之前第1-2图相同或相似的实施例的组件为简洁目的而省略。
如图3所示，半导体封装组件500c与图1所示的半导体封装组件500a之间的其中一个不同处在于半导体封装350c的被动组件330未使用任何导电凸块而与焊料326耦合。换句话说，半导体封装350c与焊料326直接接触。在此实施例，被动组件330与第二模塑料320间的界面(即第二模塑料320的表面321b的位置)位于半导体封装组件500c的晶圆级半导体封装350c的重布层结构310的相对的表面312与表面314之间。
在此实施例，如图3所示，被动组件330在重布层结构310的表面312上的厚度(高度)小于导电结构332的直径。具有细薄轮廓的被动组件330可利于让晶圆级半导体封装350c的导电结构332实施表面安装技术(SMT)重新加工制程。
图4显示根据某些实施例，半导体封装组件500d的剖面示意图。在此所述与之前图1-3相同或相似的实施例的组件为简洁目的而省略。
如图4所示，半导体封装组件500d与图1所示的半导体封装组件500a之间的其中一个不同处在于重布层结构310的一些导线316可延伸至第二模塑料320内而形成。应该注意的是，延伸至第二模塑料320内的导线316经由第二模塑料320与导电凸块324和焊料326电性隔离。
实施例提供半导体封装组件。半导体封装组件包含晶圆级半导体封装，晶圆级半导体封装包含半导体芯片。第一模塑料覆盖半导体芯片的背面。重布层(RDL)结构设置于半导体芯片的正面上。半导体芯片与重布层结构耦合。第二模塑料设置于半导体芯片的正面上，且内嵌于重布层结构。被动组件设置于第二模塑料上，且与半导体芯片耦合。被动组件与导电结构(例如，焊球或凸块结构)设置于靠近重布层结构的远离半导体芯片的表面上。被动组件经由穿过第二模塑料的导电凸块与半导体芯片耦合。此外，重布层结构和第二模塑料各别地覆盖半导体芯片的正面的不同部分。应该注意的是，被动组件未使用重布层结构的导线而与半导体芯片耦合。因此，可减低被动组件与半导体芯片之间的导电路径的长度(即导电凸块的长度)以更增进半导体封装组件的信号完整性/电源完整性(SI/PI)的效能。另外，被动组件的厚度(高度)被设计成小于导电结构的直径。具有细薄轮廓的被动组件可利于让晶圆级半导体封装的导电结构实施表面安装技术(SMT)重新加工制程。在其它一些实施例，晶圆级半导体封装的被动组件被设计成内嵌于重布层结构的一部分以更减低被动组件与半导体芯片之间的距离。
虽然本揭露的实施例及其优点已揭露如上，但应该了解的是，任何所属技术领域中具有通常知识者，在不脱离本揭露的精神和范围内，当可作更动、替代与润饰。此外，本揭露的保护范围并未局限于说明书内所述特定实施例中的制程、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中具有通常知识者可从本揭露揭示内容中理解现行或未来所发展出的制程、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大抵相同功能或获得大抵相同结果皆可根据本揭露使用。因此，本揭露的保护范围包括上述制程、机器、制造、物质组成、装置、方法及步骤。另外，每一申请专利范围构成个别的实施例，且本揭露的保护范围也包括各个申请专利范围及实施例的组合。

Claims (20)

1.一种半导体封装组件，包括:
一半导体芯片；
一第一模塑料，覆盖该半导体芯片的一背面；
一重布层结构，设置于该半导体芯片的一正面上，其中该半导体芯片与该重布层结构耦合；
一第二模塑料，设置于该半导体芯片的该正面上，且内嵌于该重布层结构；以及
一被动组件，设置于该第二模塑料上，且与该半导体芯片耦合；
其中，该重布层结构包括一延伸至该第二模塑料内的导线。
2.如权利要求1所述的半导体封装组件，更包括:
一导电凸块，穿过该第二模塑料，其中该被动组件经由该导电凸块与该半导体芯片耦合。
3.如权利要求1所述的半导体封装组件，其中该第二模塑料的一侧壁被该重布层结构围绕。
4.如权利要求1所述的半导体封装组件，其中该第一模塑料经由该半导体芯片和该重布层结构与该第二模塑料隔开。
5.如权利要求1所述的半导体封装组件，其中该被动组件内嵌于该重布层结构。
6.如权利要求1所述的半导体封装组件，其中该被动组件与该第二模塑料之间的一界面与该重布层结构的一远离于该半导体芯片的第一表面对齐。
7.如权利要求6所述的半导体封装组件，更包括:
一导电结构，设置于该重布层结构的该第一表面上，其中该导电结构与重布层结构耦合。
8.一种半导体封装组件，包括:
一半导体芯片；
一第一模塑料，设置于该半导体芯片的一第一表面上；
一重布层结构，设置于该半导体芯片的一相对于该第一表面的第二表面上；
一第二模塑料，设置于该半导体芯片的该第二表面上，且内嵌于该重布层结构，其中该第二模塑料经由该重布层结构与该第一模塑料隔开；以及
一被动组件，设置于该第二模塑料上，且与该半导体芯片耦合；
该重布层结构包括一延伸至该第二模塑料内的导线。
9.如权利要求8所述的半导体封装组件，其中该重布层结构和该第二模塑料覆盖该半导体芯片的该第二表面的不同部分。
10.如权利要求8所述的半导体封装组件，更包括:
一导电凸块，穿过该第二模塑料，其中该被动组件经由该导电凸块与该半导体芯片耦合。
11.如权利要求8所述的半导体封装组件，其中该第二模塑料的一侧壁被该重布层结构围绕。
12.如权利要求8所述的半导体封装组件，其中该被动组件内嵌于该重布层结构。
13.如权利要求8所述的半导体封装组件，其中该被动组件与该第二模塑料之间的一界面与该重布层结构的一远离于该半导体芯片的第一表面对齐。
14.如权利要求13所述的半导体封装组件，更包括:
一导电结构，设置于该重布层结构的该第一表面上，其中该导电结构与该重布层结构耦合。
15.一种半导体封装组件，包括:
一半导体芯片；
一第一模塑料，与该半导体芯片的一第一表面接触；
一重布层结构，覆盖该半导体芯片相对于该第一表面的一第二表面的一第一部分；
一第二模塑料，覆盖该半导体芯片的该第二表面的一第二部分，且内嵌于该重布层结构；以及
一被动组件，覆盖该半导体芯片的该第二表面的该第二部分，其中该第二模塑料设置于该半导体芯片与该被动组件之间；
其中该重布层结构包括一延伸至该第二模塑料内的导线。
16.如权利要求15所述的半导体封装组件，其中该第二模塑料经由该重布层结构与该第一模塑料隔开。
17.如权利要求15所述的半导体封装组件，更包括:
一导电凸块，穿过该第二模塑料，其中该被动组件经由该导电凸块与该半导体芯片耦合。
18.如权利要求15所述的半导体封装组件，其中该被动组件内嵌于该重布层结构。
19.如权利要求15所述的半导体封装组件，其中该被动组件与该第二模塑料的一界面与该重布层结构的一远离于该半导体芯片之间的第一表面对齐。
20.如权利要求19所述的半导体封装组件，更包括:
一导电结构，设置于该重布层结构的该第一表面上，其中该导电结构与该重布层结构耦合。
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