CN103843136A - 在ic封装中封装dram和soc - Google Patents

在ic封装中封装dram和soc Download PDF

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Publication number
CN103843136A
CN103843136A CN201280048525.1A CN201280048525A CN103843136A CN 103843136 A CN103843136 A CN 103843136A CN 201280048525 A CN201280048525 A CN 201280048525A CN 103843136 A CN103843136 A CN 103843136A
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China
Prior art keywords
connector
substrate
group
nude film
memory
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Granted
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CN201280048525.1A
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CN103843136B (zh
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S·苏塔尔德加
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Publication of CN103843136A publication Critical patent/CN103843136A/zh
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Abstract

一种集成电路封装，包括第一存储器裸片、第二存储器裸片、第一基板和第二基板，第一存储器裸片具有第一组连接件，第二存储器裸片布置成邻近第一存储器裸片，第二存储器裸片具有第二组连接件，第一基板具有第一开口和第二开口，第一基板具有第三组连接件和第四组连接件，第三组连接件经由第一开口连接到第一存储器裸片的第一组连接件，第四组连接件经由第二开口连接到第二存储器裸片的第二组连接件，并且第二基板具有设置在其上的第一集成电路。第一基板连接到第二基板，其中第一集成电路设置在第一基板和第二基板之间。

Description

在IC封装中封装DRAM和SOC
相关申请的交叉引用
本申请要求2012年8月21日提交的申请号为13/590,949的美国专利申请的优先权，并且还要求2011年8月23日提交的申请号为61/526,586的美国临时申请以及2011年10月18日提交的申请号为61/548,344的美国临时申请的权益。
本申请涉及2009年9月23日提交的申请号为12/565,430的美国申请，其要求以2008年9月23日提交的申请号为61/099,355和2008年12月9日提交的申请号为61/121,018的美国临时申请为优先权。
上述申请的公开内容在此被全文引入作为参考。
技术领域
本公开总体涉及集成电路，更具体地涉及在单个集成电路(IC)封装中封装动态随机存取存储器(DRAM)和片上系统(SOC)。
背景技术
在此提供的背景描述是为了大致呈现本公开的环境。当前署名的发明人的工作，到该工作在本背景部分被描述的程度，以及在提交之时本不能作为现有技术的本说明书的各个方面，既非明确也非隐含地被认为是针对本发明的现有技术。
动态随机存取存储器(DRAM)产业已经试图解决涉及高性能DRAM的问题，高性能DRAM被用于高端应用处理器，诸如智能电话或平板电脑处理器。如今，产业中正在使用低功率(LP)双倍数据速率(DDR)DRAM，诸如LP-DDR2和DDR3DRAM。在本公开中，术语DDR或DDRx(其中x是大于或等于1的整数)将分别用于表示DDR DRAM或DDRx DRAM。缩写DRAM将被省略以提高可读性。
电子器件工程联合会(JEDEC)目前正在讨论LP-DDR3、DDR4以及超宽I/O DRAM。超宽I/O DRAM被期望解决带宽挑战，但是它的代价是需要昂贵的硅穿孔(TSV)技术。除了成本，对于每一代的超宽I/O DRAM，客户将需要利用超宽I/O DRAM来重新设计TSV和/或片上系统(SOC)。
发明内容
集成电路封装包括第一存储器裸片、第二存储器裸片、第一基板和第二基板，第一存储器芯片具有第一组连接件，第二存储器裸片布置成邻近第一存储器裸片，第二存储器裸片具有第二组连接件，第一基板具有第一开口和第二开口，第一基板具有第三组连接件和第四组连接件，第三组连接件经由第一开口连接到第一存储器裸片的第一组连接件，第四组连接件经由第二开口连接到第二存储器裸片的第二组连接件，第二基板具有设置在其上的第一集成电路。第一基板连接到第二基板，其中第一集成电路设置在第一基板和第二基板之间。
在其它特征中，第三组和第四组连接件中的每组连接件被布置成三排，间距为小于或等于0.4毫米。
在其它特征中，第一集成电路是片上系统。第一和第二存储器裸片被设置在所述第一基板的顶部。第一基板被设置在第二基板的顶部。
在其它特征中，该集成电路封装还包括热沉，其设置在第一和第二存储器裸片的顶部。
在其它特征中，第三组连接件通过键合引线被连接到第一组连接件，并且第二组连接件通过键合引线被连接到第四组连接件。
在其它特征中，集成电路封装被配置为连接到印刷电路板上的连接件或第二集成电路的连接件。
在其它特征中，第一和第二存储器裸片是双倍数据速率的动态随机存取存储器。
在其它特征中，集成电路封装被结合到计算设备中。计算设备包括智能电话、平板电脑、膝上型电脑、个人计算机、电视、或装备盒。
在其它特征中，集成电路封装还包括第三存储器裸片、第四存储器裸片、第三基板，第三存储器裸片具有第五组连接件，第四存储器芯片被布置成邻近第三存储器裸片，第四存储器裸片具有第六组连接件，第三基板具有第三开口和第四开口，第三基板具有第七组连接件和第八组连接件，第七组连接件经由第三开口连接到第三存储器裸片的第五组连接件，第八组连接件经由第四开口连接到第四存储器裸片的第六组连接件。
在其它特征中，第三基板设置在第一基板的顶部，且第一和第二存储器芯片被设置在第一和第三基板之间。
在其它特征中，集成电路封装还包括多个支柱，该支柱可用来将第三基板固定在第一基板的顶部，并在第一和第三基板之间提供连接。
在其它特征中，第三和第四存储器裸片设置在第三基板的顶部。
根据该详细描述、权利要求和附图，本公开的进一步应用领域将变得明显。该详细描述和具体示例仅用来举例说明而非用于限制本公开的范围。
附图说明
根据该详细描述和附图，将能更全面地理解本公开，其中：
图1描绘了集成电路(IC)封装，其包括使用堆叠式封装(POP)技术的布置在片上系统(SOC)顶部上的动态随机存取存储器(DRAM)封装；
图2描绘了IC封装，其包括DRAM封装和以倒装芯片结构布置在封装基板上的SOC；
图3A描绘了包括DRAM封装和SOC的IC封装，其中将DRAM封装连接到封装基板的焊球被推向DRAM封装的边缘；
图3B描绘了DRAM封装，其包括在DRAM封装每一侧上的三排0.8毫米间距的焊球；
图3C描绘了DRAM封装，其包括在DRAM封装单侧上的三排0.4毫米间距的焊球；
图3D描绘了0.4毫米间距焊球的一种布置，其中内侧排的每两个焊球的一个焊球被移除；
图4A描绘了IC封装，其包括布置在DRAM封装和封装基板之间的中间体，其中SOC布置在封装基板上；
图4B描绘了IC封装，其包括DRAM封装以及以倒装芯片结构布置在封装基板上的窗口中的SOC；
图4C描绘了IC封装，其包括布置在DRAM封装和封装基板之间的中间体，其中SOC被布置在封装基板上的窗口中；
图5A描绘了IC封装的平面图，其包括布置在两个DRAM裸片上的SOC；
图5B描绘了IC封装，其包括叠置在SOC顶部的双DRAM封装，该SOC被布置在封装基板上；
图6详细地描绘了图5B的IC封装；以及
图7描绘了IC封装，其包括叠置在SOC顶部的多个双DRAM封装并且包括热沉，该SOC被布置在封装基板上。
具体实施方式
低功率(LP)双倍数据速率(DDR)LP-DDR3动态随机存取存储器(DRAM)可以使LP-DDR2DRAM的带宽变成双倍。大多数应用处理器不能达到LP-DDR2的最大承诺性能，因为LP-DDR2的引脚输出是源自LP-DDR1的，其中最初对于速度的要求较不显著。然而，一个重要的特征是能够使用堆叠式封装(POP)的封装方式将DRAM叠置到片上系统(SOC)的顶部。为了使用POP封装将DRAM叠置到SOC的顶部，LP-DDR1的引脚必须围绕封装的周边分布，以允许直接将SOC放置于LP-DDR1封装的中心之下。然而，引脚的分布产生了相对于标准DDR2或DDR3更长的信号迹线。
当产业从LP-DDR1转移到LP-DDR2，产业并未认识到保持LP-DDR1的引脚输出将加重得到良好信号完整性的难度。当转移到LP-DDR2时，产业并未遵循DDR3的引脚输出的方式，因为标准DDR3式的封装不可能进行POP式的DRAM/SOC集成。根本上，在DDR3下方唯一可用的空间的宽度约为2mm左右。此外，DDR3的中心具有突起，用于将DDR3裸片引线键合到DDR3基板。因此，大多数SOC不能使用传统的DDR3封装适配到可用空间中。
本公开涉及各种封装结构和架构，其允许堆叠DRAM和单个IC封装中的SOC。此外，当使用32位(x32)DDR时，在此公开的封装系统和方法减小了封装尺寸，并且允许使用64位(x64)DDR而不需要改变设计。
现在参考图1，集成电路(IC)封装100包括DDRx封装102，其使用堆叠式封装(POP)技术布置在SOC104的顶部上。SOC104被布置在封装基板106上。使用焊球108将DDRx封装102连接到封装基板106。IC封装100可以被封装和布置在印刷电路板(PCB)上，或使用键合焊盘110和/或焊球112被附接至另一个IC。焊球108围绕SOC104并限制SOC104的宽度和高度。
现在参考图2，IC封装150包括DDRx封装102和SOC104，SOC104以倒装芯片结构布置在封装基板106上。虽然图2示出了封装基板106使用球栅阵列(BGA)型封装，任何其它类型的封装，诸如四方扁平封装(QFP)或四方扁平无引线(QFN)封装可被代替地使用。
现在参考图3A-3D，IC封装200包括DDRx封装202和SOC204。在图3A中，用于将DDRx封装202连接到封装基板106的焊球208被推向DDRx封装202的边缘，使得SOC204可以比图1和2所示的SOC104更宽。在图3B中，标准DDRx封装在DDRx封装的每一例上具有三排0.8毫米间距焊球，其几乎没有为SOC留下空间(虚线所示)。在图3C中，三排0.8毫米间距焊球可以被减少到两排≤0.4毫米间距焊球，其留出了比图3B中所示更多的空间(虚线所示)。因此，在图3B中，焊球208可以排列为≤0.4mm的间距。在图3D中，内排中的焊球(相邻于SOC的排)可以排列为间距大于外排(相邻于DDRx封装的边缘的排)中的焊球。例如，内排中的一个或多个可替代焊球可以被移除，以允许额外的空间用于布线连接。
因此，如果使用0.4毫米间距的焊球，大约30个焊球可被包括在一排中，用于12mm高的DRAM封装(即，4排中包括约120个焊球)。使用这种改进的焊球布置的一个优点是，未来的高速移动类别的DRAM(例如，移动设备中使用的LP-DDR3)可以使用与使用中心I/O位置的PC类DRAM(例如，DDR3)相同的布局拓扑。这可以提供类似于PC类DRAM的性能，其封装将适合于移动应用处理器的POP-安装。
进一步地，由于120个焊球对于典型的x32宽度的I/O DRAM通常不是必需的，焊球的内排可被排列地稍微稀疏一些。例如，每两个焊球中的一个可以被移除。这将导致每个内排具有约20个焊球，间距为0.4毫米。因此，12mm高的封装仅需要100个引脚。这应该足以满足x32LP-DDR3的需求。如果不足，则一些焊球可分配到顶部和底部边缘上，只要焊球不会靠近封装的中心，因为封装的中心被用于打开DRAM裸片至基板的引线键合。
现在参考图4A-4C，可以在DDRx封装102和封装基板106之间使用中间体，以产生对于SOC204的附加空间。例如，在图4A中，IC封装250包括中间体252，其被布置在DDRx封装102与封装基板106之间。替代将DDRx封装102的焊球108向外推向IC封装250的边缘，中间体252包括焊球208，其被向外推向IC封装250的边缘。将焊球208向外推向IC封装250的边缘产生了对于SOC204的附加空间。中间体252提供了焊球108和焊球208之间的连接。
在图4B中，替代使用中间体，封装基板106可以包括窗口，其中布置了SOC204。例如，在所示的IC封装300中，封装基板106-1包括窗口302。窗口302沿着封装基板106-1的第一表面304布置，其与封装基板106-1的第二表面306相反，其中第一表面304相邻于IC封装300的底部，并且其中第二表面306相邻于DDRx封装102。
在图4C中，IC封装350包括中间体252和封装基板106-2。封装基板106-2包括窗口352。窗口352沿着封装基板106-2的第一表面354布置，其中第一表面354相邻于中间体252，并且与封装基板106-2的第二表面356相反，其中第二表面356相邻于IC封装350的底部。
现在参照图5A和5B，双DDRx封装可以堆叠在SOC的顶部。通常，在图5A中，IC封装400包括两个DRAM裸片402-1和402-2，以及SOC404。DRAM裸片402-1和402-2被切割成一对，并被用作基板，其顶部上堆叠了SOC404。DRAM裸片402-1和402-2中的每一个在每一侧上包括三排0.8毫米间距的焊球。
相反，在图5B中，IC封装450包括堆叠在SOC454顶部上的双DDRx封装452。SOC454布置在封装基板456上。双DDRx封装452包括两个DRAM裸片458-1和458-2。DRAM裸片458-1和458-2可以在封装之前被分离。在双DDRx封装452中，DRAM裸片458-1和458-2可以被布置成彼此更接近或彼此更远离。
DRAM裸片458-1和458-2中的每一个在一侧上仅包括三排0.4毫米间距的焊球460-1和460-2，而不是每一侧具有三排0.8毫米间距的焊球。由于焊球460-1和460-2的间距是图5A中所示的焊球间距的一半，IC封装450中的焊球数量在相同的空间量中可以变为两倍。因此，尽管每个DRAM的焊球总量在图5A和5B中是相同的，对应于DRAM的焊球可以仅布置在IC封装450的一侧。从DRAM裸片458-1到焊球460-1的连接可以布置在IC封装450的左侧，从DRAM裸片458-2到焊球460-2的连接可以布置在IC封装450的右侧。SOC454可以布置在DRAM458-1的焊球460-1与DRAM裸片458-2的焊球460-2之间的空间中的封装基板456上。
现在参考图6，IC封装450被详细示出。在双DDRx封装452中，DRAM裸片458-1和458-2被布置在封装基板470上。DRAM裸片458-1和458-2可以被集成到单个芯片中或者被实施为单独的芯片。双DDRx封装452的封装基板470包括两个窗口472-1和472-2。窗口开口并不居中，而是稍微偏置，使得窗口开口被置于离裸片的边缘约四分之一的距离(向内方向)。这可以被描述为似乎两个几乎相同的DDR3裸片458-1和458-2在水平方向上彼此相邻地布置(假定现有引脚是垂直布置)。
键合引线474-1和474-2分别将DRAM裸片458-1和458-2连接到封装基板470。这种布置，结合了将焊球460-1和460-2分别移动到封装基板470的左边缘和右边缘(在以上参考图3A进行说明)，减小了从DRAM裸片458-1和458-2到相应焊球460-1和460-2的布线距离。这转而降低了高速信号迹线(尤其是数据引脚上的迹线)的电感和寄生电容。
为了获得最大可能的灵活性和速度，控制和地址(C/A)总线可以被分配在IC封装450的中心周围，而数据总线可以被分配在IC封装450的外角。因此，对于x32(即32位)配置，8个数据引脚可以被分配在每个角上，并且对于x64(即64位)配置，16个数据引脚可以被分配在每个角上。进一步地，用于支持x64配置的额外8个引脚(加上每个关联的控制引脚)可以布置在最外部位置。这导致x32配置的较小的DRAM封装，同时保证了与x64配置的前向兼容性。这允许x32配置使用较小的封装以节省成本。
现在参考图7，示出了包括堆叠的DRAM芯片的IC封装500。例如，在IC封装500中，DRAM芯片458-1和458-2被布置在封装基板470-1上，并且DRAM裸片458-3和458-4被布置在封装基板470-2上。布置在封装基板470-1上的DRAM裸片458-1和458-2垂直堆叠在布置在封装基板470-2上的DRAM裸片458-3和458-4的顶部上。附加的DRAM裸片可以被垂直堆叠在DRAM裸片458-3和458-4的顶部上。散热器508被布置在DRAM裸片458-3和458-4的顶部上。热沉510被布置在散热器508的顶部上。
封装基板470-1包括键合焊盘501-1和501-2，其分别位于封装基板470-1的下表面和上表面上。焊球460-1和460-2将封装基板470-1的键合焊盘501-1连接到封装基板456。穿硅过孔502-1将键合焊盘501-1连接到键合焊盘501-2。
封装基板470-2包括键合焊盘501-3和501-4，其分别位于封装基板470-2的下表面和上表面上。穿硅过孔502-2将键合焊盘501-3连接到键合焊盘501-4。支柱504将封装基板470-1的键合焊盘501-2连接到封装基板470-2的键合焊盘501-3。其它类型的连接，诸如焊球，可以用来代替支柱504。
使用上述x64(或x72)配置的方法，DIMM封装可以根据未来的PC DRAM需求被一起排除。随着该行业进入PC应用的DDR4速度，这将是极重要的。上述方法的另一个主要优点是，DRAM叠层中仅有单个DRAM在正常操作期间起作用，因为每个DRAM可以提供所有64个信号引脚。此外，只要考虑连接到主CPU(SOC454中)，地址和命令引脚(C/A引脚)被有效地点对点连接，因而允许C/A引脚在高得多的时钟频率运行。C/A引脚还可以具有片载终端，用于叠层中的至少一个DRAM(例如，在叠层的顶部)，以允许非常高速的操作。这将显著减少功率耗散。最后，尽管整个DRAM需要被冷却用于PC应用(以非常高的速度)，DRAM的仅单个叠层需要用单个热沉510冷却，因而也降低了热沉的成本。
以上公开的IC封装可以在各种计算设备中使用，其包括但不限于智能电话、平板电脑、膝上型电脑、个人计算机、电视、和装备盒。
上述描述仅仅是说明性的，而决不是旨在限制本公开、其应用或用途。本公开的广泛教导可以以多种形式来实现。因此，虽然本公开包括特定示例，但是本公开的真实范围不应如此限制，因为在研究了附图、说明书和权利要求之后，其它修改将变得显而易见。为了清楚起见，在附图中使用相同的附图标记来标识类似的元件。如这里所使用的，用语A、B和C中的至少一个应该被理解为逻辑(A或B或C)，使用非排他性的逻辑“或”。应当理解，方法中的一个或多个步骤可以以不同顺序(或同时)执行，而不改变本公开的原理。
权利要求书(按照条约第19条的修改)
1.一种集成电路封装，包括：
第一存储器裸片，具有第一组连接件；
第二存储器裸片，被设置成邻近所述第一存储器裸片，所述第二存储器裸片具有第二组连接件；
第一基板，具有第一开口和第二开口，所述第一基板具有第三组连接件和第四组连接件，所述第三组连接件经由所述第一开口连接到所述第一存储器裸片的所述第一组连接件，所述第四组连接件经由所述第二开口连接到所述第二存储器裸片的所述第二组连接件；以及
第二基板，具有设置在其上的第一集成电路；
其中使用焊球将所述第一基板连接到所述第二基板，所述第一集成电路设置在所述第一基板和所述第二基板之间。
2.根据权利要求1所述的集成电路封装，其中所述第三组连接件和所述第四组连接件中的每组连接件被布置成间距为小于或等于0.4毫米的三排。
3.根据权利要求1所述的集成电路封装，其中所述第一集成电路是片上系统。
4.根据权利要求1所述的集成电路封装，其中所述第一存储器裸片和所述第二存储器裸片被设置在所述第一基板的顶部上。
5.根据权利要求1所述的集成电路封装，其中所述第一基板被设置在所述第二基板的顶部上。
6.根据权利要求1所述的集成电路封装，还包括热沉，所述热沉设置在所述第一存储器裸片和所述第二存储器裸片的顶部上。
7.根据权利要求1所述的集成电路封装，其中所述第三组连接件通过键合引线被连接到所述第一组连接件；并且其中所述第二组连接件通过键合引线被连接到所述第四组连接件。
8.根据权利要求1所述的集成电路封装，其中所述集成电路封装被配置为连接到印刷电路板上的连接件或第二集成电路的连接件。
9.根据权利要求1所述的集成电路封装，其中所述第一存储器裸片和所述第二存储器裸片是动态随机存取存储器(DRAM)。
10.根据权利要求9所述的集成电路封装，其中所述DRAM是双倍数据速率DRAM。
11.一种计算设备，包括权利要求1所述的集成电路封装，其中所述计算设备包括智能电话、平板电脑、膝上型电脑、个人计算机、电视、或机顶盒。
12.一种集成电路封装，包括：
第一存储器裸片，具有第一组连接件；
第二存储器裸片，被设置成邻近所述第一存储器裸片，所述第二存储器裸片具有第二组连接件；
第一基板，具有第一开口和第二开口，所述第一基板具有第三组连接件和第四组连接件，所述第三组连接件经由所述第一开口连接到所述第一存储器裸片的所述第一组连接件，所述第四组连接件经由所述第二开口连接到所述第二存储器裸片的所述第二组连接件；以及
第二基板，具有设置在其上的第一集成电路；
其中所述第一基板连接到所述第二基板，所述第一集成电路设置在所述第一基板和所述第二基板之间；
第三存储器裸片，具有第五组连接件；
第四存储器裸片，被布置成邻近所述第三存储器裸片，所述第四存储器裸片具有第六组连接件；以及
第三基板，具有第三开口和第四开口，所述第三基板具有第七组连接件和第八组连接件，所述第七组连接件经由所述第三开口连接到所述第三存储器裸片的所述第五组连接件，所述第八组连接件经由所述第四开口连接到所述第四存储器裸片的所述第六组连接件。
13.根据权利要求12所述的集成电路封装，其中所述第三基板设置在所述第一基板的顶部上；并且其中所述第一存储器裸片和所述第二存储器裸片被设置在所述第一基板和所述第三基板之间。
14.根据权利要求13所述的集成电路封装，还包括多个支柱；其中所述多个支柱用来将所述第三基板固定在所述第一基板的顶部上，并在所述第一基板和所述第三基板之间提供连接。
15.根据权利要求12所述的集成电路封装，其中所述第三存储器裸片和所述第四存储器裸片设置在所述第三基板的顶部上。
16.一种集成电路封装，包括：
第一存储器裸片，具有第一组连接件；
第二存储器裸片，被设置成邻近所述第一存储器裸片，所述第二存储器裸片具有第二组连接件；
第一基板，具有第一开口和第二开口，其中所述第一存储器裸片和所述第二存储器裸片被安装在所述第一基板的第一表面上，其中所述第一表面具有第三组连接件和第四组连接件，所述第三组连接件经由所述第一开口连接到所述第一存储器裸片的所述第一组连接件，所述第四组连接件经由所述第二开口连接到所述第二存储器裸片的所述第二组连接件，其中所述第三组连接件和所述第四组连接件位于所述第一基板的第二表面上，并且其中所述第二表面与所述第一表面相反；以及
第二基板，具有设置在所述第二基板的第三表面上的第一集成电路，其中所述第三表面相邻于所述第二表面；
其中所述第一基板连接到所述第二基板，所述第一集成电路设置在所述第一基板和所述第二基板之间。

Claims (15)

1.一种集成电路封装，包括：
第一存储器裸片，具有第一组连接件；
第二存储器裸片，被设置成邻近所述第一存储器裸片，所述第二存储器裸片具有第二组连接件；
第一基板，具有第一开口和第二开口，所述第一基板具有第三组连接件和第四组连接件，所述第三组连接件经由所述第一开口连接到所述第一存储器裸片的所述第一组连接件，所述第四组连接件经由所述第二开口连接到所述第二存储器裸片的所述第二组连接件；以及
第二基板，具有设置在其上的第一集成电路；
其中所述第一基板连接到所述第二基板，所述第一集成电路设置在所述第一基板和所述第二基板之间。
2.根据权利要求1所述的集成电路封装，其中所述第三组连接件和所述第四组连接件中的每组连接件被布置成间距为小于或等于0.4毫米的三排。
3.根据权利要求1所述的集成电路封装，其中所述第一集成电路是片上系统。
4.根据权利要求1所述的集成电路封装，其中所述第一存储器裸片和所述第二存储器裸片被设置在所述第一基板的顶部上。
5.根据权利要求1所述的集成电路封装，其中所述第一基板被设置在所述第二基板的顶部上。
6.根据权利要求1所述的集成电路封装，还包括热沉，所述热沉设置在所述第一存储器裸片和所述第二存储器裸片的顶部上。
7.根据权利要求1所述的集成电路封装，其中所述第三组连接件通过键合引线被连接到所述第一组连接件；并且其中所述第二组连接件通过键合引线被连接到所述第四组连接件。
8.根据权利要求1所述的集成电路封装，其中所述集成电路封装被配置为连接到印刷电路板上的连接件或第二集成电路的连接件。
9.根据权利要求1所述的集成电路封装，其中所述第一存储器裸片和所述第二存储器裸片是动态随机存取存储器(DRAM)。
10.根据权利要求9所述的集成电路封装，其中所述DRAM是双倍数据速率DRAM。
11.一种计算设备，包括权利要求1所述的集成电路封装，其中所述计算设备包括智能电话、平板电脑、膝上型电脑、个人计算机、电视、或机顶盒。
12.根据权利要求1所述的集成电路封装，还包括：
第三存储器裸片，具有第五组连接件；
第四存储器裸片，被布置成邻近所述第三存储器裸片，所述第四存储器裸片具有第六组连接件；
第三基板，具有第三开口和第四开口，所述第三基板具有第七组连接件和第八组连接件，所述第七组连接件经由所述第三开口连接到所述第三存储器裸片的所述第五组连接件，所述第八组连接件经由所述第四开口连接到所述第四存储器裸片的所述第六组连接件。
13.根据权利要求12所述的集成电路封装，其中所述第三基板设置在所述第一基板的顶部上；并且其中所述第一存储器裸片和所述第二存储器裸片被设置在所述第一基板和所述第三基板之间。
14.根据权利要求13所述的集成电路封装，还包括多个支柱；其中所述多个支柱用来将所述第三基板固定在所述第一基板的顶部上，并在所述第一基板和所述第三基板之间提供连接。
15.根据权利要求12所述的集成电路封装，其中所述第三存储器裸片和所述第四存储器裸片设置在所述第三基板的顶部上。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106910722A (zh) * 2015-12-23 2017-06-30 三星电子株式会社 系统模块和包括该系统模块的移动计算装置
CN109472099A (zh) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 一种服务器的印刷电路板及制作方法
CN110783295A (zh) * 2018-07-24 2020-02-11 三星电子株式会社 半导体封装件安装板

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011044289A1 (en) * 2009-10-07 2011-04-14 Rain Bird Corporation Volumetric budget based irrigation control
US8597986B2 (en) * 2011-09-01 2013-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. System in package and method of fabricating same
US10163877B2 (en) * 2011-11-07 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
KR20130071884A (ko) * 2011-12-21 2013-07-01 삼성전자주식회사 다이 패키지 및 이를 포함하는 시스템
KR20140067727A (ko) * 2012-11-27 2014-06-05 삼성전자주식회사 멀티칩 패키지 및 이의 제조 방법
KR102107147B1 (ko) * 2013-02-01 2020-05-26 삼성전자주식회사 패키지 온 패키지 장치
US9087765B2 (en) * 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
KR20140130921A (ko) * 2013-05-02 2014-11-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102127772B1 (ko) * 2013-05-16 2020-06-29 삼성전자주식회사 방열 판을 갖는 반도체 패키지 및 그 형성 방법
WO2014188632A1 (ja) * 2013-05-23 2014-11-27 パナソニック株式会社 放熱構造を有する半導体装置および半導体装置の積層体
KR102144367B1 (ko) * 2013-10-22 2020-08-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9379078B2 (en) * 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
JP2015216263A (ja) * 2014-05-12 2015-12-03 マイクロン テクノロジー， インク． 半導体装置
TWI690029B (zh) * 2014-06-13 2020-04-01 蘋果公司 重組態之寬輸入輸出記憶體模組及使用其之封裝架構
US20160013156A1 (en) * 2014-07-14 2016-01-14 Apple Inc. Package-on-package options with multiple layer 3-d stacking
WO2016130859A1 (en) * 2015-02-11 2016-08-18 Endura Technologies LLC Switched power stage with integrated passive components
US10360972B2 (en) * 2015-03-10 2019-07-23 Rambus Inc. Memories and memory components with interconnected and redundant data interfaces
JP6305961B2 (ja) * 2015-08-04 2018-04-04 オートモーティブエナジーサプライ株式会社 リチウムイオン二次電池
KR102413441B1 (ko) 2015-11-12 2022-06-28 삼성전자주식회사 반도체 패키지
US10492299B2 (en) * 2015-11-13 2019-11-26 Intel Corporation Electronic assembly that includes a substrate bridge
US10411001B2 (en) 2015-12-16 2019-09-10 Intel Corporation Dynamic random access memory (DRAM) mounts
KR102533236B1 (ko) 2016-06-20 2023-05-17 삼성전자주식회사 개선된 레이턴시를 갖는 메모리 장치 및 그것의 동작 방법
KR102547800B1 (ko) * 2016-08-23 2023-06-26 삼성전자주식회사 그래핀 퀀텀닷을 이용한 방열 구조체 및 그 제조방법
JP6733534B2 (ja) * 2016-12-16 2020-08-05 住友電気工業株式会社 半導体装置およびその製造方法
KR20180130043A (ko) * 2017-05-25 2018-12-06 에스케이하이닉스 주식회사 칩 스택들을 가지는 반도체 패키지
US10153221B1 (en) * 2017-06-13 2018-12-11 Micron Technology, Inc. Face down dual sided chip scale memory package
US11171115B2 (en) 2019-03-18 2021-11-09 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
US11152343B1 (en) 2019-05-31 2021-10-19 Kepler Computing, Inc. 3D integrated ultra high-bandwidth multi-stacked memory
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
KR102600154B1 (ko) * 2019-06-12 2023-11-07 삼성전자주식회사 반도체 패키지
JP7245131B2 (ja) 2019-07-16 2023-03-23 株式会社日本クライメイトシステムズ 車両用蓄熱システム
US11348856B2 (en) * 2019-12-20 2022-05-31 Micron Technology, Inc. Thermal cooling element for memory devices of a memory sub-system
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
KR102462798B1 (ko) 2022-02-07 2022-11-03 최해용 공간 보면대 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060110849A1 (en) * 2004-10-28 2006-05-25 Cheng-Yin Lee Method for stacking BGA packages and structure from the same
US7061092B2 (en) * 1999-02-01 2006-06-13 Micron Technology, Inc. High-density modularity for ICS
KR20060120365A (ko) * 2005-05-19 2006-11-27 삼성테크윈 주식회사 반도체 칩 적층 패키지
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
US20110063805A1 (en) * 2007-08-31 2011-03-17 Samsung Electronics Co., Ltd. Stack-type semiconductor package, method of forming the same and electronic system including the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049129A (en) 1997-12-19 2000-04-11 Texas Instruments Incorporated Chip size integrated circuit package
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6825550B2 (en) 1999-09-02 2004-11-30 Micron Technology, Inc. Board-on-chip packages with conductive foil on the chip surface
KR20010064907A (ko) 1999-12-20 2001-07-11 마이클 디. 오브라이언 와이어본딩 방법 및 이를 이용한 반도체패키지
US6414396B1 (en) * 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
JP3867796B2 (ja) * 2003-10-09 2007-01-10 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7061121B2 (en) * 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
US7851899B2 (en) 2004-04-02 2010-12-14 Utac - United Test And Assembly Test Center Ltd. Multi-chip ball grid array package and method of manufacture
US7678610B2 (en) 2004-10-28 2010-03-16 UTAC-United Test and Assembly Test Center Ltd. Semiconductor chip package and method of manufacture
US7368319B2 (en) 2006-03-17 2008-05-06 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
SG136822A1 (en) 2006-04-19 2007-11-29 Micron Technology Inc Integrated circuit devices with stacked package interposers
US7535110B2 (en) 2006-06-15 2009-05-19 Marvell World Trade Ltd. Stack die packages
US7518226B2 (en) 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
US7816154B2 (en) * 2007-06-06 2010-10-19 Renesas Electronics Corporation Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same
JP4829853B2 (ja) * 2007-08-24 2011-12-07 力成科技股▲分▼有限公司 半導体ｐｏｐ装置
KR20090043898A (ko) 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
KR20090050810A (ko) * 2007-11-16 2009-05-20 삼성전자주식회사 접합 신뢰성이 향상된 적층형 반도체 패키지
US8247894B2 (en) * 2008-03-24 2012-08-21 Stats Chippac Ltd. Integrated circuit package system with step mold recess
US8354742B2 (en) * 2008-03-31 2013-01-15 Stats Chippac, Ltd. Method and apparatus for a package having multiple stacked die
US8253231B2 (en) 2008-09-23 2012-08-28 Marvell International Ltd. Stacked integrated circuit package using a window substrate
KR101601847B1 (ko) * 2009-05-21 2016-03-09 삼성전자주식회사 반도체 패키지
KR20120007839A (ko) * 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
KR101118711B1 (ko) * 2010-12-17 2012-03-12 테세라, 인코포레이티드 중앙 콘택을 구비한 적층형 마이크로전자 조립체

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061092B2 (en) * 1999-02-01 2006-06-13 Micron Technology, Inc. High-density modularity for ICS
US20060110849A1 (en) * 2004-10-28 2006-05-25 Cheng-Yin Lee Method for stacking BGA packages and structure from the same
KR20060120365A (ko) * 2005-05-19 2006-11-27 삼성테크윈 주식회사 반도체 칩 적층 패키지
US20070241441A1 (en) * 2006-04-17 2007-10-18 Stats Chippac Ltd. Multichip package system
US20110063805A1 (en) * 2007-08-31 2011-03-17 Samsung Electronics Co., Ltd. Stack-type semiconductor package, method of forming the same and electronic system including the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106910722A (zh) * 2015-12-23 2017-06-30 三星电子株式会社 系统模块和包括该系统模块的移动计算装置
CN106910722B (zh) * 2015-12-23 2020-10-09 三星电子株式会社 系统模块和包括该系统模块的移动计算装置
CN110783295A (zh) * 2018-07-24 2020-02-11 三星电子株式会社 半导体封装件安装板
CN109472099A (zh) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 一种服务器的印刷电路板及制作方法

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