CN107305890B - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN107305890B
CN107305890B CN201610600640.5A CN201610600640A CN107305890B CN 107305890 B CN107305890 B CN 107305890B CN 201610600640 A CN201610600640 A CN 201610600640A CN 107305890 B CN107305890 B CN 107305890B
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crystal grain
logic
semiconductor packages
bridge formation
logic crystal
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CN107305890A (zh
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施信益
吴铁将
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明公开了一种半导体封装，包含一第一逻辑晶粒；一第二逻辑晶粒，邻近第一逻辑晶粒而设置；一架桥存储器晶粒，耦接到第一逻辑晶粒与第二逻辑晶粒；一重布层(RDL)结构，耦合第一逻辑晶粒与第二逻辑晶粒；以及一模塑料，至少部分包覆第一逻辑晶粒、第二逻辑晶粒及架桥存储器晶粒。第一逻辑晶粒与第二逻辑晶粒位于共平面。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种将多个逻辑晶粒(logic die)及双埠随机存取存储器(dual-port RAM)整合在单一封装的半导体封装及其制造方法。
背景技术
双埠随机存取存储器(dual-port RAM)是本领域公知的。双埠随机存取存储器可以同时在不同地址读取并写入不同的存储胞(memory cell)。双埠随机存取存储器和单埠随机存取存储器(single-port RAM)的主要区别在于，单埠随机存取存储器一次只能存取单一地址。因此，单埠随机存取存储器各时钟周期(clock cycle)只允许读取或写入一个存储单元。
视频RAM(Video RAM)，又称为VRAM，是一种双端口动态随机存取存储器(dual-port DRAM)，主要用于视频存储器。VRAM允许计算机的中央处理器(CPU)，在视频硬件读取图像到屏幕的同时又能绘制图像。其它类型的双埠随机存取存储器则以静态随机存取存储器(SRAM)为基础。计算机的CPU其处理器缓存器(processor register)多为一双埠或多埠(multi-ported)随机存取存储器。
图1例示现有的存储器系统100，其包含一电路板101、安装在电路板101上的一双埠随机存取存储器120，及安装在双埠随机存取存储器120两个相对侧的电路板101上的两个处理器140及160。两个处理器140及160是透过电路板101上的存储器总线(memory bus)110与双埠随机存取存储器120信号连通。本技术领域中，仍希望能进一步改进处理器140和160与双埠随机存取存储器120之间的数据传输速度。
发明内容
本发明的主要目的在提供一种改良的半导体封装及其制造方法，其能够将多个逻辑晶粒(logic die)及双埠随机存取存储器(dual-port RAM)整合在单一封装。
本发明一实施例披露一种半导体封装，包含一第一逻辑晶粒；一第二逻辑晶粒，邻近第一逻辑晶粒而设置；一架桥存储器晶粒，耦接至第一逻辑晶粒与第二逻辑晶粒；一重布层(RDL)结构，耦合第一逻辑晶粒与第二逻辑晶粒；以及一模塑料，至少部分包覆第一逻辑晶粒、第二逻辑晶粒及架桥存储器晶粒。
根据本发明一实施例，第一逻辑晶粒与第二逻辑晶粒位于共平面。架桥存储器晶粒是以面对面覆晶组态与第一逻辑晶粒与第二逻辑晶粒电连接。
根据本发明一实施例，架桥存储器晶粒是一双埠随机存取存储器(dual-portRAM)。例如，架桥存储器晶粒是一双端口动态随机存取存储器(dual-port DRAM)。
根据本发明一实施例，第一逻辑晶粒包含中央处理器单元、绘图处理器单元或应用处理器。第二逻辑晶粒包含中央处理器单元、绘图处理器单元或应用处理器。
根据本发明一实施例，架桥存储器晶粒容许第一逻辑晶粒与第二逻辑晶粒之间的处理器间信号传递。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
附图提供对于此实施例更深入的了解，并纳入此说明书成为其中一部分。这些附图与描述，用来说明一些实施例的原理。
图1例示现有的存储器系统。
图2至图6为依据本发明一实施例所绘示的制造半导体封装的方法剖面示意图。
图7为依据本发明另一实施例所绘示的半导体封装的剖面示意图。
图8至图12为依据本发明又另一实施例所绘示的制造半导体封装的方法剖面示意图。
图13为依据本发明又另一实施例所绘示的半导体封装的剖面示意图。
其中，附图标记说明如下：
1、2、3、4 半导体封装
10 载板
11、12 逻辑晶粒
11a、12a、13a 有源面
13b 非有源面
13 架桥存储器晶粒
20 模塑料
30 重布层(RDL)结构
40 焊锡凸块或锡球
60 上层重布层结构
111、112、121、122、131 输出/输入(I/O)垫
113、123、133 连接件
116、126、132 穿板通孔
202 穿模通孔
301、601 介电层
302、602 金属层
302a 焊接垫
303 防焊层
303a 防焊开孔
304 钝化层
100 存储器系统
101 电路板
110 存储器总线
120 双埠随机存取存储器
140、160 处理器
具体实施方式
接下来的详细叙述是参照相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，仍可做结构上的等效修改，并延伸应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求来界定。与本发明权利要求所述各组件或限制具均等意义的，也应属本发明涵盖的范围。
本发明实施例所参照的附图为示意图，并未按原比例绘制，且相同或类似的特征通常以相同的附图标记描述。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“衬底”意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制造集成电路结构的结构物，例如重布层(RDL)。须了解的是“衬底”包含半导体晶圆，但并不限于此。"衬底"在工艺中也意指包含制造在其上的材料层的半导体结构物。
本发明披露一种多处理器半导体封装，将至少两个逻辑晶粒(logic die)及一架桥存储器晶粒(bridge memory die)整合在单一的封装体中。所述架桥存储器晶粒可以是一双端口动态随机存取存储器(dual-port DRAM)，而所述逻辑晶粒同时对所述架桥存储器晶粒内的存储单元进行寻址及存取。相较于先前技艺，存储器晶粒与逻辑晶粒之间的信号传递距离缩短，故存储器操作速率(memory operating speed)及信号完整性(signalintegrity)可以获得改善。
请参阅图2至图6，是依据本发明一实施例所绘示的制造半导体封装的方法剖面示意图。首先，如图2所示，提供一载板10。载板10可以是一可卸式衬底材料，适合用于承载支撑一薄型衬底或晶圆。例如，载板10可以包含硅、玻璃或金属，但不限于此。接着，将逻辑晶粒11及逻辑晶粒12贴合至载板10一上表面，使逻辑晶粒11及12的有源面11a及12a面朝上。其中，逻辑晶粒11是邻近逻辑晶粒12而设置，且逻辑晶粒11与逻辑晶粒12位于共平面。
根据本发明实施例，例如，逻辑晶粒11及逻辑晶粒12可以包含中央处理器单元(central processing units，CPU)、绘图处理器单元(graphics processing units，GPU)或应用处理器(application processor)，但不限于此。逻辑晶粒11及逻辑晶粒12也可以是，例如，系统单芯片(system on a chip，SoC)，但不限于此。
在逻辑晶粒11的有源面11a上，提供多个输出/输入(input/output，I/O)垫111及112，其中，I/O垫112被设置在逻辑晶粒11接近逻辑晶粒12的一边缘上。I/O垫111上则分别形成有连接件113，例如金属凸块或金属柱。根据本发明实施例，连接件113可以包含铜、铝、金等等，但不限于此。同样的，在逻辑晶粒12的有源面12a上，提供多个输出/输入(I/O)垫121及122，其中，I/O垫122被设置在逻辑晶粒12接近逻辑晶粒11的一边缘上。I/O垫121上则分别形成有连接件123，例如金属凸块或金属柱。根据本发明实施例，连接件123可以包含铜、铝、金等等，但不限于此。
如图3所示，接着将架桥存储器晶粒(bridge memory die)13耦接到逻辑晶粒11及逻辑晶粒12上。架桥存储器晶粒13是透过连接件133，例如微凸块(micro bump)、焊锡凸块、金属凸块或金属柱，安置固定在相应的I/O垫112及122上。根据本发明实施例，架桥存储器晶粒13可以是一覆晶存储器晶粒(flip chip memory die)。架桥存储器晶粒13的有源面13a是面朝向逻辑晶粒11及逻辑晶粒12，以面对面覆晶组态(face-to-faceconfiguration)与逻辑晶粒11与逻辑晶粒12电连接。架桥存储器晶粒13的有源面13a上提供多个I/O垫131。架桥存储器晶粒13的非有源面13b(在此图中为相对于有源面13a的架桥存储器晶粒13的上表面)是大致与连接件123的上表面齐平或共平面。
根据本发明实施例，架桥存储器晶粒13可以是一双埠随机存取存储器(dual-portRAM)，例如一双端口动态随机存取存储器(dual-port DRAM)，但不限于此。根据本发明实施例，架桥存储器晶粒13容许逻辑晶粒11与逻辑晶粒12之间的数据交换或任何的处理器间信号传递(inter-processor communication)。双端口动态随机存取存储器，其提供一个额外的输入/输出端口给存储器数组，故具有优于传统DRAM的速度优势。在传统的DRAM，由于通过单一的随机存取埠，故读取及写入两种操作无法同时进行。在双端口动态随机存取存储器中，除了随机存取埠，还另提供一第二端口(通常是一串行端口)。在序列移位寄存器(serial shift register)与存储器数组(array)之间，数据可同时被读出及写入。
根据本发明实施例，例如，沿着架桥存储器晶粒13的外围，可以设置穿板通孔(through substrate via)132。穿板通孔132可以利用已知的穿硅通孔(TSV)工艺来制造，其中穿板通孔132至少电连接至部分的I/O垫131。根据本发明实施例，架桥存储器晶粒13可以透过至少部分穿板通孔132与RDL结构中的金属层电连接。例如，电源或接地信号可以借由RDL结构及穿板通孔132提供给架桥存储器晶粒13。
根据本发明实施例，例如，架桥存储器晶粒13可以利用一覆晶接合工艺(flip-chip bonding process)耦合到逻辑晶粒11与逻辑晶粒12上。借由提供这样的面对面覆晶组态，架桥存储器晶粒13可以被设置在接近逻辑晶粒11与逻辑晶粒12的位置。如此一来，存储器晶粒与逻辑晶粒之间的信号传递距离缩短，故存储器操作速率(memory operatingspeed)及信号完整性(signal integrity)可以获得改善。
如图4所示，接着形成一模塑料20，其至少部分包覆逻辑晶粒11、逻辑晶粒12、架桥存储器晶粒13，及连接件113及123。模塑料20可以填入架桥存储器晶粒13与两个逻辑晶粒11、12之间的细缝，并填入两个逻辑晶粒11、12之间的细缝。根据本发明实施例，后续可以对模塑料20进行一固化工艺。
根据本发明实施例，模塑料20例如为高分子聚合物、环氧树脂及/或二氧化硅填充剂的混和物，但并不限于此。根据本发明实施例，可以再对模塑料20进行一抛光工艺，以显露出架桥存储器晶粒13的穿板通孔132的上表面，以及连接件113、123的上表面。
如图5所示，接着形成一重布层(RDL)结构30，使其耦合架桥存储器晶粒13的穿板通孔132及连接件113、123的上表面。RDL结构30可以包含，但不限于，至少一介电层301及至少一金属层302，设于介电层301中。介电层301可包含有机材料，例如，聚亚酰胺(polyimide)，或者无机材料，例如氮化硅、氧化硅等，但不限于此。金属层302可包含铝、铜、钨、钛、氮化钛或类似的材料。上述RDL结构30可以利用本技术领域的已知方法形成。
RDL结构30可以另包含一钝化层或一防焊层303，覆盖RDL结构30的下表面。防焊层303中可以形成有防焊开孔303a，显露出各焊接垫302a。焊锡凸块(例如，C4凸块)或锡球(例如BGA锡球)40被设置在RDL结构30下表面的各个防焊开孔303a中，构成一球格数组(ballgrid array)。虽然未明示在图中，本领域技术人员应理解在形成上述锡球40之前，可以先形成一凸块下金属(UBM)层。
如图6所示，在RDL结构30下表面形成焊锡凸块或锡球40之后，接着将载板10去除。上述去除载板10可以利用激光工艺、紫外线(UV)照射、抛光或蚀刻工艺，但不限于此。最后，对此晶圆级封装进行一晶圆切割工艺，将个别的半导体封装1彼此分离。
根据本发明实施例，半导体封装1包含有两个逻辑晶粒11、12同时耦合到一架桥存储器晶粒13。根据本发明实施例，架桥存储器晶粒13是直接耦合到RDL结构30。架桥存储器晶粒13的非有源面13b是直接接触RDL结构30。根据本发明实施例，架桥存储器晶粒13是透过穿板通孔132与RDL结构30中的金属层302电连接。根据本发明实施例，架桥存储器晶粒13是位在RDL结构30与逻辑晶粒11、12之间。
本发明的优点在于数据或信号可以直接透过架桥存储器晶粒13与逻辑晶粒11、12之间的连接件133传递。架桥存储器晶粒13可以是一双端口动态随机存取存储器(dual-port DRAM)，容许处理器间信号传递。逻辑晶粒11、12可以共享架桥存储器晶粒13，且以较短的路径对架桥存储器晶粒13同时进行存取动作，故能够提升存储器操作速率及改善信号完整性。
图7为依据本发明另一实施例所绘示的半导体封装的剖面示意图，其中相同的层、区域或组件仍沿用相同的符号表示。如图7所示，半导体封装2与图6中的半导体封装1的主要差异在于，半导体封装2的架桥存储器晶粒13中不具有穿板通孔132。因此，架桥存储器晶粒13中的电路并不会直接耦合到RDL结构30。
图8至图12为依据本发明又另一实施例所绘示的制造半导体封装的方法剖面示意图。首先，如图8所示，提供一载板10。载板10可以是一可卸式衬底材料，适合用于承载支撑一薄型衬底或晶圆。例如，载板10可以包含硅、玻璃或金属，但不限于此。
接着，直接在载板10上形成一重布层(RDL)结构30。RDL结构30可以包含，但不限于，至少一介电层301及至少一金属层302，设于介电层301中。介电层301可包含有机材料，例如，聚亚酰胺(polyimide)，或者无机材料，例如氮化硅、氧化硅等，但不限于此。金属层302可包含铝、铜、钨、钛、氮化钛或类似的材料。RDL结构30可以另包含一钝化层或一防焊层303，覆盖RDL结构30的下表面。RDL结构30可以另包含一钝化层304，覆盖RDL结构30的上表面。
如图9所示，接着，将逻辑晶粒11及逻辑晶粒12贴合到载板10上，使逻辑晶粒11及12的有源面11a及12a面朝向RDL结构30。其中，逻辑晶粒11是邻近逻辑晶粒12而设置，且逻辑晶粒11与逻辑晶粒12位于共平面。根据本发明实施例，逻辑晶粒11与逻辑晶粒12为覆晶晶粒。例如，逻辑晶粒11及逻辑晶粒12可以包含中央处理器单元(central processingunits，CPU)、绘图处理器单元(graphics processing units，GPU)或应用处理器(application processor)，但不限于此。逻辑晶粒11及逻辑晶粒12也可以是，例如，系统单芯片(system on a chip，SoC)，但不限于此。逻辑晶粒11可以具有与逻辑晶粒12不相同的功能，例如，逻辑晶粒11可以是CPU，而逻辑晶粒12可以是GPU，但不限于此。
在逻辑晶粒11的有源面11a上，提供多个输出/输入(I/O)垫111。I/O垫111上形成有连接件113，例如微凸块、焊锡凸块、金属凸块或金属柱。根据本发明实施例，连接件113可以包含铜、铝、金等等，但不限于此。同样的，在逻辑晶粒12的有源面12a上，提供有多个输出/输入(I/O)垫121。I/O垫121上形成有连接件123，例如微凸块、焊锡凸块、金属凸块或金属柱。根据本发明实施例，连接件123可以包含铜、铝、金等等，但不限于此。
根据本发明实施例，逻辑晶粒11另包含有多个穿板通孔116，设置在逻辑晶粒11接近逻辑晶粒12的一边缘上。至少部分的穿板通孔116是电连接到至少部分的I/O垫111。逻辑晶粒12另包含有多个穿板通孔126，设置在逻辑晶粒12接近逻辑晶粒11的一边缘上。至少部分的穿板通孔126是电连接到至少部分的I/O垫121。
如图10所示，接着将架桥存储器晶粒(bridge memory die)13耦接到逻辑晶粒11及逻辑晶粒12上。架桥存储器晶粒13是借由连接件133，例如微凸块、焊锡凸块、金属凸块或金属柱，安置固定在相应的穿板通孔116、126上。根据本发明实施例，架桥存储器晶粒13可以是一覆晶存储器晶粒(flip chip memory die)。架桥存储器晶粒13的有源面13a是面朝下，面向逻辑晶粒11及逻辑晶粒12，并透过穿板通孔116、126电连接到逻辑晶粒11及逻辑晶粒12的内部电路。架桥存储器晶粒13的有源面13a上提供多个I/O垫131。
根据本发明实施例，架桥存储器晶粒13可以是一双埠随机存取存储器，例如一双端口动态随机存取存储器，但不限于此。根据本发明实施例，架桥存储器晶粒13容许逻辑晶粒11与逻辑晶粒12之间的数据交换或任何的处理器间信号传递。双端口动态随机存取存储器，其提供一个额外的输入/输出端口给存储器数组，故具有优于传统DRAM的速度优势。在传统的DRAM，由于通过单一的随机存取埠，故读取及写入两种操作无法同时进行。在双端口动态随机存取存储器中，除了随机存取埠，还另提供一第二端口(通常是一串行端口)。在序列移位寄存器与存储器数组之间，数据可同时被读出及写入。
如图11所示，接着形成一模塑料20，其至少部分包覆逻辑晶粒11、逻辑晶粒12、架桥存储器晶粒13，及连接件113、123、133。模塑料20可以填入架桥存储器晶粒13与两个逻辑晶粒11、12之间的细缝，并填入两个逻辑晶粒11、12之间的细缝。根据本发明实施例，后续可以对模塑料20进行一固化工艺。架桥存储器晶粒13的非有源面13b(在此图中为相对于有源面13a的架桥存储器晶粒13的上表面)是大致与模塑料20的上表面齐平或共平面。
如图12所示，在形成模塑料20之后，接着将载板10去除。上述去除载板10可以利用激光工艺、紫外线(UV)照射、抛光或蚀刻工艺，但不限于此。接着在防焊层303中形成防焊开孔303a，显露出各别焊接垫302a。再将焊锡凸块(例如，C4凸块)或锡球(例如BGA锡球)40设置在RDL结构30下表面的各个防焊开孔303a中，构成一球格数组(ball grid array)。虽然未明示在图中，熟习所述项技艺者应理解在形成上述锡球40之前，可以先形成一凸块下金属(UBM)层。最后，对此晶圆级封装进行一晶圆切割工艺，将个别的半导体封装3彼此分离。
根据本发明实施例，半导体封装3包含有两个逻辑晶粒11、12同时耦合到一架桥存储器晶粒13。根据本发明实施例，架桥存储器晶粒13不直接耦合到RDL结构30。架桥存储器晶粒13的非有源面13b不直接接触RDL结构30。根据本发明实施例，架桥存储器晶粒13是透过穿板通孔116、126及连接件133与逻辑晶粒11、12电连接。根据本发明实施例，架桥存储器晶粒13是位在RDL结构30与逻辑晶粒11、12之间。根据本发明实施例，逻辑晶粒11、12是位在RDL结构30与架桥存储器晶粒13之间。
图13为依据本发明又另一实施例所绘示的半导体封装的剖面示意图，其中相同的层、区域或组件仍沿用相同的符号表示。如第13图所示，半导体封装4与图12中的半导体封装3的主要差异在于，半导体封装4的架桥存储器晶粒13另包含有穿板通孔132。半导体封装4另包含有一上层重布层结构60，直接设在架桥存储器晶粒13的非有源面13b上以及模塑料20的上表面。所述上层重布层结构60包含至少一介电层601以及至少一金属层602，位在介电层601中。半导体封装4另包含有一穿模通孔(through mold via)202，其电连接到上层重布层结构60的金属层602。因此，架桥存储器晶粒13内的电路是透过上层重布层结构60与穿模通孔202耦合到RDL结构30。
本发明的优点在于数据或信号可以直接透过架桥存储器晶粒13与逻辑晶粒11、12之间的连接件133传递。架桥存储器晶粒13可以是一双端口动态随机存取存储器(dual-port DRAM)，容许处理器间信号传递。逻辑晶粒11、12可以共享架桥存储器晶粒13，且以较短的路径对架桥存储器晶粒13同时进行存取动作，故能够提升存储器操作速率及改善信号完整性。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种半导体封装，其包含：
第一逻辑晶粒；
第二逻辑晶粒，其横向邻近所述第一逻辑晶粒而设置，所述第一逻辑晶粒的第一有源面和所述第二逻辑晶粒的第二有源面面向同一方向；
架桥存储器晶粒，其在与所述第一有源面和所述第二有源面相对的所述第一逻辑晶粒的第一非有源面和所述第二逻辑晶粒的第二非有源面上耦接到所述第一逻辑晶粒与所述第二逻辑晶粒两者；
重布层RDL结构，其耦合所述第一逻辑晶粒与所述第二逻辑晶粒，其中所述架桥存储器晶粒通过延伸穿过所述架桥存储器晶粒的多个穿板通孔电耦合至所述RDL结构；以及
模塑料，其至少部分包覆所述第一逻辑晶粒、所述第二逻辑晶粒及所述架桥存储器晶粒。
2.根据权利要求1所述的半导体封装，其中所述第一逻辑晶粒的所述第一有源面与所述第二逻辑晶粒的所述第二有源面共平面。
3.根据权利要求1所述的半导体封装，其中所述架桥存储器晶粒是以面对面覆晶组态电耦合至所述第一逻辑晶粒与所述第二逻辑晶粒，以使得所述架桥存储器晶粒的有源表面面向所述第一非有源面和所述第二非有源面。
4.根据权利要求1所述的半导体封装，其中所述架桥存储器晶粒是双埠随机存取存储器。
5.根据权利要求1所述的半导体封装，其中所述架桥存储器晶粒是双端口动态随机存取存储器。
6.根据权利要求1所述的半导体封装，其中所述第一逻辑晶粒包含中央处理器单元、绘图处理器单元或应用处理器。
7.根据权利要求1所述的半导体封装，其中所述第二逻辑晶粒包含中央处理器单元、绘图处理器单元或应用处理器。
8.根据权利要求1所述的半导体封装，其中所述架桥存储器晶粒容许所述第一逻辑晶粒与所述第二逻辑晶粒之间的处理器间通信。
9.根据权利要求1所述的半导体封装，其中所述第一逻辑晶粒是经由多个第一连接件与所述RDL结构电连接。
10.根据权利要求9所述的半导体封装，其中所述第二逻辑晶粒是经由多个第二连接件与所述RDL结构电连接。
11.根据权利要求10所述的半导体封装，其中所述架桥存储器晶粒是经由多个第三连接件与所述第一逻辑晶粒与所述第二逻辑晶粒电连接。
12.根据权利要求11所述的半导体封装，其中所述第一连接件、所述第二连接件与所述第三连接件包含金属凸块或金属柱。
13.根据权利要求1所述的半导体封装，其中所述架桥存储器晶粒是介于所述RDL结构与所述第一逻辑晶粒和所述第二逻辑晶粒之间的。
14.根据权利要求13所述的半导体封装，其中所述架桥存储器晶粒的非有源面是直接接触所述RDL结构的。
15.根据权利要求1所述的半导体封装，其进一步包含安装在所述RDL结构的下表面上的多个焊锡凸块或锡球。
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