TW201739030A - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

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Publication number
TW201739030A
TW201739030A TW105116593A TW105116593A TW201739030A TW 201739030 A TW201739030 A TW 201739030A TW 105116593 A TW105116593 A TW 105116593A TW 105116593 A TW105116593 A TW 105116593A TW 201739030 A TW201739030 A TW 201739030A
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Taiwan
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die
logic die
semiconductor package
logic
bridge memory
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TW105116593A
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TWI599012B (zh
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施信益
吳鐵將
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美光科技公司
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    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract

一種半導體封裝，包含一第一邏輯晶粒；一第二邏輯晶粒，鄰近該第一邏輯晶粒而設置；一架橋記憶體晶粒，耦接至該第一邏輯晶粒與該第二邏輯晶粒；一重佈線層（RDL）結構，耦合該第一邏輯晶粒與該第二邏輯晶粒；以及一成型模料，至少部分包覆該第一邏輯晶粒、該第二邏輯晶粒及該架橋記憶體晶粒。該第一邏輯晶粒與該第二邏輯晶粒位於共平面。

Description

半導體封裝及其製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種將多個邏輯晶粒（logic die）及雙埠隨機存取記憶體（dual-port RAM）整合於單一封裝的半導體封裝及其製作方法。
雙埠隨機存取記憶體（dual-port RAM）是本領域公知的。雙埠隨機存取記憶體可以同時於不同位址讀取並寫入不同的記憶胞（memory cell）。雙埠隨機存取記憶體和單埠隨機存取記憶體（single-port RAM）的主要區別在於，單埠隨機存取記憶體一次只能存取單一地址。因此，單埠隨機存取記憶體各時脈週期（clock cycle）只允許讀取或寫入一個記憶胞。
視頻RAM（Video RAM），又稱為VRAM，是一種雙埠動態隨機存取記憶體（dual-port DRAM），主要用於視頻記憶體。VRAM允許電腦的中央處理器（CPU），在視頻硬體讀取圖像到螢幕的同時又能繪製圖像。其它類型的雙埠隨機存取記憶體則以靜態隨機存取記憶體（SRAM）為基礎。電腦的CPU其處理器暫存器（processor register）多為一雙埠或多埠（multi-ported）隨機存取記憶體。
第1圖例示習知的記憶體系統100，其包含一電路板101、安裝在電路板101上的一雙埠隨機存取記憶體120，及安裝在雙埠隨機存取記憶體120兩個相對側的電路板101上的兩個處理器140及160。兩個處理器140及160係透過電路板101上的記憶體匯流排（memory bus）110與雙埠隨機存取記憶體120訊號連通。該技術領域中，仍希望能進一步改進處理器140和160與雙埠隨機存取記憶體120之間的數據傳輸速度。
本發明一主要目的在提供一種改良的半導體封裝及其製作方法，其能夠將多個邏輯晶粒（logic die）及雙埠隨機存取記憶體（dual-port RAM）整合於單一封裝。
本發明一實施例披露一種半導體封裝，包含一第一邏輯晶粒；一第二邏輯晶粒，鄰近該第一邏輯晶粒而設置；一架橋記憶體晶粒，耦接至該第一邏輯晶粒與該第二邏輯晶粒；一重佈線層（RDL）結構，耦合該第一邏輯晶粒與該第二邏輯晶粒；以及一成型模料，至少部分包覆該第一邏輯晶粒、該第二邏輯晶粒及該架橋記憶體晶粒。
根據本發明一實施例，該第一邏輯晶粒與該第二邏輯晶粒位於共平面。該架橋記憶體晶粒係以面對面覆晶組態與該第一邏輯晶粒與該第二邏輯晶粒電連接。
根據本發明一實施例，該架橋記憶體晶粒係為一雙埠隨機存取記憶體（dual-port RAM）。例如，該架橋記憶體晶粒係為一雙埠動態隨機存取記憶體（dual-port DRAM）。
根據本發明一實施例，該第一邏輯晶粒包含中央處理器單元、繪圖處理器單元或應用處理器。該第二邏輯晶粒包含中央處理器單元、繪圖處理器單元或應用處理器。
根據本發明一實施例，該架橋記憶體晶粒容許該第一邏輯晶粒與該第二邏輯晶粒之間的處理器間訊號傳遞。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
接下來的詳細敘述係參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例已提供足夠的細節，可使本領域技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可做結構上的等效修改，並延伸應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求來界定。與本發明權利要求所述個元件或限制具均等意義者，也應屬本發明涵蓋的範圍。
本發明實施例所參照的附圖為示意圖，並未按原比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層（RDL）。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
本發明披露一種多處理器半導體封裝，將至少兩個邏輯晶粒（logic die）及一架橋記憶體晶粒（bridge memory die）整合於單一的封裝體中。所述架橋記憶體晶粒可以是一雙埠動態隨機存取記憶體（dual-port DRAM），而所述邏輯晶粒同時對該架橋記憶體晶粒內的記憶胞進行定址及存取。相較於先前技藝，記憶體晶粒與邏輯晶粒之間的訊號傳遞距離縮短，故記憶體操作速率（memory operating speed）及訊號完整性（signal integrity）可以獲得改善。
請參閱第2圖至第6圖，其為依據本發明一實施例所繪示的製作半導體封裝的方法剖面示意圖。首先，如第2圖所示，提供一載板10。載板10可以是一可卸式基板材料，適合用於承載支撐一薄型基板或晶圓。例如，載板10可以包含矽、玻璃或金屬，但不限於此。接著，將邏輯晶粒11及邏輯晶粒12貼合至載板10一上表面，使邏輯晶粒11及12的主動面11a及12a面朝上。其中，邏輯晶粒11係鄰近邏輯晶粒12而設置，且邏輯晶粒11與邏輯晶粒12位於共平面。
根據本發明實施例，例如，邏輯晶粒11及邏輯晶粒12可以包含中央處理器單元（central processing units，CPU）、繪圖處理器單元（graphics processing units，GPU）或應用處理器（application processor），但不限於此。邏輯晶粒11及邏輯晶粒12也可以是，例如，系統單晶片（system on a chip，SoC），但不限於此。
在邏輯晶粒11的主動面11a上，提供有複數個輸出/輸入（input/output，I/O）墊111及112，其中，I/O墊112被設置在邏輯晶粒11接近邏輯晶粒12的一邊緣上。I/O墊111上則分別形成有連接件113，例如金屬凸塊或金屬柱。根據本發明實施例，連接件113可以包含銅、鋁、金等等，但不限於此。同樣的，在邏輯晶粒12的主動面12a上，提供有複數個輸出/輸入（I/O）墊121及122，其中，I/O墊122被設置在邏輯晶粒12接近邏輯晶粒11的一邊緣上。I/O墊121上則分別形成有連接件123，例如金屬凸塊或金屬柱。根據本發明實施例，連接件123可以包含銅、鋁、金等等，但不限於此。
如第3圖所示，接著將架橋記憶體晶粒（bridge memory die）13耦接至邏輯晶粒11及邏輯晶粒12上。架橋記憶體晶粒13係透過連接件133，例如微凸塊（micro bump）、焊錫凸塊、金屬凸塊或金屬柱，安置固定於相應的I/O墊112及122上。根據本發明實施例，架橋記憶體晶粒13可以是一覆晶記憶體晶粒（flip chip memory die）。架橋記憶體晶粒13的主動面13a係面朝向邏輯晶粒11及邏輯晶粒12，以面對面覆晶組態（face-to-face configuration）與邏輯晶粒11與邏輯晶粒12電連接。架橋記憶體晶粒13的主動面13a上提供有複數個I/O墊131。架橋記憶體晶粒13的非主動面13b（在此圖中為相對於主動面13a的架橋記憶體晶粒13的上表面）係大致與連接件123的上表面齊平或共平面。
根據本發明實施例，架橋記憶體晶粒13可以是一雙埠隨機存取記憶體（dual-port RAM），例如一雙埠動態隨機存取記憶體（dual-port DRAM），但不限於此。根據本發明實施例，架橋記憶體晶粒13容許邏輯晶粒11與邏輯晶粒12之間的數據交換或任何的處理器間訊號傳遞（inter-processor communication）。雙埠動態隨機存取記憶體，其提供一個額外的輸入/輸出埠給記憶體陣列，故具有優於傳統DRAM的速度優勢。在傳統的DRAM，由於通過單一的隨機存取埠，故讀取及寫入兩種操作無法同時進行。在雙埠動態隨機存取記憶體中，除了隨機存取埠，還另提供一第二埠（通常是一序列埠）。在序列移位暫存器（serial shift register）與記憶體陣列（array）之間，數據可同時被讀出及寫入。
根據本發明實施例，例如，沿著架橋記憶體晶粒13的週邊，可以設置有穿板通孔（through substrate via）132。穿板通孔132可以利用習知的穿矽通孔（TSV）製程來製作，其中穿板通孔132至少電連接至部分的I/O墊131。根據本發明實施例，架橋記憶體晶粒13可以透過至少部分穿板通孔132與RDL結構中的金屬層電連接。例如，電源或接地訊號可以經由RDL結構及穿板通孔132提供給架橋記憶體晶粒13。
根據本發明實施例，例如，架橋記憶體晶粒13可以利用一覆晶接合製程（flip-chip bonding process）耦合至邏輯晶粒11與邏輯晶粒12上。藉由提供這樣的面對面覆晶組態，架橋記憶體晶粒13可以被設置在接近邏輯晶粒11與邏輯晶粒12的位置。如此一來，記憶體晶粒與邏輯晶粒之間的訊號傳遞距離縮短，故記憶體操作速率（memory operating speed）及訊號完整性（signal integrity）可以獲得改善。
如第4圖所示，接著形成一成型模料20，其至少部分包覆邏輯晶粒11、邏輯晶粒12、架橋記憶體晶粒13，及連接件113及123。成型模料20可以填入架橋記憶體晶粒13與兩個邏輯晶粒11、12之間的細縫，並填入兩個邏輯晶粒11、12之間的細縫。根據本發明實施例，後續可以對成型模料20進行一固化製程。
根據本發明實施例，成型模料20例如為高分子聚合物、環氧樹脂及/或二氧化矽填充劑的混和物，但並不限於此。根據本發明實施例，可以再對成型模料20進行一研磨製程，以顯露出架橋記憶體晶粒13的穿板通孔132的上表面，以及連接件113、123的上表面。
如第5圖所示，接著形成一重佈線層（RDL）結構30，使其耦合架橋記憶體晶粒13的穿板通孔132及連接件113、123的上表面。RDL結構30可以包含，但不限於，至少一介電層301及至少一金屬層302，設於介電層301中。介電層301可包含有機材料，例如，聚亞醯胺（polyimide），或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層302可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。上述RDL結構30可以利用該技術領域的習知方法形成。
RDL結構30可以另包含一鈍化層或一防銲層303，覆蓋RDL結構30的下表面。防銲層303中可以形成有防焊開孔303a，顯露出各別焊接墊302a。焊錫凸塊（例如，C4凸塊）或錫球（例如BGA錫球）40被設置在RDL結構30下表面的各個防焊開孔303a中，構成一球格陣列（ball grid array）。雖然未明示於圖中，熟習該項技藝者應理解在形成上述錫球40之前，可以先形成一凸塊下金屬（UBM）層。
如第6圖所示，於RDL結構30下表面形成焊錫凸塊或錫球40之後，接著將載板10去除。上述去除載板10可以利用雷射製程、紫外線（UV）照射、研磨或蝕刻製程，但不限於此。最後，對此晶圓級封裝進行一晶圓切割製程，將個別的半導體封裝1彼此分離。
根據本發明實施例，半導體封裝1包含有兩個邏輯晶粒11、12同時耦合至一架橋記憶體晶粒13。根據本發明實施例，架橋記憶體晶粒13係直接耦合至RDL結構30。架橋記憶體晶粒13的非主動面13b係直接接觸RDL結構30。根據本發明實施例，架橋記憶體晶粒13係透過穿板通孔132與RDL結構30中的金屬層302電連接。根據本發明實施例，架橋記憶體晶粒13係位於RDL結構30與邏輯晶粒11、12之間。
本發明的優點在於數據或訊號可以直接透過架橋記憶體晶粒13與邏輯晶粒11、12之間的連接件133傳遞。架橋記憶體晶粒13可以是一雙埠動態隨機存取記憶體（dual-port DRAM），容許處理器間訊號傳遞。邏輯晶粒11、12可以共享架橋記憶體晶粒13，且以較短的路徑對架橋記憶體晶粒13同時進行存取動作，故能夠提升記憶體操作速率及改善訊號完整性。
第7圖為依據本發明另一實施例所繪示的半導體封裝的剖面示意圖，其中相同的層、區域或元件仍沿用相同的符號表示。如第7圖所示，半導體封裝2與第6圖中的半導體封裝1的主要差異在於，半導體封裝2的架橋記憶體晶粒13中不具有穿板通孔132。因此，架橋記憶體晶粒13中的電路並不會直接耦合至RDL結構30。
第8圖至第12圖為依據本發明又另一實施例所繪示的製作半導體封裝的方法剖面示意圖。首先，如第8圖所示，提供一載板10。載板10可以是一可卸式基板材料，適合用於承載支撐一薄型基板或晶圓。例如，載板10可以包含矽、玻璃或金屬，但不限於此。
接著，直接於載板10上形成一重佈線層（RDL）結構30。RDL結構30可以包含，但不限於，至少一介電層301及至少一金屬層302，設於介電層301中。介電層301可包含有機材料，例如，聚亞醯胺（polyimide），或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層302可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。RDL結構30可以另包含一鈍化層或一防銲層303，覆蓋RDL結構30的下表面。RDL結構30可以另包含一鈍化層304，覆蓋RDL結構30的上表面。
如第9圖所示，接著，將邏輯晶粒11及邏輯晶粒12貼合至載板10上，使邏輯晶粒11及12的主動面11a及12a面朝向RDL結構30。其中，邏輯晶粒11係鄰近邏輯晶粒12而設置，且邏輯晶粒11與邏輯晶粒12位於共平面。根據本發明實施例，邏輯晶粒11與邏輯晶粒12為覆晶晶粒。例如，邏輯晶粒11及邏輯晶粒12可以包含中央處理器單元（central processing units，CPU）、繪圖處理器單元（graphics processing units，GPU）或應用處理器（application processor），但不限於此。邏輯晶粒11及邏輯晶粒12也可以是，例如，系統單晶片（system on a chip，SoC），但不限於此。邏輯晶粒11可以具有與邏輯晶粒12不相同的功能，例如，邏輯晶粒11可以是CPU，而邏輯晶粒12可以是GPU，但不限於此。
在邏輯晶粒11的主動面11a上，提供有複數個輸出/輸入（I/O）墊111。I/O墊111上形成有連接件113，例如微凸塊、焊錫凸塊、金屬凸塊或金屬柱。根據本發明實施例，連接件113可以包含銅、鋁、金等等，但不限於此。同樣的，在邏輯晶粒12的主動面12a上，提供有複數個輸出/輸入（I/O）墊121。I/O墊121上形成有連接件123，例如微凸塊、焊錫凸塊、金屬凸塊或金屬柱。根據本發明實施例，連接件123可以包含銅、鋁、金等等，但不限於此。
根據本發明實施例，邏輯晶粒11另包含有複數個穿板通孔116，設置在邏輯晶粒11接近邏輯晶粒12的一邊緣上。至少部分的穿板通孔116係電連接至至少部分的I/O墊111。邏輯晶粒12另包含有複數個穿板通孔126，設置在邏輯晶粒12接近邏輯晶粒11的一邊緣上。至少部分的穿板通孔126係電連接至至少部分的I/O墊121。
如第10圖所示，接著將架橋記憶體晶粒（bridge memory die）13耦接至邏輯晶粒11及邏輯晶粒12上。架橋記憶體晶粒13係經由連接件133，例如微凸塊、焊錫凸塊、金屬凸塊或金屬柱，安置固定在相應的穿板通孔116、126上。根據本發明實施例，架橋記憶體晶粒13可以是一覆晶記憶體晶粒（flip chip memory die）。架橋記憶體晶粒13的主動面13a係面朝下，面向邏輯晶粒11及邏輯晶粒12，並透過穿板通孔116、126電連接至邏輯晶粒11及邏輯晶粒12的內部電路。架橋記憶體晶粒13的主動面13a上提供有複數個I/O墊131。
根據本發明實施例，架橋記憶體晶粒13可以是一雙埠隨機存取記憶體，例如一雙埠動態隨機存取記憶體，但不限於此。根據本發明實施例，架橋記憶體晶粒13容許邏輯晶粒11與邏輯晶粒12之間的數據交換或任何的處理器間訊號傳遞。雙埠動態隨機存取記憶體，其提供一個額外的輸入/輸出埠給記憶體陣列，故具有優於傳統DRAM的速度優勢。在傳統的DRAM，由於通過單一的隨機存取埠，故讀取及寫入兩種操作無法同時進行。在雙埠動態隨機存取記憶體中，除了隨機存取埠，還另提供一第二埠（通常是一序列埠）。在序列移位暫存器與記憶體陣列之間，數據可同時被讀出及寫入。
如第11圖所示，接著形成一成型模料20，其至少部分包覆邏輯晶粒11、邏輯晶粒12、架橋記憶體晶粒13，及連接件113、123、133。成型模料20可以填入架橋記憶體晶粒13與兩個邏輯晶粒11、12之間的細縫，並填入兩個邏輯晶粒11、12之間的細縫。根據本發明實施例，後續可以對成型模料20進行一固化製程。架橋記憶體晶粒13的非主動面13b（在此圖中為相對於主動面13a的架橋記憶體晶粒13的上表面）係大致與成型模料20的上表面齊平或共平面。
如第12圖所示，於形成成型模料20之後，接著將載板10去除。上述去除載板10可以利用雷射製程、紫外線（UV）照射、研磨或蝕刻製程，但不限於此。接著於防銲層303中形成防焊開孔303a，顯露出各別焊接墊302a。再將焊錫凸塊（例如，C4凸塊）或錫球（例如BGA錫球）40設置在RDL結構30下表面的各個防焊開孔303a中，構成一球格陣列（ball grid array）。雖然未明示於圖中，熟習該項技藝者應理解在形成上述錫球40之前，可以先形成一凸塊下金屬（UBM）層。最後，對此晶圓級封裝進行一晶圓切割製程，將個別的半導體封裝3彼此分離。
根據本發明實施例，半導體封裝3包含有兩個邏輯晶粒11、12同時耦合至一架橋記憶體晶粒13。根據本發明實施例，架橋記憶體晶粒13不直接耦合至RDL結構30。架橋記憶體晶粒13的非主動面13b不直接接觸RDL結構30。根據本發明實施例，架橋記憶體晶粒13係透過穿板通孔116、126及連接件133與邏輯晶粒11、12電連接。根據本發明實施例，架橋記憶體晶粒13係位於RDL結構30與邏輯晶粒11、12之間。根據本發明實施例，邏輯晶粒11、12係位於RDL結構30與架橋記憶體晶粒13之間。
第13圖為依據本發明又另一實施例所繪示的半導體封裝的剖面示意圖，其中相同的層、區域或元件仍沿用相同的符號表示。如第13圖所示，半導體封裝4與第12圖中的半導體封裝3的主要差異在於，半導體封裝4的架橋記憶體晶粒13另包含有穿板通孔132。半導體封裝4另包含有一上層重佈線層結構60，直接設於架橋記憶體晶粒13的非主動面13b上以及成型模料20的上表面。所述上層重佈線層結構60包含至少一介電層601以及至少一金屬層602，位於介電層601中。半導體封裝4另包含有一穿模通孔（through mold via）202，其電連接至上層重佈線層結構60的金屬層602。因此，架橋記憶體晶粒13內的電路係透過上層重佈線層結構60與穿模通孔202耦合至RDL結構30。
本發明的優點在於數據或訊號可以直接透過架橋記憶體晶粒13與邏輯晶粒11、12之間的連接件133傳遞。架橋記憶體晶粒13可以是一雙埠動態隨機存取記憶體（dual-port DRAM），容許處理器間訊號傳遞。邏輯晶粒11、12可以共享架橋記憶體晶粒13，且以較短的路徑對架橋記憶體晶粒13同時進行存取動作，故能夠提升記憶體操作速率及改善訊號完整性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1、2、3、4‧‧‧半導體封裝
10‧‧‧載板
11、12‧‧‧邏輯晶粒
11a、12a、13a‧‧‧主動面
13b‧‧‧非主動面
13‧‧‧架橋記憶體晶粒
20‧‧‧成型模料
30‧‧‧重佈線層（RDL）結構
40‧‧‧焊錫凸塊或錫球
60‧‧‧上層重佈線層結構
111、112、121、122、131‧‧‧輸出/輸入（I/O）墊
113、123、133‧‧‧連接件
116、126、132‧‧‧穿板通孔
202‧‧‧穿模通孔
301、601‧‧‧介電層
302、602‧‧‧金屬層
302a‧‧‧焊接墊
303‧‧‧防銲層
303a‧‧‧防焊開孔
304‧‧‧鈍化層
100‧‧‧記憶體系統
101‧‧‧電路板
110‧‧‧記憶體匯流排
120‧‧‧雙埠隨機存取記憶體
140、160‧‧‧處理器
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。 第1圖例示習知的記憶體系統。 第2圖至第6圖為依據本發明一實施例所繪示的製作半導體封裝的方法剖面示意圖。 第7圖為依據本發明另一實施例所繪示的半導體封裝的剖面示意圖。 第8圖至第12圖為依據本發明又另一實施例所繪示的製作半導體封裝的方法剖面示意圖。 第13圖為依據本發明又另一實施例所繪示的半導體封裝的剖面示意圖。
1‧‧‧半導體封裝
11、12‧‧‧邏輯晶粒
11a、12a、13a‧‧‧主動面
13‧‧‧架橋記憶體晶粒
20‧‧‧成型模料
30‧‧‧重佈線層(RDL)結構
40‧‧‧焊錫凸塊或錫球
111、112、131‧‧‧輸出/輸入(I/O)墊
113、123、133‧‧‧連接件
132‧‧‧穿板通孔
301‧‧‧介電層
302‧‧‧金屬層
302a‧‧‧焊接墊
303‧‧‧防銲層
303a‧‧‧防焊開孔

Claims (20)

  1. 一種半導體封裝，包含： 一第一邏輯晶粒； 一第二邏輯晶粒，鄰近該第一邏輯晶粒而設置； 一架橋記憶體晶粒，耦接至該第一邏輯晶粒與該第二邏輯晶粒； 一重佈線層（RDL）結構，耦合該第一邏輯晶粒與該第二邏輯晶粒；以及 一成型模料，至少部分包覆該第一邏輯晶粒、該第二邏輯晶粒及該架橋記憶體晶粒。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該第一邏輯晶粒與該第二邏輯晶粒位於共平面。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒係以面對面覆晶組態與該第一邏輯晶粒與該第二邏輯晶粒電連接。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒係為一雙埠隨機存取記憶體（dual-port RAM）。
  5. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒係為一雙埠動態隨機存取記憶體（dual-port DRAM）。
  6. 如申請專利範圍第1項所述的半導體封裝，其中該第一邏輯晶粒包含中央處理器單元、繪圖處理器單元或應用處理器。
  7. 如申請專利範圍第1項所述的半導體封裝，其中該第二邏輯晶粒包含中央處理器單元、繪圖處理器單元或應用處理器。
  8. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒容許該第一邏輯晶粒與該第二邏輯晶粒之間的處理器間訊號傳遞。
  9. 如申請專利範圍第1項所述的半導體封裝，其中該第一邏輯晶粒係經由複數個第一連接件與該RDL結構電連接。
  10. 如申請專利範圍第9項所述的半導體封裝，其中該第二邏輯晶粒係經由複數個第二連接件與該RDL結構電連接。
  11. 如申請專利範圍第10項所述的半導體封裝，其中該架橋記憶體晶粒係經由複數個第三連接件與該第一邏輯晶粒與該第二邏輯晶粒電連接。
  12. 如申請專利範圍第11項所述的半導體封裝，其中該第一連接件、該第二連接件與該第三連接件包含金屬凸塊或金屬柱。
  13. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒係經由複數個穿板通孔（through substrate via）與該RDL結構電連接。
  14. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒的一非主動面係直接接觸該RDL結構。
  15. 如申請專利範圍第1項所述的半導體封裝，其中該架橋記憶體晶粒係介於該RDL結構與該第一邏輯晶粒與該第二邏輯晶粒之間。
  16. 如申請專利範圍第1項所述的半導體封裝，其中該第一邏輯晶粒與該第二邏輯晶粒係介於該RDL結構與該架橋記憶體晶粒之間。
  17. 如申請專利範圍第16項所述的半導體封裝，其中另包含一上層重佈線層，位於該架橋記憶體晶粒與該成型模料上，及至少一穿模通孔（through mold via），設於該成型模料中，電連接至該上層重佈線層。
  18. 如申請專利範圍第17項所述的半導體封裝，其中該穿模通孔係電連接至該RDL結構。
  19. 如申請專利範圍第17項所述的半導體封裝，其中該架橋記憶體晶粒包含電連接至該上層重佈線層的數個穿板通孔。
  20. 如申請專利範圍第1項所述的半導體封裝，其中另包含複數個焊錫凸塊或錫球，設於該RDL結構的一下表面。
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