TWI726367B - 半導體封裝結構及其製備方法 - Google Patents

半導體封裝結構及其製備方法 Download PDF

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TWI726367B
TWI726367B TW108126670A TW108126670A TWI726367B TW I726367 B TWI726367 B TW I726367B TW 108126670 A TW108126670 A TW 108126670A TW 108126670 A TW108126670 A TW 108126670A TW I726367 B TWI726367 B TW I726367B
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die
conductors
semiconductor package
package structure
manufacturing
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TW108126670A
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TW202025424A (zh
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施信益
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體封裝結構及其製備方法。該半導體封裝結構包括一第一晶粒、至少一第二晶粒、位在該第二晶粒上的一重佈線層(RDL)、將該第一晶粒與該第二晶粒封入的一封模、位在該封模中的複數個第一導體，以及位在該第二晶粒中的複數個第二導體。該第一晶粒具有相對設置的一第一側與一第二側。該第二晶粒具有相對設置的一第三側及一第四側，該第三側係面對該第一晶粒的該第一側。該重佈線層位在該第二晶粒的該第四側上。該第一晶粒經由該等第一導體電性連接該重佈線層，且該第二晶粒經由該等第二導體電性連接該重佈線層。

Description

半導體封裝結構及其製備方法
本申請案主張2018/12/20申請之美國臨時申請案第62/782,712號及2019/06/27申請之美國正式申請案第16/454,609號的優先權及益處，該美國臨時申請案及該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝結構及其製備方法。特別是有關於一種三維積體電路(three-dimensional integrated circuit，3DIC)的半導體封裝結構及其製備方法。
對於許多現代應用，半導體裝置是必不可少的。隨著電子科技的進步，半導體裝置的尺寸變得更小，同時具有較佳功能性以及較大量的積體電路。由於半導體裝置規格的微小化，因此現在層疊晶片(chip-on-chip)技術係廣泛地被用於製造半導體封裝。
在一方法中，在一三維(3D)封裝中使用至少二晶片(或晶粒)的一層疊以形成如一記憶體裝置，其係可能製造出一產品，此產品係具有一記憶體容量(memory capacity)，此記憶體容量係為經由其他半導體整合製程(semiconductor integration process)所可包含的兩倍以上。除了增 加記憶體容量，一層疊封裝亦提供改善安裝密度(mounting density)及安裝面積之利用效率。由於如此的優點，疊層封裝(stack package)技術係已加速研發。
半導體裝置的製造正變得更加複雜。半導體裝置係用一些積體元件(integrated components)所組裝而成，而積體元件具有不同材料，而這些材料係具有不同的熱性質(thermal properties)。因為結合許多具有不同材料的元件，因此係增加半導體裝置之製造操作的複雜度。據此，係有持續需要來改善半導體裝置的製造製程以及應付上述的複雜度。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一晶粒、至少一第二晶粒、位在該第二晶粒上的一重佈線層(RDL)、將該第一晶粒與該第二晶粒封在其中的一封模、位在該封模中的複數個第一導體，以及位在該第二晶粒中的複數個第二導體。在一些實施例中，該第一晶粒具有相對設置的一第一側及一第二側。在一些實施例中，該第二晶粒具有相對設置的一第三側及一第四側，該第三側係面對該第一晶粒的該第一側。該重佈線層係位在該第二晶粒的該第四側上。在一些實施例中，該第一晶粒係經由該等第一導體電性連接該重佈線層，且該第二晶粒係經由該等第二導體電性連接該重佈線層。
依據本揭露之一些實施例，該半導體封裝結構還包括複數個導電組件，位在該第一晶粒的該第一側與該第二晶粒的該第三側之間。
依據本揭露之一些實施例，該第一晶粒與該第二晶粒係以該等導電組件而相互連結(bonded)且電性連接。
依據本揭露之一些實施例，該封模具有相對設置的一第五側及一第六側，該第五側係面對該重佈線層。
依據本揭露之一些實施例，該封模的該第六側與該第一晶粒的該第二側為共面(coplanar)。
依據本揭露之一些實施例，該半導體封裝結構還包括複數個連接結構，係位在該重佈線層上。
依據本揭露之一些實施例，該第一晶粒為一邏輯晶粒(logic die)。在一些實施例中，該第二晶粒為一記憶體晶粒(memory die)。
依據本揭露之一些實施例，該第一晶粒的一晶粒尺寸係大於該第二晶粒的一晶粒尺寸。
依據本揭露之一些實施例，該等第一導體包括複數個直通模穿孔(through molding vias，TMVs)。
依據本揭露之一些實施例，該等第二導體包括複數個直通矽穿孔(through Silicon Vias,TSVs)。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該製備方法包括下列步驟。提供一第一晶粒。將一第二晶粒連結(bonding)到該第一晶粒，其中該第二晶粒包含複數個第一導體。在該第一晶粒上配置複數個第二導體。配置一封模以將該第一晶粒、該第二晶粒以及該等第二導體封在其中。在該第二晶粒與該封模上配置一重佈線層(RDL)。在該重佈線層上配置複數個連接結構。
依據本揭露之一些實施例，該製備方法還包括在該第二晶 粒連結到該第一晶粒之前，係將該第一晶粒貼合在一載送基底(carrier substrate)上。
依據本揭露之一些實施例，該製備方法還包括下列步驟。於該連接結構形成之後，單顆化該重佈線層、該封模，以及該第二晶粒，以形成一半導體封裝結構。從該載送基底分離該半導體封裝結構。
依據本揭露之一些實施例，該第一晶粒還包括複數個導電組件。
依據本揭露之一些實施例，該第二晶粒經由該等導電組件而連結且電性連接該第一晶粒。
依據本揭露之一些實施例，該製備方法還包括於形成該重佈線層之前，移除該封模的一部分，以暴露該第二晶粒的一表面以及該等第二導體的表面。
依據本揭露之一些實施例，該第一晶粒的一晶粒尺寸係大於該第二晶粒的一晶粒尺寸。
依據本揭露之一些實施例，該第一晶粒為一邏輯晶粒。在一些實施例中，該第二晶粒為一記憶體晶粒。
依據本揭露之一些實施例，該等第一導體包含複數個直通矽穿孔(through Silicon Vias，TSVs)。
依據本揭露之一些實施例，該等第二導體包含複數個直通模穿孔(through molding vias，TMVs)。
在本揭露中，係提供一種半導體封裝結構的製備方法。依據該製備方法，該第一晶粒經由該等直通模穿孔(TMVs)電性連接該重佈線層，同時該第二晶粒經由該等直通矽穿孔(TSVs)電性連接該重佈線 層。據此，係簡化在半導體封裝結構中元件之間的電性連接。值得注意地，複數個直通模穿孔及複數個直通矽穿孔在該半導體封裝結構中係均垂直地延伸。因此，由於垂直的電性連接，係可更縮小半導體封裝結構的封裝尺寸(package size)。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:製備方法
101:步驟
102:步驟
103:步驟
104:步驟
105:步驟
106:步驟
107:步驟
108:步驟
200:半導體封裝結構
201:載送基底
210:第一晶粒
212a:第一側
212b:第二側
214:導電組件
220:第二晶粒
222a:第三側
222b:第四側
230:導體
232:導體
240:封模
242a:上側
242b:底側
250:重佈線層
260:連接結構
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一些實施例的一種半導體封裝結構的製備方法之流程示意圖。
圖2至圖9為依據本揭露一些實施例該半導體封裝結構的製備方法於不同製備階段之結構示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。
圖1為依據本揭露一些實施例的一種半導體封裝結構的製備方法之流程示意圖。所述半導體封裝結構的製備方法10包括步驟101，將一第一晶粒結合在一載送基底(carrier substrate)上。該製備方法10還包括一步驟102，將一第二晶粒連結(bonded)到第一晶粒。在一些實施例中，弟二晶粒包含複數個第一導體。該製備方法10還包括一步驟103，在第一 晶粒上配置複數個第二導體。該製備方法10還包括一步驟104，配置一封模(molding)以將第一晶粒、第二晶粒以及複數個第二導體封在其中。該製備方法10還包括一步驟105，在第二晶粒上及封模上配置一重佈線層(redistribution layer，RDL)。該製備方法10還包括一步驟106，在重佈線層上配置複數個連接結構(connecting structures)。該製備方法10還包括一步驟107，單顆化第一晶粒、第二晶粒以及封模，以形成一半導體封裝結構。該半導體封裝結構的製備方法10係依據下列的一或多個實施例，將再做進一步的描述。
圖2至圖9為依據本揭露一些實施例該半導體封裝結構的製備方法於不同製備階段之結構示意圖。請參考圖2，依據步驟101，係提供一第一晶粒210並結合(attached)到一載送基底201。在一些實施例中，複數個第一晶粒210係可結合到單一個載送基底201，但本揭露並不以此為限。在一些實施例中，第一晶粒210係經由一離型膜(release film)(圖未示)暫時地結合到載送基底201。在一些實施例中，離型膜係可為一氟基膜(fluorine-base film)、一塗矽聚對苯二甲酸乙二酯(silicon-coated polyethylene terephthalate)膜、一聚甲基戊烯(polymethylpentene)膜、一聚丙烯(polypropylene)膜，或者是其他適合的材料，但本揭露並不以此為限。在一些實施例中，載送基底201係架構來支撐一晶粒(die)、一晶片(chip)或者是一封裝(package)。在一些實施例中，載送基底201係為一矽晶圓(silicon wafer)、一玻璃晶圓(glass wafer)或者是其類似物。
在一些實施例中，第一晶粒210係為一晶粒、一晶片或者是一封裝。在一些實施例中，第一晶粒210係與由微影(photolithography)製程所生產的第一晶粒210中的一預定功能電路(predetermined functional circuit)所一同製造。在一些實施例中，第一晶粒210係以一機械刀(mechanical blade)或是一雷射刀(laser blade)從一半導體晶圓(semiconductor wafer)單顆化。在一些實施例中，第一晶粒210包括適合於不同應用之電子電路的一變化(variety)。在一些實施例中，所述電子電路包括不同裝置，例如電晶體、電容器、電阻器、二極體或其類似物。在一些實施例中，第一晶粒210包括任何一種已知的不同型態的半導體裝置，以形成一加速處理單元(accelerated processing unit，APU)、一中央處理單元(central processing unit，CPU)、一圖形處理單元(Graphic Processing Unit，GPU)、微處理器(microprocessors)、特殊應用積體電路(Application-Specific Integrated Circuits，ASICs)、數位信號處理器(digital signal processors，DSPs)，或其類似物。在一些實施例中，依據本實施例，第一晶粒210係可為一邏輯裝置(logic device)，但本揭露並不以此為限。
在一些實施例中，第一晶粒210包括相對設置的一第一側212a及一第二側212b。在一些實施例中，第一側212a係為有電路或電子元件配置在其上的一前側或一主動側(active side)。在一些實施例中，第二側212b係為不存在電路或電子元件的一後側或一非主動側(inactive side)。如圖2所示，第一晶粒210係經由第二側212b而結合到載送基底201。第一晶粒210還包括複數個導電組件(conductive members)214，導電組件214係位在第一側212a上。在一些實施例中，複數個導電組件214係電性連接位在第一晶粒210中的電路或是電子元件。
請參考圖3，依據步驟102，至少一第二晶粒220係連結(bonded)到第一晶粒210。在一些實施例中，如圖3所示，複數個第二晶圓 220係配置在單一個第一晶粒210上，但本揭露並不以此為限。在一實施例中，第一晶粒210的一晶粒尺寸(die size)係大於第二晶粒220的一晶粒尺寸，但本揭露並不以此為限。在一些實施例中，第二晶粒220係為一晶粒、一晶片或者是一封裝。在一些實施例中，第二晶粒220係與由微影製程所生產的第二晶粒220中的一預定功能電路所一同製造。在一些實施例中，第二晶粒220係以一機械刀或是一雷射刀從一半導體晶圓單顆化。在一些實施例中，第二晶粒220包括適合於不同應用之電子電路的一變化(variety)。在一些實施例中，所述電子電路包括不同裝置，例如電晶體、電容器、電阻器、二極體或其類似物。在一些實施例中，在一些實施例中，第二晶粒220包括任何一種已知的不同型態的半導體裝置，以形成一加速處理單元(APU)、記憶體(memories)、動態隨機存取記憶體(DRAM)、一反及快閃記憶體(NAND flash memory)、一中央處理單元(CPU)、一圖形處理單元(GPU)、微處理器、特殊應用積體電路(ASICs)、數位信號處理器(DSPs)，或其類似物。在一些實施例中，第二晶粒220係為一記憶體晶粒(memory die)，但本揭露並不以此為限。在一些實施例中，第一晶粒210與第二晶粒220係包括完全相同或是不同型態的半導體裝置。
第二晶粒220包括相對設置的一第三側222a以及一第四側222b。在一些實施例中，第三側222a係為有電路或電子元件配置在其上的一前側或一主動側(active side)。在一些實施例中，第四側222b係為不存在電路或電子元件的一後側或一非主動側(inactive side)。如圖3所示，第二晶粒220係經由第三側222a而結合到第一晶粒210。再者，如第3圖所示，第二晶粒220係經由複數個導電組件214而連結並電性連接第一晶粒 210，此處的複數個導電組件214係位在第一晶粒210的第一側212a與第二晶粒220的第三側222a之間。
值得注意地，第二晶粒220包含配置在其中的複數個導體230(在一些實施例中，導體230可作為直通矽穿孔，TSV)。在一些實施例中，一互連結構(interconnection structure)(圖未示)係可配置在第二晶粒220的第三側222a上。在一些實施例中，複數個直通矽穿孔230係從第二晶粒220的第四側222b延伸到第二晶粒220的第三側222a，並電性連接所述互連結構。在一些實施例中，第二晶粒220經由所述互連結構與複數個導電組件214電性連接第一晶粒210。在一些實施例中，複數個直通矽穿孔230係經由第二晶粒220的第四側222b暴露。
請參考圖4，依據步驟103，複數個導體232係配置在第一晶粒210上(在一些實施例中，複數個導體232係為導電柱體)，導電柱體係配置在第一晶粒210的第一側212a上。在一些實施例中，導電柱體232係位在第一晶粒210的一晶粒墊(die pad)或一導腳(terminal)上，並電性連接晶粒墊或導腳與第一晶粒210外的一元件(component)。在一些實施例中，導電柱體232係包含導電材料，例如銅(Cu)、銀(Ag)或金(Au)。在一些實施例中，導電柱體232係為圓柱形(cylindrical shape)。在一些實施例中，導電柱體232的一剖面係可包括圓形、矩形、四邊形或是多邊形，但本揭露並不以此為限。在一些實施例中，導電柱體232的一高度係大致與第二晶粒220之一厚度加上導電組件214的一高度之總合相同，但本揭露並不以此為限。
請參考圖5所示，依據步驟104，一封模(molding)240係配置來將第一晶粒210、第二晶粒220以及複數個導電柱體232封在其中。如 圖5所示，封模240係可位在載送基底201上，以圍繞第一晶粒210、第二晶粒220以及複數個導電柱體232。在一些實施例中，封模240係可為單一層膜或是一複合疊(composite stack)。在一些實施例中，封模240包含不同材料，例如模製化合物(molding compound)、模塑底部填充物(molding underfill)、環氧樹脂(epoxy)、樹脂(resin)或其類似物。在一些實施例中，封模240具有一高導熱性(high thermal conductivity)、一低吸濕率(low moisture absorption rate)，以及一高抗彎強度(flexural strength)。再者，如圖5所示，第一晶粒210、第二晶粒220以及複數個導電柱體232係可全部地埋置或封入在封模240中。
請參考圖6，在一些實施例中，步驟104還包括移除封模240的一部分，以暴露第二晶粒220的一表面以及複數個導電柱體232的表面。在一些實施例中，係回磨(grinded back)封模240，直至暴露第四側222b上之第二晶粒220的表面以及複數個導電柱體232的端表面(end surfaces)。
請參考圖7，依據步驟105，一重佈線層(RDL)250係位在第二晶粒220與封模240上。在一些實施例中，重佈線層250係可包括一介電堆疊(dielectric stack)(圖未示)以及位在介電堆疊中的許多導線(conductive lines)(圖未示)。導線電性連接在重佈線層250相對兩側上的導電導腳(conductive terminals)(圖未示)。導線係亦被使用來形成在複數個導體230與外部元件(external components)(圖未示)之間的一電性連接，以及形成複數個導電柱體232與外部元件之間的一電性連接。在一些實施例中，導線係可由下列材料所製：銅(Cu)、金(Au)、銀(Ag)、鎳(Ni)、錫(Sn)、鉛(Pb)、鎢(W)、鋁(Al)、鈦(Ti)、鈀(Pd)、焊錫(solder)或者是其 合金(alloys)，但本揭露並不以此為限。
請參考圖8，依據步驟106，複數個連接結構(connecting structures)260係位在重佈線層250上。在一些實施例中，複數個連接結構260係位在重佈線層250的一側上，同時第一晶粒210、第二晶粒220以及複數個導電柱體232係位在重佈線層250相對複數個連接結構260的一側上。在一些實施例中，複數個連接結構260係為導電凸塊(conductive bumps)，其係包含導電材料，例如焊錫、銅、鎳或金，但本揭露並不以此為限。在一些實施例中，複數個連接結構260係為錫球(solder balls)、球柵陣列(ball grid array，BGA)球、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊(microbumps)，或是柱體(pillars)，但本揭露並不以此為限。在一些實施例中，連接結構260係可為球形、半球形，或是圓柱形，但本揭露並不以此為限。
請參考圖9，在一些實施例中，依據步驟107，在形成連接結構260之後，單顆化第一晶粒210、位在第一晶粒210上的第二晶粒以及封模240。因此，依據步驟108，係形成一半導體封裝結構200。再者，如圖9所示，係可翻轉半導體封裝結構200。
繼續參考圖9，半導體封裝結構200包括一第一晶粒210、至少一第二晶粒220、至少將第一晶粒210與第二晶粒220封在其中的一封模240、一重佈線層250、位在第二晶粒220中的複數個導體230，以及位在封模240中的複數個導體232。如圖9所示，第一晶粒210具有相對設置的一第一側212a以及一第二側212b。在一些實施例中，第一側212a係為一主動側，其上配置有電路或電子元件。第二晶粒220具有相對設置的一第三側222a以及一第四側222b，第三側222a係面對第一晶粒210的第一側 212a。如上所述，第二晶粒220的第三側222a係為一主動側，其上配置有電路或電子元件。再者，位在第二晶粒220中的複數個導體230係從第四側222b延伸到第三側222a。複數個導體230係經由第二晶粒220的第四側222b暴露。如上所述，位在第二晶粒220中的複數個導體230係為複數個直通矽穿孔(TSVs)。第二晶粒220經由複數個直通矽穿孔電性連接重佈線層250。複數個導體232係位在封模240中，並封入到封模240中。換言之，複數個導體232在封模240中垂直地延伸，並將第一晶粒210電性連接到重佈線層250。據此，在封模240中延伸的複數個導體232係歸類為直通模穿孔(TMVs)。再者，半導體封裝結構200係包括複數個導電組件214，導電組件214係位在第一晶粒210與第二晶粒220之間。第一晶粒210與第二晶粒220也因此經由複數個導電組件214而相互連結並電性連接。半導體封裝結構200還包括複數個連接結構260，連接結構260係位在重佈線層250上。如圖9所示，複數個連接結構260係位在重佈線層250的一側上，該側係相對第一晶粒210、第二晶粒220、複數個導體232以及封模240。複數個連接結構260係提供在半導體封裝結構200與外部元件之間的電性連接。
如圖9所示，封模240具有相對設置的一上側242a以及一底側242b。如圖9所示，封模240的底側242b係接觸重佈線層250，同時封模240的上側242a係與第一晶粒210的第二側212b為共面(coplanar)。再者，在一些實施例中，第一晶粒210的側壁(sidewalls)以及第二晶粒220的側壁(sidewalls)係接觸封模240，但本揭露並不以此為限。
在一些實施例中，第一晶粒210係可為一邏輯晶粒，同時第二晶粒220係可為一記憶體晶粒，但本揭露並不以此為限。在一些實施例 中，第一晶粒210的一晶粒尺寸係大於第二晶粒220的一晶粒尺寸，但本揭露並不以此為限。
請繼續參考圖9，在一些實施例中，第一晶粒210係經由複數個導體232(例如直通模穿孔(TMVs))電性連接重佈線層250，同時第二晶粒220係經由複數個導體230(例如直通矽穿孔(TSVs))電性連接重佈線層250。
在本揭露中，係提供一種半導體封裝結構的製備方法10。依據所述製備方法10，係形成複數個導體230以提供第二晶粒220與重佈線層250之間的電性連接、形成複數個導體232以提供第一晶粒210與重佈線層250之間的電性連接、以及形成導電組件214以提供第一晶粒210與第二晶粒220之間的電性連接。據此，係簡化在半導體封裝結構與外部元件(external components)中之元件(例如第一晶粒210與第二晶粒220)之間的電性連接。值得注意地，複數個導體230與複數個導體232係全部在半導體封裝結構200中垂直地延伸。因此，由於垂直電性連接，係可更加縮小半導體封裝結構200的封裝尺寸(package size)。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一晶粒、至少一第二晶粒、位在該第二晶粒上的一重佈線層(RDL)、將該第一晶粒與該第二晶粒封在其中的一封模、位在該封模中的複數個第一導體，以及位在該第二晶粒中的複數個第二導體。在一些實施例中，該第一晶粒具有相對設置的一第一側及一第二側。在一些實施例中，該第二晶粒具有相對設置的一第三側及一第四側，該第三側係面對該第一晶粒的該第一側。該重佈線層係位在該第二晶粒的該第四側上。在一些實施例中，該第一晶粒係經由該等第一導體電性連接該重佈線層，且該 第二晶粒係經由該等第二導體電性連接該重佈線層。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該製備方法包括下列步驟。提供一第一晶粒。將一第二晶粒連結(bonding)到該第一晶粒，其中該第二晶粒包含複數個第一導體。在該第一晶粒上配置複數個第二導體。配置一封模以將該第一晶粒、該第二晶粒以及該等第二導體封在其中。在該第二晶粒與該封模上配置一重佈線層(RDL)。在該重佈線層上配置複數個連接結構。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
200:半導體封裝結構
210:第一晶粒
212a:第一側
212b:第二側
214:導電組件
220:第二晶粒
222a:第三側
222b:第四側
230:導體
232:導體
240:封模
242a:上側
242b:底側
250:重佈線層
260:連接結構

Claims (20)

  1. 一種半導體封裝結構，包括：一第一晶粒，具有相對設置的一第一側及一第二側；至少二個第二晶粒，各具有相對設置的一第三側及一第四側，該第三側係面對該第一晶粒的該第一側；一重佈線層，位在該等第二晶粒的該第四側上；一封模，將該第一晶粒及該至少二個第二晶粒封在其中；複數個第一導體，位在該封模中；以及複數個第二導體，位在該等第二晶粒各者中；其中該第一晶粒經由該等第一導體電性連接該重佈線層，且該等第二晶粒經由該等第二導體電性連接該重佈線層。
  2. 如請求項1所述之半導體封裝結構，還包括複數個導電組件，位在該第一晶粒的該第一側與該等第二晶粒的該第三側之間。
  3. 如請求項2所述之半導體封裝結構，其中該第一晶粒與該等第二晶粒係以該等導電組件而相互連結且電性連接。
  4. 如請求項1所述之半導體封裝結構，其中該封模具有相對設置的一第五側及一第六側，該第五側係面對該重佈線層。
  5. 如請求項4所述之半導體封裝結構，其中該封模的該第六側與該第一 晶粒的該第二側為共面。
  6. 如請求項1所述之半導體封裝結構，還包括複數個連接結構，係位在該重佈線層上。
  7. 如請求項1所述之半導體封裝結構，其中該第一晶粒為一邏輯晶粒，該等第二晶粒為一記憶體晶粒。
  8. 如請求項1所述之半導體封裝結構，其中該第一晶粒的一晶粒尺寸係大於該等第二晶粒各者的一晶粒尺寸。
  9. 如請求項1所述之半導體封裝結構，其中該等第一導體包括複數個直通模穿孔。
  10. 如請求項1所述之半導體封裝結構，其中該等第二導體包括複數個直通矽穿孔。
  11. 一種半導體封裝結構的製備方法，包括：提供一第一晶粒；將二個第二晶粒連結到該第一晶粒，其中該等第二晶粒各者包含複數個第一導體；在該第一晶粒上配置複數個第二導體；配置一封模以將該第一晶粒、該等第二晶粒以及該等第二導體封 在其中；在該等第二晶粒與該封模上配置一重佈線層；以及在該重佈線層上配置複數個連接結構。
  12. 如請求項11所述之製備方法，還包括在該等第二晶粒連結到該第一晶粒之前，係將該第一晶粒貼合在一載送基底上。
  13. 如請求項12所述之製備方法，還包括：於該連接結構形成之後，單顆化該重佈線層、該封模，以及該等第二晶粒，以形成一半導體封裝結構；以及從該載送基底分離該半導體封裝結構。
  14. 如請求項11所述之製備方法，其中該第一晶粒還包括複數個導電組件。
  15. 如請求項14所述之製備方法，其中該等第二晶粒經由該等導電組件而連結且電性連接該第一晶粒。
  16. 如請求項11所述之製備方法，還包括於形成該重佈線層之前，移除該封模的一部分，以暴露該等第二晶粒各者的一表面以及該等第二導體的表面。
  17. 如請求項11所述之製備方法，其中該第一晶粒的一晶粒尺寸係大於 該等第二晶粒各者的一晶粒尺寸。
  18. 如請求項11所述之製備方法，其中該第一晶粒為一邏輯晶粒，該等第二晶粒為一記憶體晶粒。
  19. 如請求項11所述之製備方法，其中該等第一導體包含複數個直通矽穿孔。
  20. 如請求項11所述之製備方法，其中該等第二導體包含複數個直通模穿孔。
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