TWI550801B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TWI550801B
TWI550801B TW102141194A TW102141194A TWI550801B TW I550801 B TWI550801 B TW I550801B TW 102141194 A TW102141194 A TW 102141194A TW 102141194 A TW102141194 A TW 102141194A TW I550801 B TWI550801 B TW I550801B
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Taiwan
Prior art keywords
semiconductor substrate
layer
heat dissipation
package structure
sidewall
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TW102141194A
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English (en)
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TW201519388A (zh
Inventor
廖宗仁
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南茂科技股份有限公司
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Priority to TW102141194A priority Critical patent/TWI550801B/zh
Priority to CN201410125667.4A priority patent/CN104637895B/zh
Priority to US14/246,302 priority patent/US20150130084A1/en
Publication of TW201519388A publication Critical patent/TW201519388A/zh
Application granted granted Critical
Publication of TWI550801B publication Critical patent/TWI550801B/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

封裝結構及其製造方法
本發明係關於一種半導體封裝，且更特定言之，係關於一種具有側邊散熱設計之扇出封裝結構。
因應目前電腦與消費電子產品之可攜式及多功能的要求，其外形尺寸需不斷縮小，而積體電路晶片之積體電路密度則不斷提升。受限於可用空間的限制，因此許多不同的封裝方式如：多晶片模組(multi-chip module；MCM)、覆晶封裝(flip chip package)、三維垂直堆疊封裝(3D stack package)、晶圓級晶片尺寸封裝(wafer level chip scale package；WLCSP)等技術應運而生。晶圓級封裝技術的概念基本上是在整片晶圓上執行晶片尺寸的封裝技術，也就是在晶圓階段就完成了於積體電路晶片上直接形成錫球等大部分的封裝工作，不但省略了傳統封裝技術中承載晶片之基板或導線架，也簡化了封裝製程。因此，晶圓級晶片尺寸封裝可以縮小封裝體尺寸，並且在製程及材料成本上也相當具有優勢。
目前WLCSP晶圓級封裝完成後，需要在後段研磨後再進行切割。如圖1所示，最後封裝後的成品背面需塗上散熱膏7再裝上散熱片5幫助晶片導熱，然而此方式的成本過高。且塗上散 熱膏7及放置散熱片5之前，需要另一研磨製程使得晶圓背面光滑，此製程增加額外成本。
傳統散熱膏7及散熱片5結構中，熱能朝著垂直晶片(圖1箭頭)的方向逸散，一部份熱能往散熱片5方向逸散，一部份熱能透過銲球往基板方向逸散。然而隨著晶片產熱量增加，以及晶片面積縮小，其散熱方式已不符合時宜。
本發明之一個實施例描述一種具有側邊散熱設計之扇出封裝結構，包括：一半導體基板，一銲墊位於所述半導體基板上，以及一重分佈線路層連接於所述銲墊並位於所述半導體基板上方且該重分佈線路層之一端往所述半導體基板之一側壁延伸，且所述端與所述側壁切齊。
在一個實施例中，所述側壁為一粗糙化表面。
在一個實施例中，所述半導體基板之背面為一粗糙化表面。
在一個實施例中，所述重分佈線路層位於所述半導體基板外圍。
本發明之一個實施例描述一種具散熱圖案之封裝結構包含：一半導體基板，一銲墊位於所述半導體基板上，以及一散熱圖案位於所述半導體基板上方，其中所述散熱圖案係由一重分佈線路層連接於所述銲墊並位於所述半導體基板之外圍並且切齊所述半導體基板之一側壁所組成。
在一個實施例中，所述散熱圖案為一圍繞半導體基板外圍之環狀結構。
本發明之一個實施例描述一種具有側邊散熱設計之扇出封 裝結構的製造方法，其步驟包含：提供一半導體基板具有一銲墊位於所述半導體基板之一正面之上方；形成一第一介電層位於所述半導體基板之所述正面上方；以及形成一重分佈線路層連接於所述銲墊並覆蓋所述第一介電層及所述半導體基板之外圍，使所述重分佈線路層與所述半導體基板之一側壁切齊。
在一個實施例中，進一步包含附著一保護層於所述半導體基板之所述正面及所述重分佈線路層上僅露出所述半導體基板之一背面及所述側壁。
在一個實施例中，進一步包含沈浸所述半導體基板之所述背面及所述側壁於蝕刻液中，並且濕式微蝕刻所述半導體基板之所述側壁及所述背面。
在一個實施例中，進一步包含形成一保護層在所述半導體基板之所述背面。
在一個實施例中，進一步包含沈浸所述半導體基板於蝕刻液中，並且濕式微蝕刻所述半導體基板之所述側壁。
在一個實施例中，進一步包含無電極電鍍所述半導體基板之所述側壁及/或所述背面。
前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述，且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解，所揭示之概念及特定實施例可易於用作修改或設計其他結構或程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離如隨附申請專利範圍中所闡明之本發明之精神及範疇。
5‧‧‧散熱片
7‧‧‧散熱膏
10‧‧‧封裝結構
11‧‧‧封裝結構
14‧‧‧封裝結構
15‧‧‧封裝結構
16‧‧‧封裝結構
21‧‧‧半導體基板
22‧‧‧銲墊
23‧‧‧鈍化層
24‧‧‧圖案化層
25‧‧‧端面
26‧‧‧側壁
27‧‧‧正面
28‧‧‧背面
31‧‧‧第一介電層
32‧‧‧延伸介電層
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41‧‧‧重分佈線路層
42‧‧‧重分佈線路層
43‧‧‧重分佈線路層
45‧‧‧散熱圖案
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51‧‧‧第二介電層
52‧‧‧第二介電層
53‧‧‧第二介電層
55‧‧‧開口
56‧‧‧開口
57‧‧‧開口
61‧‧‧焊球
71‧‧‧保護層
72‧‧‧保護層
圖1顯示為先前技術； 圖2為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構之示意性剖視圖；圖3為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構之示意性剖視圖；圖4為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構之示意性剖視圖；圖5為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構之示意性剖視圖；圖6為本揭露一實施例之一具有散熱圖案之封裝結構之上視圖；以及圖7-8為本揭露一實施例之形成粗糙側壁之示意圖。
上文已經概略地敍述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應可瞭解，下文揭示之概念與特定實施例可作為基礎而相當輕易地予以修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應可瞭解，這類等效的建構並無法脫離後附之申請專利範圍所提出之本揭露的精神和範圍。
以下所述的詳細內容主要是用來舉例說明本發明中所提的例示裝置或方法，所述內容不應用來限定本發明，而且對於任何與本發明概念均等的功能與元件皆不脫離本發明的精神。以下描述請參考附圖，以便於說明本發明之目的及優點。
圖2顯示為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構10之示意性剖視圖。封裝結構10包括：一半導體基板21、一銲墊22、一鈍化層23、一圖案化層24、一第一介電層31、一重分佈線路 層(RDL,Redistribution Layer)41、一第二介電層51、以及一焊球61。半導體基板21包含一側壁26及一背面28，側壁26及背面28包含粗糙化的表面。第一介電層31包含一延伸介電層32。鈍化層23之側邊及圖案化層24之側邊組成一端面25。
根據某些實施例，如圖2所示，銲墊22位於半導體基板21上方。鈍化層23位於銲墊22之上方，鈍化層23具有一開口用以暴露一部份銲墊22。圖案化層24位於鈍化層23之上方，圖案化層24亦具有一開口相容於暴露的一部份銲墊22。第一介電層31位於圖案化層24上方，第一介電層31覆蓋圖案化層24及端面25並往側壁26延伸而形成延伸介電層32。延伸介電層32位於半導體基板21上方。此外，延伸介電層32與側壁26切齊。重分佈線路層41連接銲墊22並位於半導體基板21上方，重分佈線路層41之一端往半導體基板21之側壁26延伸，且所述端與側壁26切齊。
在本實施例中，第二介電層51覆蓋於重分佈線路層41上方，第二介電層51向側壁26延伸，並且與側壁26切齊。第二介電層51包含一開口55。開口55暴露一部份重分佈線路層41。開口55可用來作為焊球61生成的位置。在某些實施例中，一凸塊下金屬層(UBM，未顯示)形成於開口55內。再將焊球61形成於凸塊下金屬層上方，使得焊球61與重分佈線路層41電性連接。
重分佈線路層41除了作為封裝結構10內部的電連結結構，亦可提供一熱能逸散的途徑。銲球61與銲墊22為主要產熱區域，電連接的過程中會產生熱能，重分佈線路層41如同一熱傳導路線，不僅傳導電性，亦傳導熱能。此外，重分佈線路層41由金屬所構成，金屬相對於介電質具有更高的導熱係數，使得電傳導過程中所產生的熱能，透過重分佈線路層41的路徑，將熱能引導到側邊，側邊與外界產生對流或傳導，加速熱能的逸散。
在某些實施例中，側壁26為一粗糙化表面。半導體基板21承受內部電路產生的熱能，粗糙化表面能增加散熱之表面積，使得增加側壁26與外界的對流，用以降低溫度，帶走熱能。避免半導體基板21過熱而導致電性偏離或雜訊過大。此外，粗糙化的側壁26提供側邊的散熱機制，將半導體基板21的熱能往側壁26發散，作為熱源的出口。在某些實施例中，粗糙化表面上能電鍍金屬，金屬具有較佳的導熱係數，增加側壁26與外界的對流。
此外，在某些實施例中，側壁26及背面28皆為粗糙表面可進一步增加散熱面積，與重分佈線路層41配合之下，使得散熱效果得以提升。相對於先前技術需要研磨背面並貼上散熱片，背面28不需要額外研磨或物件以降低成本與製程複雜度。背面28僅實施粗糙化處理，即可作為半導體基板21熱源的出口。此外，背面28佔大部分表面積，提供大面積的散熱區域。背面28提供半導體基板21一縱向的散熱機制，取代散熱片的功能。在某些實施例中，背面28的粗糙化表面上能電鍍金屬，金屬具有較佳的導熱係數，增加背面28與外界的對流。
圖2中的封裝結構10的製造方法，說明如下。先提供半導體基板21，半導體基板21為矽基板、切割後的晶粒或印刷電路板。之後，銲墊22形成於半導體基板21之一正面27。銲墊22之形成方式例如是利用化學氣相沉積(CVD)、電漿化學氣相沉積(PECVD)或物理氣相沉積(PVD)如濺鍍或蒸鍍形成在基板21上表面。銲墊22之材料為金屬，例如銀、銅等常使用於封裝之導電金屬。
鈍化層23形成於半導體基板21上方。接著圖案化該鈍化層23以暴露出一部分銲墊22。鈍化層23材料為鈍化材料，例如氧化物層、氮化物層。鈍化層23能利用濺鍍、蒸鍍或塗佈的方式形成。進一步形成圖案化光阻或遮罩層於鈍化層23上方，並進行蝕刻用以暴露一 部分銲墊22，隨後將光阻或遮罩層去除。
之後，沉積一圖案化層24以覆蓋該鈍化層23，其中，圖案化層24包含位於銲墊22上方的一預定尺寸開孔。圖案化層24的材料為聚合物介電層，但不限於此。圖案化層24可利用塗佈方式形成，利用塗佈機以旋轉塗佈將液態聚合物均勻塗佈在晶圓上，再經由利用光罩將聚合物介電層預定開孔的位置遮住而進行曝光，再經顯影移除未曝光的區域，使用烤箱加熱將聚合物加速固化至完全熟化的穩定狀態。鈍化層23與圖案化層24的末端切齊而形成端面25。
隨後，將第一介電層31形成於半導體基板21之正面27上方。第一介電層31可為(但不限制於)氧化物層、氮化物層或聚合層。第一介電層31的形成方式可依需求調整，如CVD、PVD製程，或旋轉塗佈(spin coating)的方式。第一介電層31覆蓋圖案化層24與半導體基板21。第一介電層31具有一延伸介電層32部分。延伸介電層32覆蓋端面25並且與側壁26切齊。第一介電層31順應高低差別而具有一近似梯形分布。
隨後，形成重分佈線路層41連接於銲墊22並覆蓋第一介電層31及半導體基板21之外圍。並且重分佈線路層41與半導體基板21之側壁26切齊。重分佈線路層41的一主要功能是提供電流流通路徑。重分佈線路層41之材質可為銅、銀、鈀、金或其合金。重分佈線路層41可利用CVD、PVD方式形成。
形成第二介電層51於重分佈線路層41上方。隨後利用光阻或光罩定義開口55，並藉由乾、濕式蝕刻、或光學蝕刻方式暴露出一部分重分佈線路層41。在某些實施例中，球下金屬層(UBM,Under Bump Metallization)形成於開口55內，UBM層包括至少兩層金屬層，即黏接層及晶種層。該黏接層與重分佈線路層41直接接觸且通常由鈦或鎢化鈦(TiW)製成，以便提供重分佈線路層41與焊球61之間的機械 上較佳之連接及較好的黏著性。該晶種層定位於該黏接層上且由金、銅、鎳或合金組成。UBM層由金屬濺鍍程序、氣相沈積程序或金屬膏印刷程序形成。
之後，形成焊球61於UBM層上或直接形成於重分佈線路層41上。本實施例中焊球61可為錫球，而此步驟可為一植球步驟，植球方式例如但不限於網版印刷、蒸鍍、電鍍、落球、噴球等。
根據另一實施例，圖3顯示為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構11之示意性剖視圖。封裝結構11的結構及製造方法相似於封裝結構10。封裝結構10與封裝結構11的差別在於一圖案化重分佈線路層42，重分佈線路層42具有一開口56。開口55對準開口56。兩開口提供焊球61擁有更深層的容置空間，能穩定焊球61。同時重分佈線路層42仍具有側邊散熱效果。搭配具有粗糙表面的側壁26和背面28，使得具有更佳的側邊及背面散熱效率。
根據另一實施例，圖4為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構14之示意性剖視圖。封裝結構14的結構及製造方法相似於封裝結構10。封裝結構14與封裝結構10的差別在於一重分佈線路層43包含一開口57。開口57遠離開口55，並且填充一第二介電層52，使得開口57作為阻斷半導體基板21與外界的電性連接。此外，第一介電層31包含一延伸介電層33。延伸介電層33覆蓋端面25與部分半導體基板21，其中，僅覆蓋半導體基板21外圍一部分，並未與側壁26切齊。如此，使得重分佈線路層43之一端能接觸半導體基板21外圍。重分佈線路層43與半導體基板21的更多接觸能帶走更多基板熱能。同時，重分佈線路層43與具有粗糙表面的側壁26和背面28提供側邊、背面的散熱效果。
根據另一實施例，圖5為本揭露一實施例之一具有側邊散熱設計之扇出封裝結構15之示意性剖視圖。封裝結構15的結構及製造方 法相似於封裝結構10。封裝結構15與封裝結構10的差別在於重分佈線路層43包含開口57。開口57遠離開口55，並且填充一第二介電層53，使得開口57作為阻斷半導體基板21與外界的電性連接。此外，第二介電層53覆蓋部分重分佈線路層43，並未與側壁26切齊。如此，末端的重分佈線路層43直接暴露在環境中，增加與外界的對流，加速散熱。同時，具有粗糙表面的側壁26和背面28提供側邊、背面的散熱效果。
圖6為本揭露一實施例之一具有散熱圖案之封裝結構16、17之上視圖。如左圖所示，重分佈線路層位於半導體基板外圍而形成一散熱圖案45。散熱圖案45位於半導體基板或晶粒上方，其中散熱圖案45係由一重分佈線路層由內部連接銲墊，散熱圖案45位於半導體基板之外圍並且切齊半導體基板之側壁26。本實施例中，散熱圖案45為一連續環狀結構分布於半導體基板外圍。封裝結構16包含焊球61，其相對位置如圖6之左圖所示。某些實施例中，散熱圖案45由內部連接焊球61，某些實施例中，兩者並未電性連接。其散熱圖案45提供側邊散熱途徑。同時，具有粗糙化表面的側壁26亦具有側邊散熱效果。
圖6之右圖為一具有散熱圖案之封裝結構17之上視圖。重分佈線路層位於半導體基板外圍而形成一散熱圖案46。散熱圖案46連接焊球61，散熱圖案46能導引焊球61所產生的熱能。散熱圖案46為非連續，其散熱圖案46的配置能決定熱能逸散的路徑。散熱圖案46分布於半導體基板外圍並且切齊半導體基板之側壁26。同時，粗糙化的側壁26亦具有側邊散熱效果。故藉由散熱圖案46與外界接觸，將焊球61在電性操作時產生的熱能逸散到封裝結構17的四周。由於散熱圖案46為金屬，且金屬具有較高導熱係數，容易傳導熱能，使得中心的熱能藉由散熱圖案46傳遞，並作為熱源出口。同時，粗糙化的側壁26亦提供中心的熱能往側邊逸散，增加散熱效率。在某些實施例中，在粗糙化的側壁26上電鍍金屬，能提升散熱效能。
圖7-8為本揭露一實施例之形成粗糙化側壁26之示意圖。根據某些實施例中，如圖7所示，在焊球61完成後，附著一保護層71於半導體基板21之正面27及第二介電層51上，僅露出半導體基板21之背面28及側壁26。保護層71為例如一乾膜(dry film)、光阻、或膠帶。隨後，沈浸半導體基板21之背面28及側壁26於蝕刻液中，並且濕式微蝕刻半導體基板21之側壁26及背面28。使得背面28及側壁26形成粗糙化表面，能作為散熱途徑。在某些實施例中，進一步無電極電鍍半導體基板21之側壁26及/或背面28，使得電鍍金屬附著於側壁26及/或背面28，以增加散熱效果。
粗糙化的背面28能作為散熱途徑。與先前技術不同，本揭露不需要進一步研磨、塗上散熱膏或黏上散熱片，使得大幅減少成本。
根據某些實施例中，如圖8所示，在焊球61完成後，附著一保護層71於半導體基板21之正面27及第二介電層51上，僅露出所述半導體基板21之背面28及側壁26。此外，形成一保護層72在半導體基板21之背面28，僅露出側壁26。隨後，進一步沈浸半導體基板21於蝕刻液中，並且濕式微蝕刻半導體基板21之側壁26。因此，側壁26具有粗糙化表面，能作為散熱途徑。在某些實施例中，無電極電鍍半導體基板21之側壁26，以增加散熱效果。
雖然已詳細地描述了本發明及其優勢，但應理解，在不脫離如由隨附申請專利範圍界定的本發明之精神及範疇之情況下，本文中可進行各種改變、替代及更改。舉例而言，上文所論述之程序中之多者可以不同方法來實施且可由其他程序或其組合替代。
此外，本申請案之範疇不應侷限於說明書中所描述之程序、機器、製造、物質組成、手段、方法及步驟之特定實施例。如一般熟習此項技術者將易於自本發明之揭示內容瞭解，根據本發明，可 利用當前存在或日後將開發出的執行與本文中所描述之相應實施例大體上相同的功能或達成與本文中所描述之相應實施例大體上相同的結果之程序、機器、製造、物質組成、手段、方法或步驟。因此，隨附申請專利範圍意欲在其範疇中包括此等程序、機器、製造、物質組成、手段、方法或步驟。
10‧‧‧封裝結構
21‧‧‧半導體基板
22‧‧‧銲墊
23‧‧‧鈍化層
24‧‧‧圖案化層
25‧‧‧端面
26‧‧‧側壁
27‧‧‧正面
28‧‧‧背面
31‧‧‧第一介電層
32‧‧‧延伸介電層
41‧‧‧重分佈線路層
51‧‧‧第二介電層
55‧‧‧開口
61‧‧‧焊球

Claims (11)

  1. 一種具有側邊散熱設計之扇出封裝結構，包括：一半導體基板；一銲墊位於所述半導體基板上；以及一重分佈線路層連接於所述銲墊並位於所述半導體基板上方，其中該重分佈線路層為環狀結構且該重分佈線路層之一端往所述半導體基板之一側壁延伸，且所述端與所述側壁切齊。
  2. 根據請求項1的結構，其中所述側壁為一粗糙化表面。
  3. 根據請求項1的結構，其中所述半導體基板之背面為一粗糙化表面。
  4. 根據請求項1的結構，其中所述重分佈線路層位於所述半導體基板外圍。
  5. 一種具散熱圖案之封裝結構，包含：一半導體基板；一銲墊位於所述半導體基板上；以及一散熱圖案位於所述半導體基板上方，其中所述散熱圖案係由一重分佈線路層連接於所述銲墊並位於所述半導體基板之外圍並且切齊所述半導體基板之一側壁所組成，其中所述散熱圖案為一圍繞該半導體基板外圍之環狀結構。
  6. 一種具有側邊散熱設計之扇出封裝結構的製造方法，其步驟包含：提供一半導體基板具有一銲墊位於所述半導體基板之一正面之上方；形成一第一介電層位於所述半導體基板之所述正面上方； 以及形成一重分佈線路層連接於所述銲墊並覆蓋所述第一介電層及所述半導體基板之外圍，使所述重分佈線路層形成一環狀結構並與所述半導體基板之一側壁切齊。
  7. 根據請求項6的方法，進一步包含附著一保護層於所述半導體基板之所述正面及所述重分佈線路層上僅露出所述半導體基板之一背面及所述側壁。
  8. 根據請求項7的方法，進一步包含沈浸所述半導體基板之所述背面及所述側壁於蝕刻液中，並且濕式微蝕刻所述半導體基板之所述側壁及所述背面。
  9. 根據請求項7的方法，進一步包含形成一保護層在所述半導體基板之所述背面。
  10. 根據請求項9的方法，進一步包含沈浸所述半導體基板於蝕刻液中，並且濕式微蝕刻所述半導體基板之所述側壁。
  11. 根據請求項8或10的方法，進一步包含無電極電鍍所述半導體基板之所述側壁及/或所述背面。
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US11195809B2 (en) 2018-12-28 2021-12-07 Stmicroelectronics Ltd Semiconductor package having a sidewall connection
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