TW202115852A - 半導體裝置及製造方法 - Google Patents

半導體裝置及製造方法 Download PDF

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TW202115852A
TW202115852A TW109137885A TW109137885A TW202115852A TW 202115852 A TW202115852 A TW 202115852A TW 109137885 A TW109137885 A TW 109137885A TW 109137885 A TW109137885 A TW 109137885A TW 202115852 A TW202115852 A TW 202115852A
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Taiwan
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substrate
semiconductor device
die
lateral
pillar
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TW109137885A
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TWI816063B (zh
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金進勇
鄭季洋
元秋亨
安曠黃
林河貞
李泰勇
貝俊明
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美商艾馬克科技公司
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Abstract

本發明提供一種半導體裝置及一種製造半導體裝置的方法。作為非限制性範例，本發明的各種態樣提供一種具有小尺寸及細節距的可堆疊半導體裝置以及其製造方法。

Description

半導體裝置及製造方法
本發明關於一種半導體裝置及一種製造半導體裝置的方法。
目前的半導體裝置及用於製造半導體裝置的方法是不足的，舉例來說，引起過低的靈敏度、過多的成本、減低的可靠性，或過大的封裝尺寸。藉由比較常規及傳統做法與如在本申請案的剩餘部分中參考附圖所闡述的本發明，此類做法的另外限制及缺點對於所屬領域的技術人員來說將變得顯而易見。
本發明提供一種半導體裝置及一種製造半導體裝置的方法。作為非限制性範例，本發明的各種態樣提供一種具有小尺寸及細節距的可堆疊半導體裝置以及其製造方法。
以下論述藉由提供本發明的範例來呈現本發明的各種態樣。此類範例是非限制性的，且因此，本發明的各種態樣的範圍應未必受到所提供範例的任何特定特性限制。在以下論述中，用語“舉例來說”、“例如”及“示範性”是非限制性的，且與“作為範例而非限制”、“舉例來說而非限制”及其類似者大體上同義。
如本文中所利用，“及/或”意指由“及/或”接合的列表中的項目中的任何一或多者。作為一範例，“x及/或y”意指三元素集合{(x), (y), (x, y)}中的任何元素。換句話說，“x及/或y”意指“x及y中的一或兩者”。作為另一範例，“x、y及/或z”意指七元素集合{(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}中的任何元素。換句話說，“x、y及/或z”意指“x、y及z中的一或多者”。
本文中所使用的術語是僅出於描述特定範例的目的，且並不意欲限制本發明。如本文中所使用，單數形式也意欲包含複數形式，除非上下文另有清晰指示。將進一步理解，術語“包括”、“包含”、“具有”及其類似者在用於本說明書中時表示所陳述特徵、整數、步驟、操作、元件及/或元件的存在，但並不排除一或多個其它特徵、整數、步驟、操作、元件、元件及/或其群組的存在或添加。
將理解，儘管術語第一、第二等等可在本文中用以描述各種元件，但這些元件不應受到這些術語限制。這些術語僅用以區分一個元件與另一元件。因此，舉例來說，在不脫離本發明的教示的情況下，下文所論述的第一元件、第一元件或第一區段可被稱為第二元件、第二元件或第二區段。相似地，諸如“上部”、“上方”、“下部”、“下方”、“側”、“橫向”、“水準”、“垂直”及其類似者的各種空間術語可用來以相對方式區分一個元件與另一元件。然而，應理解，在不脫離本發明的教示的情況下，元件可以不同方式而定向，舉例來說，半導體裝置可側向地轉動使得其“頂部”表面水準地面向且其“側”表面垂直地面向。
還將理解，術語耦合、連接、附接及其類似者包含直接及間接（例如，用介入元件）耦合、連接、附接等等，除非另有明確指示。舉例來說，如果元件A耦合到元件B，那麼元件A可藉由中間信號分配結構而間接地耦合到元件B，元件A可直接地耦合到元件B（例如，直接地黏附到、直接地焊接到、藉由直接金屬到金屬接合而附接）…等等。
在附圖中，可出於清晰起見而誇示結構、層、區域等等的尺寸（例如，絕對及/或相對尺寸）。雖然此類尺寸通常指示範例實施方案，但其並非限制性的。舉例來說，如果將結構A說明為大於區域B，那麼此通常指示範例實施方案，但通常並不要求結構A大於結構B，除非另有指示。另外，在附圖中，類似參考數字可在整個論述中代表類似元件。
本發明的各種態樣提供一種半導體裝置及其製造方法，其特徵可為小佔據面積、小厚度及細節距圖案間距。舉例來說，半導體裝置可為可堆疊的。
本發明的各種態樣提供一種半導體裝置，其包括基板、耦合到基板的一個表面的半導體晶粒、耦合到基板的表面的金屬柱，及封裝半導體晶粒及金屬柱且曝露金屬柱的囊封物。舉例來說，金屬柱可沿著囊封物的孔垂直地形成。
本發明的各種態樣提供一種製造半導體裝置的方法，所述方法包括：提供包含金屬柱的載體基板及環繞金屬柱的絕緣構件；在絕緣構件表面上塗布及圖案化光阻；對金屬柱執行鍍覆；將金屬柱耦合到基板；去除光阻及載體基板；及形成封裝金屬柱的囊封物。
本發明的各種態樣提供一種製造半導體裝置的方法，所述方法包括：在載體基板的表面上提供種子層及光阻；藉由在光阻的圖案中執行鍍覆而形成金屬柱；去除光阻；將金屬柱耦合到基板；形成封裝金屬柱的囊封物；及去除載體基板。
舉例來說，本發明的各種態樣可提供一種半導體裝置，其包括在基板的頂部表面上具有細節距的金屬柱，其中金屬柱曝露到囊封物外部，由此提供具有小尺寸及細節距圖案間距的可堆疊半導體裝置。舉例來說，半導體裝置還可包括耦合到金屬柱的上部基板。
現在將參考附圖來詳細地描述本發明的各種態樣，使得其可容易由所屬領域的技術人員實踐。
圖1展示根據本發明的各種態樣的半導體裝置的橫截面圖。舉例來說，範例半導體裝置100可包括基板110、半導體晶粒120、金屬柱130、囊封物140及導電球150。
舉例來說，基板110可由一般印刷電路板（PCB）或引線框架形成。而且，基板110可以半導體製程而由基於矽的內建基板形成。儘管未單獨地展示，但舉例來說，基板110可包含一或多個導電層（例如，金屬等等），其電耦合形成在基板的頂部及底部表面上的襯墊，從而提供上覆半導體晶粒120或金屬柱130以電連接到底層導電球150。舉例來說，基板110的此類導電層可包括銅（Cu）、鋁（Al）、其合金等等，但本發明的範圍並不限於此情形。另外，為了增強連線性，可另外將諸如金（Au）的金屬施加到襯墊。
舉例來說，半導體晶粒120可包括與半導體晶片分離（或單切或分割）的積體電路晶片。半導體晶粒120可包括多種不同類型的電路中的任一者，舉例來說，中央處理單元（CPU）、數位訊號處理器（DSP）、網路處理器、功率管理單元、音訊處理器、RF電路、無線基帶(wireless baseband)晶片上系統（SoC）處理器、感測器、專用積體電路等等。
舉例來說，半導體晶粒120可藉由導電襯墊121將電信號輸入到第一表面120-1（例如，底部表面等等）及/或從第一表面120-1（例如，底部表面等等）輸出電信號。舉例來說，導電襯墊121可連接到半導體晶粒120的內部圖案（或導電層），且可通常包含鋁（Al）及/或其它導電材料。另外，半導體晶粒120的導電襯墊121可藉由導電黏著構件120a（例如，包括焊料、導電環氧樹脂等等）而電連接到形成在基板110的頂部表面上的球（或襯墊或其它互連結構）。應注意，還可利用直接金屬到金屬（例如，無焊）金屬間接合。舉例來說，半導體晶粒120可包括使除了導電襯墊121被曝露的區域以外的區域絕緣的鈍化層。儘管論述僅一個導電襯墊121，但可存在任何數目個此類導電襯墊。
舉例來說，半導體晶粒120可包括與第一表面120-1（例如，底部表面）相對的第二表面122（例如，頂部表面）。舉例來說，第二表面122可曝露到外部（例如，從囊封材料曝露）。舉例來說，第二表面122可與囊封物140的頂部表面具有相同高度，囊封物140的頂部表面將被曝露到囊封物140外部。在這個範例配置中，半導體晶粒120可經配置以促進熱從半導體晶粒120散發到外部。
金屬柱130從基板110的頂部表面突出。舉例來說，金屬柱130可由金屬（例如，銅等等）製成，且可定位在除了半導體晶粒120被定位的區域以外的區域上。舉例來說，金屬柱130可藉由導電黏著構件130a（例如，包括焊料等等）而電連接到基板110。另外，金屬柱130可從囊封物140的上部部分（例如，從上部表面）曝露。在一些狀況下，金屬柱130的末端131可從基板110延伸得比從囊封物140延伸得更遠，舉例來說，從囊封物140的頂部表面突出。當將另一半導體裝置堆疊在半導體裝置100上時，所述半導體裝置可藉由金屬柱130而彼此電連接。
在範例實施方案中，舉例來說，金屬柱130的寬度可在約10μm到約15μm的範圍內。因此，與利用直徑為約350μm的焊料凸塊的狀況相比較，金屬柱130可以細節距而實施在基板110上，由此縮減包含基板110的半導體裝置100的總尺寸。另外，許多金屬柱130可定位在具有相同小尺寸（及/或多種尺寸）的基板110上，在設計半導體裝置100的態樣可得到較高自由度。
舉例來說，囊封物140可形成在基板110的第一表面110-1（例如，頂部表面）上以環繞半導體晶粒120及金屬柱130（例如，以環繞及/或接觸其橫向表面等等）。舉例來說，囊封物140可由多種材料中的任一者（例如，一般樹脂等等）製成，且可在固定半導體晶粒120及金屬柱130的位置的同時保護半導體晶粒120及金屬柱130免受外部衝擊。
導電球150（或多種互連結構中的任一者，舉例來說，導電凸塊、導電支柱或柱等等）可形成在基板110之下（例如，形成在圖1中的基板110的底部表面上）。舉例來說，導電球150可由焊料製成，且可耦合到基板110的底部表面上的互連結構（例如，襯墊、跡線、球、凸塊等等）。導電球150可稍後連接到外部電路以提供用於將電信號輸入到基板110及/或從基板110輸出電信號的路徑。
如上文所描述，在範例半導體裝置100中，具有細節距的金屬柱130定位（或形成）在基板110的頂部表面上且曝露到囊封物140外部，由此實施細節距且提供另一半導體裝置在半導體裝置100上的堆疊（或反之亦然），同時縮減總尺寸。
在範例實施方案中，另一基板或插入件可堆疊（或形成）在半導體晶粒120及/或囊封物140的頂部側上。在圖2處提供此類實施方案的範例，如現在將描述。
圖2展示根據本發明的各種態樣的半導體裝置的橫截面圖。舉例來說，範例半導體裝置200可包括基板110、半導體晶粒120、金屬柱130、上部基板230、囊封物140，及導電球150。與圖1的範例半導體裝置100的功能元件相同的功能元件是由相同參考數位表示，且以下描述將大體上集中於圖2的範例半導體裝置200與圖1的範例半導體裝置100之間的差異。
上部基板230是沿著囊封物140的頂部表面而定位。另外，上部基板230包括多個導電圖案231（或其部分），其從上部基板230的底部表面（或在上部基板230的底部表面處）曝露到囊封物140的頂部表面。上部基板230可藉由從上部基板230的頂部表面（或在上部基板230的頂部表面處）曝露的導電圖案231（或其部分）而電連接到堆疊在上部基板230上的半導體裝置。另外，導電圖案231可在範例半導體裝置200的各種區域（舉例來說，除了半導體晶粒120被定位的區域以外的區域）中電連接到金屬柱130。舉例來說，上部基板230可藉由金屬柱130而電連接到基板110。
如上文所描述，範例半導體裝置200可經形成以藉由提供金屬柱130而不對囊封物140執行鐳射鑽孔（或燒蝕）而具有細節距圖案（例如，導體、焊盤、跡線、襯墊等等）。另外，範例半導體裝置200可經配置以提供另一半導體裝置在半導體裝置200上的堆疊（或反之亦然），舉例來說，藉由使上部基板230連接到金屬柱130。
在下文中，將描述根據本發明的一實施例的製造半導體裝置的範例方法。舉例來說，範例方法可用以製造本文中所論述的範例半導體裝置中的任一者或全部，或其任何部分。
圖3A到圖3F展示說明根據本發明的各種態樣的製造半導體裝置的範例方法的視圖。
參看圖3A，根據本發明的各種態樣的製造半導體裝置的範例方法可包括在載體基板10上提供（或形成）金屬柱130，及提供（或形成）覆蓋金屬柱130的絕緣構件20。舉例來說，載體基板10可包括金屬、介電材料、半導體材料等等。舉例來說，絕緣構件20可藉由模製而形成，但本發明的態樣並不限於此情形。舉例來說，絕緣構件20可藉由旋塗、氣相沉積、印刷等等而形成。另外，可在載體基板10上圖案化絕緣構件20，且可（舉例來說）使用載體基板10作為種子層來執行電鍍或無電式鍍覆，由此形成金屬柱130。舉例來說，金屬柱130可由銅（Cu）、鋁（Al）等等製成。舉例來說，金屬柱130可藉由（舉例來說）在種子層上、在載體基板10的導電圖案（例如，襯墊、焊盤、跡線等等）上、在種子層上等等鍍覆金屬柱130而形成。
參看圖3B，在絕緣構件20上形成（例如，塗布等等）且圖案化光阻30（或光阻層），且對由光阻30的圖案曝露的區域執行電鍍或無電式鍍覆，由此增加金屬柱130的高度。舉例來說，此類鍍覆物可為與金屬柱130相同的材料及/或不同的材料。而且，導電黏著構件130a可進一步形成在金屬柱130上（例如，除了將金屬添加到金屬柱130以外及/或代替將金屬添加到金屬柱130）。舉例來說，導電黏著構件130a可由一般焊接材料製成，但本發明的態樣並不限於此情形。
參看圖3C，去除光阻30（或光阻層）及載體基板10。舉例來說，可藉由一般灰化製程來去除光阻30，且可藉由研磨（例如，帶材研磨等等）、藉由剝離膠帶（如果膠帶形成在光阻30與載體基板10之間的介面處）、藉由化學/機械平坦化等等來去除載體基板10。因此，可曝露形成在金屬柱130上的導電黏著構件130a及金屬柱130（或其部分）。
參看圖3D，在導電黏著構件130a被翻轉以面向下的狀態中，金屬柱130耦合到基板110。在範例實施方案中，基板110可處於半導體晶粒120在金屬柱130之前耦合到基板110的狀態，且導電黏著構件130a可相對於形成在基板110上的圖案（例如，跡線、襯墊、焊盤等等）而對準，由此使金屬柱130及基板110彼此耦合。舉例來說，此類耦合可藉由熱壓接合、迴焊(mass reflow)、直接金屬到金屬（例如，無焊）接合、導電黏著劑等等而執行。
參看圖3E，囊封物140（或囊封材料）可填充絕緣構件20與基板110之間的區域以封裝半導體晶粒120及金屬柱130。囊封物140可經形成以從至少一個側（例如，從橫向側等等）封裝內部元件。另外，儘管未另外地展示，但分開的底部填充還可任選地在囊封物140之前形成在半導體晶粒120的導電襯墊121周圍。
另外，參看圖3E，在形成囊封物140之後可去除絕緣構件20。舉例來說，可藉由研磨（例如，帶材研磨等等）、蝕刻、化學/機械平坦化等等來去除絕緣構件20。因此，半導體晶粒120的頂部表面122可從囊封物140的上部部分（例如，從上部表面）曝露。在這種狀況下，舉例來說，歸因於去除絕緣構件20時的物理性質差異，金屬柱130（例如，其末端表面）還可從囊封物140的上部部分曝露及/或還可從囊封物140的頂部表面向上突出。
參看圖3F，導電球150（或其它互連結構，舉例來說，柱、支柱、凸塊等等）形成在基板110的底部表面上。導電球150可經形成以對應於基板110的底部表面上的圖案（例如，跡線、焊盤、襯墊、凸塊下金屬化層等等），由此提供用於連接到外部電路的路徑。
在下文中，將描述根據本發明的一實施例的半導體裝置的另一製造方法。舉例來說，範例方法可用以製造本文中所論述的範例半導體裝置中的任一者或全部，或其任何部分。
圖4A到圖4I展示說明根據本發明的各種態樣的製造半導體裝置的方法的視圖。舉例來說，所述範例方法可與圖3A到圖3F所說明的範例方法共用任何或所有特性。
參看圖4A及圖4B，根據本發明的各種態樣的製造半導體裝置的範例方法可包括在載體基板10的表面上形成種子層11及光阻12（或光阻層）。舉例來說，種子層11可由諸如銅（Cu）的金屬或金屬薄板形成，但本發明的態樣並不限於此情形。
參看圖4C，舉例來說，藉由掩蔽而在光阻12中形成圖案。舉例來說，圖案可經配置以曝露對應於稍後待形成的金屬柱130的區域。
參看圖4D，使用種子層11作為種子而執行電鍍，由此形成鍍覆層13。鍍覆層13可形成在光阻12的圖案12a中及/或之外，舉例來說，形成在由光阻12的圖案12a曝露的種子層11的部分上。應注意，鍍覆層13可形成在多種導電圖案（例如，襯墊、焊盤、跡線等等）中的任一者上。舉例來說，鍍覆層13可與被鍍覆有鍍覆層13的導體一體地形成。
參看圖4E，可對光阻12及鍍覆層13執行研磨（例如，帶材研磨等等）或一般薄化。另外，由研磨引起的鍍覆層13可構成金屬柱130。然而，任選地執行這個步驟。如果不執行這個步驟，那麼鍍覆層13可與金屬柱130相同。
參看圖4F，可去除光阻12。如上文所描述，舉例來說，可藉由灰化來去除光阻12，由此曝露種子層11及金屬柱130。
參看圖4G，導電黏著構件130a形成在金屬柱130之下，且金屬柱130及基板110可藉由導電黏著構件130a而彼此耦合。應注意，舉例來說，導電黏著構件130可如本文中關於圖3所論述而形成在金屬柱130上，可在附接金屬柱130之前形成在基板110上，等等。此處，半導體晶粒120可在金屬柱130之前耦合到基板110。舉例來說，導電黏著構件130a可相對於形成在基板110上的圖案（例如，跡線、襯墊、焊盤等等）而對準，由此使金屬柱130及基板110彼此耦合。
參看圖4H，囊封物140（例如，模具材料、一般介電材料等等）可經形成（例如，模製、旋塗、氣相沉積等等）以填充種子層11與基板110之間的區域，舉例來說，以封裝半導體晶粒120及金屬柱130（例如，其橫向表面等等）。舉例來說，囊封物140可經形成以從至少一個側封裝內部元件。另外，儘管未另外地展示，但分開的底部填充還可任選地在囊封物140之前形成在半導體晶粒120的導電襯墊121周圍。
另外，參看圖4H，在形成囊封物140之後可去除載體基板10及種子層11。舉例來說，可藉由研磨（例如，帶材研磨等等）、蝕刻、化學/機械平坦化、一般平坦化等等來去除絕緣構件20。因此，半導體晶粒120的頂部表面122可從囊封物140的上部部分（例如，從上部表面）曝露。在這種狀況下，舉例來說，歸因於去除絕緣構件20時的物理性質差異，金屬柱130（例如，其頂部表面）還可從囊封物140的上部部分曝露及/或還可經形成以從囊封物的頂部表面向上突出。
參看圖4I，導電球150（或其它互連結構，舉例來說，柱、支柱、凸塊等等）形成在基板110的底部表面上。導電球150可經形成以對應於形成在基板110的底部表面上的圖案（例如，跡線、焊盤、襯墊、凸塊下金屬化層等等），由此提供用於連接到外部電路的路徑。
在下文中，將描述根據本發明的另一實施例的半導體裝置的製造方法。舉例來說，範例方法可用以製造本文中所論述的範例半導體裝置中的任一者或全部，或其任何部分。
圖5A到圖5F展示說明根據本發明的各種態樣的製造半導體裝置的方法的視圖。舉例來說，所述範例方法可與圖3A到圖3F所說明的範例方法及/或與圖4A到圖4I所說明的範例方法共用任何或所有特性。
參看圖5A，根據本發明的各種態樣的製造半導體裝置的範例方法可包括在載體基板10上提供（或形成）導電圖案231（例如，跡線、焊盤、襯墊等等）及金屬柱130，及提供（或形成）覆蓋導電圖案231及金屬柱130之絕緣構件20。舉例來說，絕緣構件20可藉由模製而形成，但本發明的態樣並不限於此情形。舉例來說，絕緣構件20可藉由旋塗、氣相沉積、印刷等等而形成。
另外，在範例實施方案中，可首先在載體基板10上圖案化絕緣構件20，且可（舉例來說）使用載體基板10作為種子層來執行電鍍或無電式鍍覆，由此形成導電圖案231。接下來，在圖案化絕緣構件20之後，可（舉例來說）使用導電圖案231（例如，襯墊、焊盤、跡線等等）及/或載體基板10作為種子層來形成鍍覆式金屬柱130。舉例來說，鍍覆層13可與被鍍覆有鍍覆層13的導體（例如，種子層、襯墊、焊盤、跡線等等）一體地形成。
參看圖5B，在絕緣構件20上形成（例如，塗布等等）且圖案化光阻30（或光阻層），且對由光阻30的圖案曝露的區域執行電鍍或無電式鍍覆，由此增加金屬柱130的高度。舉例來說，此類鍍覆物可為與金屬柱130相同的材料及/或不同的材料。而且，導電黏著構件130a可進一步形成在金屬柱130上（例如，除了將金屬添加到金屬柱130以外及/或代替將金屬添加到金屬柱130）。舉例來說，導電黏著構件130a可由一般焊接材料製成，但本發明的態樣並不限於此情形。
參看圖5C，去除光阻30（或光阻層）及載體基板10。舉例來說，可藉由一般灰化製程來去除光阻30，且可藉由研磨（例如，帶材研磨等等）或藉由剝離膠帶（如果膠帶形成在光阻30與載體基板10之間的介面處）、藉由化學/機械偏振等等來去除載體基板10。因此，可曝露形成在金屬柱130上的導電黏著構件130a及金屬柱130（或其部分）。以此類方式，可形成具有導電圖案231的範例上部基板230及金屬柱130。在這個步驟中，還可去除絕緣構件20的部分，由此進一步曝露金屬柱130。在範例實施方案中，如果縮減絕緣構件20的厚度且增加光阻30的厚度，那麼可藉由去除光阻30而曝露金屬柱130的相當大的部分。
參看圖5D，在導電黏著構件130a被翻轉以面向下的狀態中，金屬柱130耦合到基板110。在範例實施方案中，基板110可處於半導體晶粒120在金屬柱130之前耦合到基板110的狀態，且導電黏著構件130a可相對於形成在基板110上的圖案（例如，跡線、襯墊、焊盤等等）而對準，由此使金屬柱130及基板110彼此耦合。舉例來說，此類耦合可藉由熱壓接合、迴焊(mass reflow)、直接金屬到金屬（例如，無焊）接合、導電黏著劑等等而執行。
另外，參看圖5D，上部基板230的導電圖案231可向上曝露。因此，待在後續步驟中堆疊的半導體裝置可容易電連接到導電圖案231。
參看圖5E，囊封物140（或囊封材料）可填充上部基板230與基板110之間的區域以封裝半導體晶粒120及金屬柱130。囊封物140可經形成以從一個側（例如，從橫向側等等）封裝內部元件。另外，儘管未另外地展示，但分開的底部填充還可任選地在囊封物140之前形成在半導體晶粒120的導電襯墊121周圍。
參看圖5F，導電球150（或其它互連結構，舉例來說，柱、支柱、凸塊等等）形成在基板110的底部表面上。導電球150可經形成以對應於基板110的底部表面上的圖案（例如，跡線、焊盤、襯墊、凸塊下金屬化層等等），由此提供用於連接到外部電路的路徑。
雖然已參考某些支援範例及/或實施方案而描述根據本發明的各種態樣的半導體裝置及其製造方法，但所屬領域的技術人員將理解，本發明的範圍並不限於所揭示的特定範例，而是本發明將包含屬於所附申請專利範圍的範疇內的所有實施例、範例及實施方案。
本文中的論述包含展示電子裝置組合件及其製造方法的各種部分的眾多說明性附圖。出於說明清晰起見，此類附圖並未展示每一範例組合件的所有態樣。本文中所提供的任何範例組合件及/或方法可與本文中所提供的任何或所有其它組合件及/或方法共用任何或所有特性。
總之，本發明的各種態樣提供一種半導體裝置及一種製造半導體裝置的方法。作為非限制性範例，本發明的各種態樣提供一種具有小尺寸及細節距的可堆疊半導體裝置以及其製造方法。雖然已參考某些態樣及範例而描述前述內容，但所屬領域的技術人員將理解，在不脫離本發明的範圍的情況下，可進行各種改變且可取代等效者。另外，在不脫離本發明的範圍的情況下，可進行許多修改以使特定情形或材料適應於本發明的教示。因此，希望本發明不限於所揭示的特定範例，而是本發明將包含屬於所附申請專利範圍的範疇內的所有範例。
10:載體基板 11:種子層 12:光阻 12a:圖案 13:鍍覆層 20:絕緣構件 30:光阻 100:半導體裝置 110:基板 110-1:基板的第一表面 120:半導體晶粒 120-1:半導體晶粒的第一表面 120a:導電黏著構件 121:導電襯墊 122:第二表面 130:金屬柱 130a:導電黏著構件 131:金屬柱末端 140:囊封物 150:導電球 200:半導體裝置 230:上部基板 231:導電圖案
[圖1]展示根據本發明的各種態樣的半導體裝置的橫截面圖；
[圖2]展示根據本發明的各種態樣的半導體裝置的橫截面圖；
[圖3]A到圖3F展示說明根據本發明的各種態樣的製造半導體裝置的方法的視圖；
[圖4]A到圖4I展示說明根據本發明的各種態樣的製造半導體裝置的方法的視圖；且
[圖5]A到圖5F展示說明根據本發明的各種態樣的製造半導體裝置的方法的視圖。
100:半導體裝置
110:基板
110-1:基板的第一表面
120:半導體晶粒
120-1:半導體晶粒的第一表面
120a:導電黏著構件
121:導電襯墊
122:第二表面
130:金屬柱
130a:導電黏著構件
131:金屬柱末端
140:囊封物
150:導電球

Claims (20)

  1. 一種半導體裝置，其包括： 基板，其具有頂部基板側、底部基板側，及在所述頂部基板側與所述底部基板側之間延伸的橫向基板側； 半導體晶粒，其具有頂部晶粒側、底部晶粒側，及在所述頂部晶粒側與所述底部晶粒側之間延伸的橫向晶粒側，其中所述底部晶粒側耦合到所述頂部基板側； 黏著構件，其包括焊料或環氧樹脂； 金屬柱，其具有頂部柱末端、底部柱末端，及在所述頂部柱側與所述底部柱末端之間延伸的橫向柱側，其中所述底部柱側是用黏著構件耦合到所述頂部基板側，且所述金屬柱被橫向定位在由所述半導體晶粒覆蓋的所述頂部基板側的區域外部；以及 囊封材料，其封裝所述橫向晶粒側的至少一部分及所述橫向柱側的至少一部分。
  2. 如請求項1所述的半導體裝置，其中所述黏著構件包括焊料，且所述頂部柱末端是無焊料的。
  3. 如請求項1所述的半導體裝置，其中所述金屬柱包括銅柱。
  4. 如請求項1所述的半導體裝置，其中所述金屬柱沒有寬於15 µm。
  5. 如請求項1所述的半導體裝置，其包括上部基板，所述上部基板具有頂部上部基板側、耦合到所述頂部晶粒側和耦合到所述囊封材料的底部上部基板側，及在所述頂部上部基板側與所述底部上部基板側之間延伸的橫向上部基板側，其中所述上部基板包括耦合到所述頂部柱末端的導電圖案和橫向地圍繞所述導電圖案的模具材料。
  6. 如請求項5所述的半導體裝置，其中所述導電圖案的一部分是直接垂直地在所述頂部晶粒側上方。
  7. 如請求項5所述的半導體裝置，其中所述金屬柱與所述導電圖案一體地形成而沒有中介材料，並且所述頂部柱末端完全由所述導電圖案接觸並且覆蓋。
  8. 如請求項7所述的半導體裝置，其中所述金屬柱被直接鍍覆到所述導電圖案上。
  9. 如請求項5所述的半導體裝置，其中所述囊封材料包括多個橫向側，所述多個橫向側中的每一個與所述橫向基板側中的相應一個以及所述橫向上部基板測中的相應一個共平面。
  10. 一種半導體裝置，其包括： 基板，其具有頂部基板側、底部基板側以及在所述頂部基板側與所述底部基板側之間延伸的橫向基板側； 半導體晶粒，其具有頂部晶粒側、底部晶粒側以及在所述頂部晶粒側與所述底部晶粒側之間延伸的橫向晶粒側，其中所述底部晶粒側耦合到所述頂部基板側； 金屬柱，其具有頂部柱末端、底部柱末端，及在所述頂部柱側與所述底部柱末端之間延伸的橫向柱側，其中： 所述金屬柱是橫向定位在由所述半導體晶粒覆蓋的所述頂部基板側的區域外部； 所述金屬柱的至少一部份是被直接定位橫向於所述半導體晶粒； 所述底部柱末端是至少與所述底部晶粒側的一部分一樣低； 所述底部柱末端是用黏著構件耦合到所述頂部基板側；並且 所述頂部柱末端是至少與所述頂部晶粒側的垂直高度一樣； 導電圖案，其連接到所述頂部柱末端；以及 絕緣材料，其橫向圍繞所述導電圖案， 其中，所述導電圖案包括下表面，所述下表面從所述絕緣材料曝露並且從所述金屬柱曝露。
  11. 如請求項10所述的半導體裝置，其中所述金屬柱包括鍍覆銅柱。
  12. 如請求項10所述的半導體裝置，包括囊封材料，所述囊封材料囊封所述橫向晶粒側的至少一部分及所述橫向柱側的至少一部分，並且所述囊封材料接觸及覆蓋所述導電圖案的所述下表面的至少一部分。
  13. 如請求項12所述的半導體裝置，其中所述金屬柱的一部分從所述囊封材料的頂部側突出。
  14. 如請求項10所述的半導體裝置，其中至少所述金屬柱的大部分是低於所述頂部晶粒側。
  15. 如請求項10所述的半導體裝置，其中所述絕緣材料包括模具材料，所述模具材料橫向圍繞所述導電圖案。
  16. 一種半導體裝置，其包括： 基板，其具有頂部基板側、底部基板側，及在所述頂部基板側與所述底部基板側之間延伸的橫向基板側，所述基板包括頂側襯墊、底側襯墊以及一個或多個導電路徑，所述導電路徑電性耦合所述頂側襯墊到所述底側襯墊； 半導體晶粒，其具有頂部晶粒側、底部晶粒側，及在所述頂部晶粒側與所述底部晶粒側之間延伸的橫向晶粒側，其中所述底部晶粒側耦合到所述頂部基板側； 金屬柱，其具有頂部柱末端、底部柱末端，及在所述頂部柱側與所述底部柱末端之間延伸的橫向柱側，其中： 所述金屬柱是橫向定位在由所述半導體晶粒覆蓋的所述頂部基板側的區域外部； 所述底部柱末端是用黏著構件耦合到所述基板的所述頂側襯墊；並且 所述頂部柱末端是與所述頂部晶粒側共平面。
  17. 如請求項16所述的半導體裝置，其包括囊封材料，所述囊封材料囊封所述橫向晶粒側的至少一部分及所述橫向柱側的至少一部分。
  18. 如請求項17所述的半導體裝置，其中所述囊封材料包含頂部表面，所述頂部表面與所述頂部柱末端共平面。
  19. 如請求項17所述的半導體裝置，其中： 所述黏著構件包括焊料或環氧樹脂；並且 所述囊封材料直接接觸並且橫向圍繞所述所述黏著構件。
  20. 如請求項17所述的半導體裝置，其中所述囊封材料的一部分是直接垂直地在所述頂部基板側和所述底部晶粒側之間。
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Publication number Priority date Publication date Assignee Title
US11569176B2 (en) * 2017-03-21 2023-01-31 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing thereof
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Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7759212B2 (en) 2007-12-26 2010-07-20 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
TWI529949B (zh) * 2008-11-28 2016-04-11 半導體能源研究所股份有限公司 半導體裝置和其製造方法
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
CN103456794B (zh) * 2008-12-19 2016-08-10 株式会社半导体能源研究所 晶体管的制造方法
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
WO2011070892A1 (en) * 2009-12-08 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8288844B2 (en) * 2009-12-17 2012-10-16 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
KR101324760B1 (ko) * 2010-04-23 2013-11-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
KR101332374B1 (ko) * 2010-04-23 2013-11-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
CN105957802A (zh) * 2010-05-21 2016-09-21 株式会社半导体能源研究所 半导体装置及其制造方法
KR20130043063A (ko) * 2011-10-19 2013-04-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
JP2013110151A (ja) * 2011-11-17 2013-06-06 Elpida Memory Inc 半導体チップ及び半導体装置
US8981559B2 (en) * 2012-06-25 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8803306B1 (en) * 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
US9153560B2 (en) * 2014-01-22 2015-10-06 Qualcomm Incorporated Package on package (PoP) integrated device comprising a redistribution layer
JP6358431B2 (ja) * 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
US9761534B2 (en) 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US9875979B2 (en) * 2015-11-16 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive external connector structure and method of forming

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TWI712134B (zh) 2020-12-01
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US11205602B2 (en) 2021-12-21
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US20180033708A1 (en) 2018-02-01
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US10062626B2 (en) 2018-08-28
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CN206259336U (zh) 2017-06-16

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