CN206259336U - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN206259336U
CN206259336U CN201621048868.XU CN201621048868U CN206259336U CN 206259336 U CN206259336 U CN 206259336U CN 201621048868 U CN201621048868 U CN 201621048868U CN 206259336 U CN206259336 U CN 206259336U
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Prior art keywords
semiconductor device
substrate
metal column
substrate surface
post
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English (en)
Inventor
金进勇
郑季洋
元秋亨
安旷黄
林河贞
李泰勇
贝俊明
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Anrely Technology Singapore Holdings Pte Ltd
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Imark Technology Co
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Abstract

本实用新型提供一种半导体装置，其包括：衬底，其具有顶部衬底表面、底部衬底表面，及在顶部衬底表面与底部衬底表面之间延伸的横向衬底表面；半导体裸片，其具有顶部裸片表面、底部裸片表面，及在顶部裸片表面与底部裸片表面之间延伸的横向裸片侧表面，其中底部裸片表面耦合到顶部衬底表面；金属柱，其具有顶部柱表面、底部柱表面，及在顶部柱表面与底部柱表面之间延伸的横向柱表面，其中底部柱表面是用粘着构件耦合到顶部衬底表面，且定位在由半导体裸片覆盖的顶部衬底表面的区域外部；及封装材料，其封装横向裸片侧表面的至少一部分及横向柱表面的至少一部分。本实用新型的各种态样提供一种具有小尺寸及细节距的可堆叠半导体装置。

Description

半导体装置
技术领域
本实用新型是关于一种半导体装置。
背景技术
目前的半导体装置及用于制造半导体装置的方法是不适当的，举例来说，引起过低的灵敏度、过多的成本、减低的可靠性，或过大的包装尺寸。通过比较常规及传统途径与如在本申请案的剩余部分中参考附图所阐述的本实用新型，此类途径的另外限制及缺点对于所属领域的技术人员来说将变得显而易见。
实用新型内容
本实用新型提供一种半导体装置。作为非限制性实例，本实用新型的各种态样提供一种具有小尺寸及细节距的可堆叠半导体装置。
本实用新型的一实施例提供一种半导体装置，其包括：衬底，其具有顶部衬底表面、底部衬底表面，及在所述顶部衬底表面与所述底部衬底表面之间延伸的横向衬底表面；半导体裸片，其具有顶部裸片表面、底部裸片表面，及在所述顶部裸片表面与所述底部裸片表面之间延伸的横向裸片侧表面，其中所述底部裸片表面耦合到所述顶部衬底表面；金属柱，其具有顶部柱表面、底部柱表面，及在所述顶部柱表面与所述底部柱表面之间延伸的横向柱表面，其中所述底部柱表面是用粘着构件耦合到所述顶部衬底表面，且定位在由所述半导体裸片覆盖的所述顶部衬底表面的区域外部；及封装材料，其封装所述横向裸片侧表面的至少一部分及所述横向柱表面的至少一部分。
在所述半导体装置中，所述粘着构件包括焊料。
在所述半导体装置中，所述顶部柱表面与所述顶部裸片表面共面。
在所述半导体装置中，所述顶部柱表面与所述封装材料的顶部表面共面。
在所述半导体装置中，所述顶部柱表面与所述封装材料的顶部表面共面。
所述半导体装置包括上部衬底，所述上部衬底具有顶部上部衬底表面、底部上部衬底表面，及在所述顶部上部衬底表面与所述底部上部衬底表面之间延伸的横向上部衬底表面。
在所述半导体装置中，所述上部衬底包括与所述金属柱一体地形成的底部导电图案。
在所述半导体装置中，所述金属柱镀覆在所述导电图案上。
在所述半导体装置中，所述上部衬底包括顶部导电图案，所述顶部导电图案直接地定位在所述金属柱上方且与所述底部导电图案及所述金属柱一体地形成。
在所述半导体装置中，所述横向裸片表面中的每一者与所述横向衬底表面中的相应横向衬底表面及所述横向上部衬底表面中的相应横向上部衬底表面共面。
附图说明
图1展示根据本实用新型的各种态样的半导体装置的横截面图；
图2展示根据本实用新型的各种态样的半导体装置的横截面图；
图3A到图3F展示说明根据本实用新型的各种态样的制造半导体装置的方法的视图；
图4A到图4I展示说明根据本实用新型的各种态样的制造半导体装置的方法的视图；且
图5A到图5F展示说明根据本实用新型的各种态样的制造半导体装置的方法的视图。
具体实施方式
以下论述通过提供本实用新型的实例来呈现本实用新型的各种态样。此类实例是非限制性的，且因此，本实用新型的各种态样的范围应未必受到所提供实例的任何特定特性限制。在以下论述中，短语“举例来说”、“例如”及“示范性”是非限制性的，且与“作为实例而非限制”、“举例来说而非限制”及其类似者大体上同义。
如本文中所利用，“及/或”意指由“及/或”接合的列表中的项目中的任何一或多者。作为一实例，“x及/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。换句话说，“x及/或y”意指“x及y中的一或两者”。作为另一实例，“x、y及/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。换句话说，“x、y及/或z”意指“x、y及z中的一或多者”。
本文中所使用的术语是仅出于描述特定实例的目的，且并不意欲限制本实用新型。如本文中所使用，单数形式也意欲包含复数形式，除非上下文另有清晰指示。将进一步理解，术语“包括”、“包含”、“具有”及其类似者在用于本说明书中时表示所陈述特征、整数、步骤、操作、元件及/或组件的存在，但并不排除一或多个其它特征、整数、步骤、操作、元件、组件及/或其群组的存在或添加。
将理解，尽管术语第一、第二等等可在本文中用以描述各种元件，但这些元件不应受到这些术语限制。这些术语仅用以区分一个元件与另一元件。因此，举例来说，在不脱离本实用新型的教示的情况下，下文所论述的第一元件、第一组件或第一区段可被称为第二元件、第二组件或第二区段。相似地，诸如“上部”、“上方”、“下部”、“下方”、“侧”、“横向”、“水平”、“垂直”及其类似者的各种空间术语可用来以相对方式区分一个元件与另一元件。然而，应理解，在不脱离本实用新型的教示的情况下，组件可以不同方式而定向，举例来说，半导体装置可侧向地转动使得其“顶部”表面水平地面向且其“侧”表面垂直地面向。
还将理解，术语耦合、连接、附接及其类似者包含直接及间接(例如，用介入元件)耦合、连接、附接等等，除非另有明确指示。举例来说，如果元件A耦合到元件B，那么元件A可通过中间信号分配结构而间接地耦合到元件B，元件A可直接地耦合到元件B(例如，直接地粘附到、直接地焊接到、通过直接金属到金属结合而附接)，等等。
在附图中，可出于清晰起见而夸示结构、层、区域等等的尺寸(例如，绝对及/或相对尺寸)。虽然此类尺寸通常指示实例实施方案，但其并非限制性的。举例来说，如果将结构A说明为大于区域B，那么此通常指示实例实施方案，但通常并不要求结构A大于结构B，除非另有指示。另外，在附图中，类似参考数字可在整个论述中指代类似元件。
本实用新型的各种态样提供一种半导体装置，其特征可为小占据面积、小厚度及细节距图案间距。举例来说，半导体装置可为可堆叠的。
本实用新型的各种态样提供一种半导体装置，其包括衬底、耦合到衬底的一个表面的半导体裸片、耦合到衬底的表面的金属柱，及封装半导体裸片及金属柱且暴露金属柱的封装物。举例来说，金属柱可沿着封装物的孔垂直地形成。
本实用新型的各种态样提供一种制造半导体装置的方法，所述方法包括：提供包含金属柱的载体衬底及环绕金属柱的绝缘构件；在绝缘构件表面上涂布及图案化光刻胶；对金属柱执行镀覆；将金属柱耦合到衬底；去除光刻胶及载体衬底；及形成封装金属柱的封装物。
本实用新型的各种态样提供一种制造半导体装置的方法，所述方法包括：在载体衬底的表面上提供种子层及光刻胶；通过在光刻胶的图案中执行镀覆而形成金属柱；去除光刻胶；将金属柱耦合到衬底；形成封装金属柱的封装物；及去除载体衬底。
举例来说，本实用新型的各种态样可提供一种半导体装置，其包括在衬底的顶部表面上具有细节距的金属柱，其中金属柱暴露到封装物外部，由此提供具有小尺寸及细节距图案间距的可堆叠半导体装置。举例来说，半导体装置还可包括耦合到金属柱的上部衬底。
现在将参考附图来详细地描述本实用新型的各种态样，使得其可容易由所属领域的技术人员实践。
图1展示根据本实用新型的各种态样的半导体装置的横截面图。举例来说，实例半导体装置100可包括衬底110、半导体裸片120、金属柱130、封装物140及导电球150。
举例来说，衬底110可由一般印刷电路板(PCB)或引线框架形成。而且，衬底110可以半导体工艺而由基于硅的内建衬底形成。尽管未单独地展示，但举例来说，衬底110可包含一或多个导电层(例如，金属等等)，其电耦合形成在衬底的顶部及底部表面上的衬垫，从而提供上覆半导体裸片120或金属柱130以电连接到下伏导电球150。举例来说，衬底110的此类导电层可包括铜(Cu)、铝(Al)、其合金等等，但本实用新型的范围并不限于此情形。另外，为了增强连接性，可另外将诸如金(Au)的金属施加到衬垫。
举例来说，半导体裸片120可包括与半导体晶片分离(或单切或分割)的集成电路芯片。半导体裸片120可包括多种不同类型的电路中的任一者，举例来说，中央处理单元(CPU)、数字信号处理器(DSP)、网络处理器、功率管理单元、音频处理器、RF电路、无线基带芯片上系统(SoC)处理器、传感器、专用集成电路等等。
举例来说，半导体裸片120可通过导电衬垫121将电信号输入到第一表面(例如，底部表面等等)及/或从第一表面(例如，底部表面等等)输出电信号。举例来说，导电衬垫121可连接到半导体裸片120的内部图案(或导电层)，且可通常包含铝(Al)及/或其它导电材料。另外，半导体裸片120的导电衬垫121可通过导电粘着构件120a(例如，包括焊料、导电环氧树脂等等)而电连接到形成在衬底110的顶部表面上的球(或衬垫或其它互连结构)。应注意，还可利用直接金属到金属(例如，无焊)金属间结合。举例来说，半导体裸片120可包括使除了导电衬垫121被暴露的区域以外的区域绝缘的钝化层。尽管论述仅一个导电衬垫121，但可存在任何数目个此类导电衬垫。
举例来说，半导体裸片120可包括与第一表面(例如，底部表面)相对的第二表面122(例如，顶部表面)。举例来说，第二表面122可暴露到外部(例如，从封装材料暴露)。举例来说，第二表面122可与封装物140的顶部表面具有相同高度，封装物140的顶部表面将被暴露到封装物140外部。在这个实例配置中，半导体裸片120可经配置以促进热从半导体裸片120散发到外部。
金属柱130从衬底110的顶部表面突出。举例来说，金属柱130可由金属(例如，铜等等)制成，且可定位在除了半导体裸片120被定位的区域以外的区域上。举例来说，金属柱130可通过导电粘着构件130a(例如，包括焊料等等)而电连接到衬底110。另外，金属柱130可从封装物140的上部部分(例如，从上部表面)暴露。在一些状况下，金属柱130的末端131可从衬底110延伸得比从封装物140延伸得更远，举例来说，从封装物140的顶部表面突出。当将另一半导体装置堆叠在半导体装置100上时，所述半导体装置可通过金属柱130而彼此电连接。
在实例实施方案中，举例来说，金属柱130的宽度可在约10μm到约15μm的范围内。因此，与利用直径为约350μm的焊料凸块的状况相比较，金属柱130可以细节距而实施在衬底110上，由此缩减包含衬底110的半导体装置100的总尺寸。另外，许多金属柱130可定位在具有相同小尺寸(及/或多种尺寸)的衬底110上，在设计半导体装置100态样可得到较高自由度。
举例来说，封装物140可形成在衬底110的第一表面(例如，顶部表面)上以环绕半导体裸片120及金属柱130(例如，以环绕及/或接触其横向表面等等)。举例来说，封装物140可由多种材料中的任一者(例如，一般树脂等等)制成，且可在固定半导体裸片120及金属柱130的位置的同时保护半导体裸片120及金属柱130免受外部冲击。
导电球150(或多种互连结构中的任一者，举例来说，导电凸块、导电支柱或柱等等)可形成在衬底110之下(例如，形成在图1中的衬底110的底部表面上)。举例来说，导电球150可由焊料制成，且可耦合到衬底110的底部表面上的互连结构(例如，衬垫、迹线、球、凸块等等)。导电球150可稍后连接到外部电路以提供用于将电信号输入到衬底110及/或从衬底110输出电信号的路径。
如上文所描述，在实例半导体装置100中，具有细节距的金属柱130定位(或形成)在衬底110的顶部表面上且暴露到封装物140外部，由此实施细节距且提供另一半导体装置在半导体装置100上的堆叠(或反之亦然)，同时缩减总尺寸。
在实例实施方案中，另一衬底或插入件可堆叠(或形成)在半导体裸片120及/或封装物140的顶部侧上。在图2处提供此类实施方案的实例，如现在将描述。
图2展示根据本实用新型的各种态样的半导体装置的横截面图。举例来说，实例半导体装置200可包括衬底110、半导体裸片120、金属柱130、上部衬底230、封装物140，及导电球150。与图1的实例半导体装置100的功能组件相同的功能组件是由相同参考数字表示，且以下描述将大体上集中于图2的实例半导体装置200与图1的实例半导体装置100之间的差异。
上部衬底230是沿着封装物140的顶部表面而定位。另外，上部衬底230包括多个导电图案231(或其部分)，其从上部衬底230的底部表面(或在上部衬底230的底部表面处)暴露到封装物140的顶部表面。上部衬底230可通过从上部衬底230的顶部表面(或在上部衬底230的顶部表面处)暴露的导电图案231(或其部分)而电连接到堆叠在上部衬底230上的半导体装置。另外，导电图案231可在实例装置200的各种区域(举例来说，除了半导体裸片120被定位的区域以外的区域)中电连接到金属柱130。举例来说，上部衬底230可通过金属柱130而电连接到衬底110。
如上文所描述，实例半导体装置200可经形成以通过提供金属柱130而不对封装物140执行激光钻孔(或烧蚀)而具有细节距图案(例如，导体、焊盘、迹线、衬垫等等)。另外，实例半导体装置200可经配置以提供另一半导体装置在半导体装置200上的堆叠(或反之亦然)，举例来说，通过使上部衬底230连接到金属柱130。
在下文中，将描述根据本实用新型的一实施例的制造半导体装置的实例方法。举例来说，实例方法可用以制造本文中所论述的实例半导体装置中的任一者或全部，或其任何部分。
图3A到图3F展示说明根据本实用新型的各种态样的制造半导体装置的实例方法的视图。
参看图3A，根据本实用新型的各种态样的制造半导体装置的实例方法可包括在载体衬底10上提供(或形成)金属柱130，及提供(或形成)覆盖金属柱130的绝缘构件20。举例来说，载体衬底10可包括金属、介电材料、半导体材料等等。举例来说，绝缘构件20可通过模制而形成，但本实用新型的态样并不限于此情形。举例来说，绝缘构件20可通过旋涂、气相沉积、印刷等等而形成。另外，可在载体衬底10上图案化绝缘构件20，且可(举例来说)使用载体衬底10作为种子层来执行电镀或无电式镀覆，由此形成金属柱130。举例来说，金属柱130可由铜(Cu)、铝(Al)等等制成。举例来说，金属柱130可通过(举例来说)在种子层上、在载体衬底10的导电图案(例如，衬垫、焊盘、迹线等等)上、在种子层上等等镀覆金属柱130而形成。
参看图3B，在绝缘构件20上形成(例如，涂布等等)且图案化光刻胶30(或光刻胶层)，且对由光刻胶30的图案暴露的区域执行电镀或无电式镀覆，由此增加金属柱130的高度。举例来说，此类镀覆物可为与金属柱130相同的材料及/或不同的材料。而且，导电粘着构件130a可进一步形成在金属柱130上(例如，除了将金属添加到金属柱130以外及/或代替将金属添加到金属柱130)。举例来说，导电粘着构件130a可由一般焊接材料制成，但本实用新型的态样并不限于此情形。
参看图3C，去除光刻胶30(或光刻胶层)及载体衬底10。举例来说，可通过一般灰化工艺来去除光刻胶30，且可通过研磨(例如，带材研磨等等)、通过剥离胶带(如果胶带形成在光刻胶30与载体衬底10之间的界面处)、通过化学/机械平坦化等等来去除载体衬底10。因此，可暴露形成在金属柱130上的导电粘着构件130a及金属柱130(或其部分)。
参看图3D，在导电粘着构件130a被翻转以面向下的状态中，金属柱130耦合到衬底110。在实例实施方案中，衬底110可处于半导体裸片120在金属柱130之前耦合到衬底110的状态，且导电粘着构件130a可相对于形成在衬底110上的图案(例如，迹线、衬垫、焊盘等等)而对准，由此使金属柱130及衬底110彼此耦合。举例来说，此类耦合可通过热压结合、质量回流、直接金属到金属(例如，无焊)结合、导电粘着剂等等而执行。
参看图3E，封装物140(或封装材料)可填充绝缘构件20与衬底110之间的区域以封装半导体裸片120及金属柱130。封装物140可经形成以从至少一个侧(例如，从横向侧等等)封装内部组件。另外，尽管未单独地展示，但单独底胶还可任选地在封装物140之前形成在半导体裸片120的导电衬垫121周围。
另外，参看图3E，在形成封装物140之后可去除绝缘构件20。举例来说，可通过研磨(例如，带材研磨等等)、蚀刻、化学/机械平坦化等等来去除绝缘构件20。因此，半导体裸片120的顶部表面122可从封装物140的上部部分(例如，从上部表面)暴露。在这种状况下，举例来说，归因于去除绝缘构件20时的物理性质差异，金属柱130(例如，其末端表面)还可从封装物140的上部部分暴露及/或还可从封装物140的顶部表面向上突出。
参看图3F，导电球150(或其它互连结构，举例来说，柱、支柱、凸块等等)形成在衬底110的底部表面上。导电球150可经形成以对应于衬底110的底部表面上的图案(例如，迹线、焊盘、衬垫、凸块下金属化层等等)，由此提供用于连接到外部电路的路径。
在下文中，将描述根据本实用新型的一实施例的半导体装置的另一制造方法。举例来说，实例方法可用以制造本文中所论述的实例半导体装置中的任一者或全部，或其任何部分。
图4A到图4I展示说明根据本实用新型的各种态样的制造半导体装置的方法的视图。举例来说，所述实例方法可与图3A到图3F所说明的实例方法共享任何或所有特性。
参看图4A及图4B，根据本实用新型的各种态样的制造半导体装置的实例方法可包括在载体衬底10的表面上形成种子层11及光刻胶12(或光刻胶层)。举例来说，种子层11可由诸如铜(Cu)的金属或金属薄板形成，但本实用新型的态样并不限于此情形。
参看图4C，举例来说，通过掩蔽而在光刻胶12中形成图案。举例来说，图案可经配置以暴露对应于稍后待形成的金属柱130的区域。
参看图4D，使用种子层11作为种子而执行电镀，由此形成镀覆层13。镀覆层13可形成在光刻胶12的图案12a中及/或之外，举例来说，形成在由光刻胶12的图案12a暴露的种子层11的部分上。应注意，镀覆层13可形成在多种导电图案(例如，衬垫、焊盘、迹线等等)中的任一者上。举例来说，镀覆层13可与被镀覆有镀覆层13的导体一体地形成。
参看图4E，可对光刻胶12及镀覆层13执行研磨(例如，带材研磨等等)或一般薄化。另外，由研磨引起的镀覆层13可构成金属柱130。然而，任选地执行这个步骤。如果不执行这个步骤，那么镀覆层13可与金属柱130相同。
参看图4F，可去除光刻胶12。如上文所描述，举例来说，可通过灰化来去除光刻胶12，由此暴露种子层11及金属柱130。
参看图4G，导电粘着构件130a形成在金属柱130之下，且金属柱130及衬底110可通过导电粘着构件130a而彼此耦合。应注意，举例来说，导电粘着构件130可如本文中关于图3所论述而形成在金属柱130上，可在附接金属柱130之前形成在衬底110上，等等。此处，半导体裸片120可在金属柱130之前耦合到衬底110。举例来说，导电粘着构件130a可相对于形成在衬底110上的图案(例如，迹线、衬垫、焊盘等等)而对准，由此使金属柱130及衬底110彼此耦合。
参看图4H，封装物140(例如，模具材料、一般介电材料等等)可经形成(例如，模制、旋涂、气相沉积等等)以填充种子层11与衬底110之间的区域，举例来说，以封装半导体裸片120及金属柱130(例如，其横向表面等等)。举例来说，封装物140可经形成以从至少一个侧封装内部组件。另外，尽管未单独地展示，但单独底胶还可任选地在封装物140之前形成在半导体裸片120的导电衬垫121周围。
另外，参看图4H，在形成封装物140之后可去除载体衬底10及种子层11。举例来说，可通过研磨(例如，带材研磨等等)、蚀刻、化学/机械平坦化、一般平坦化等等来去除绝缘构件20。因此，半导体裸片120的顶部表面122可从封装物140的上部部分(例如，从上部表面)暴露。在这种状况下，举例来说，归因于去除绝缘构件20时的物理性质差异，金属柱130(例如，其顶部表面)还可从封装物140的上部部分暴露及/或还可经形成以从封装物的顶部表面向上突出。
参看图4I，导电球150(或其它互连结构，举例来说，柱、支柱、凸块等等)形成在衬底110的底部表面上。导电球150可经形成以对应于形成在衬底110的底部表面上的图案(例如，迹线、焊盘、衬垫、凸块下金属化层等等)，由此提供用于连接到外部电路的路径。
在下文中，将描述根据本实用新型的另一实施例的半导体装置的制造方法。举例来说，实例方法可用以制造本文中所论述的实例半导体装置中的任一者或全部，或其任何部分。
图5A到图5F展示说明根据本实用新型的各种态样的制造半导体装置的方法的视图。举例来说，所述实例方法可与图3A到图3F所说明的实例方法及/或与图4A到图4I所说明的实例方法共享任何或所有特性。
参看图5A，根据本实用新型的各种态样的制造半导体装置的实例方法可包括在载体衬底10上提供(或形成)导电图案231(例如，迹线、焊盘、衬垫等等)及金属柱130，及提供(或形成)覆盖导电图案231及金属柱130之绝缘构件20。举例来说，绝缘构件20可通过模制而形成，但本实用新型的态样并不限于此情形。举例来说，绝缘构件20可通过旋涂、气相沉积、印刷等等而形成。
另外，在实例实施方案中，可首先在载体衬底10上图案化绝缘构件20，且可(举例来说)使用载体衬底10作为种子层来执行电镀或无电式镀覆，由此形成导电图案231。接下来，在图案化绝缘构件20之后，可(举例来说)使用导电图案231(例如，衬垫、焊盘、迹线等等)及/或载体衬底10作为种子层来形成镀覆式金属柱130。举例来说，镀覆层13可与被镀覆有镀覆层13的导体(例如，种子层、衬垫、焊盘、迹线等等)一体地形成。
参看图5B，在绝缘构件20上形成(例如，涂布等等)且图案化光刻胶30(或光刻胶层)，且对由光刻胶30的图案暴露的区域执行电镀或无电式镀覆，由此增加金属柱130的高度。举例来说，此类镀覆物可为与金属柱130相同的材料及/或不同的材料。而且，导电粘着构件130a可进一步形成在金属柱130上(例如，除了将金属添加到金属柱130以外及/或代替将金属添加到金属柱130)。举例来说，导电粘着构件130a可由一般焊接材料制成，但本实用新型的态样并不限于此情形。
参看图5C，去除光刻胶30(或光刻胶层)及载体衬底10。举例来说，可通过一般灰化工艺来去除光刻胶30，且可通过研磨(例如，带材研磨等等)或通过剥离胶带(如果胶带形成在光刻胶30与载体衬底10之间的界面处)、通过化学/机械偏振等等来去除载体衬底10。因此，可暴露形成在金属柱130上的导电粘着构件130a及金属柱130(或其部分)。以此类方式，可形成具有导电图案231的实例上部衬底230及金属柱130。在这个步骤中，还可去除绝缘构件20的部分，由此进一步暴露金属柱130。在实例实施方案中，如果缩减绝缘构件20的厚度且增加光刻胶30的厚度，那么可通过去除光刻胶30而暴露金属柱130的相当大的部分。
参看图5D，在导电粘着构件130a被翻转以面向下的状态中，金属柱130耦合到衬底110。在实例实施方案中，衬底110可处于半导体裸片120在金属柱130之前耦合到衬底110的状态，且导电粘着构件130a可相对于形成在衬底110上的图案(例如，迹线、衬垫、焊盘等等)而对准，由此使金属柱130及衬底110彼此耦合。举例来说，此类耦合可通过热压结合、质量回流、直接金属到金属(例如，无焊)结合、导电粘着剂等等而执行。
另外，参看图5D，上部衬底230的导电图案231可向上暴露。因此，待在后续步骤中堆叠的半导体装置可容易电连接到导电图案231。
参看图5E，封装物140(或封装材料)可填充上部衬底230与衬底110之间的区域以封装半导体裸片120及金属柱130。封装物140可经形成以从一个侧(例如，从横向侧等等)封装内部组件。另外，尽管未单独地展示，但单独底胶还可任选地在封装物140之前形成在半导体裸片120的导电衬垫121周围。
参看图5F，导电球150(或其它互连结构，举例来说，柱、支柱、凸块等等)形成在衬底110的底部表面上。导电球150可经形成以对应于衬底110的底部表面上的图案(例如，迹线、焊盘、衬垫、凸块下金属化层等等)，由此提供用于连接到外部电路的路径。
虽然已参考某些支持实例及/或实施方案而描述根据本实用新型的各种态样的半导体装置及其制造方法，但所属领域的技术人员将理解，本实用新型的范围并不限于所揭示的特定实例，而是本实用新型将包含属于所附权利要求书的范围内的所有实施例、实例及实施方案。
本文中的论述包含展示电子装置组合件及其制造方法的各种部分的众多说明性附图。出于说明清晰起见，此类附图并未展示每一实例组合件的所有态样。本文中所提供的任何实例组合件及/或方法可与本文中所提供的任何或所有其它组合件及/或方法共享任何或所有特性。
总之，本实用新型的各种态样提供一种半导体装置及一种制造半导体装置的方法。作为非限制性实例，本实用新型的各种态样提供一种具有小尺寸及细节距的可堆叠半导体装置以及其制造方法。虽然已参考某些态样及实例而描述前述内容，但所属领域的技术人员将理解，在不脱离本实用新型的范围的情况下，可进行各种改变且可取代等效者。另外，在不脱离本实用新型的范围的情况下，可进行许多修改以使特定情形或材料适应于本实用新型的教示。因此，希望本实用新型不限于所揭示的特定实例，而是本实用新型将包含属于所附权利要求书的范围内的所有实例。

Claims (10)

1.一种半导体装置，其特征在于，其包括：
衬底，其具有顶部衬底表面、底部衬底表面，及在所述顶部衬底表面与所述底部衬底表面之间延伸的横向衬底表面；
半导体裸片，其具有顶部裸片表面、底部裸片表面，及在所述顶部裸片表面与所述底部裸片表面之间延伸的横向裸片侧表面，其中所述底部裸片表面耦合到所述顶部衬底表面；
金属柱，其具有顶部柱表面、底部柱表面，及在所述顶部柱表面与所述底部柱表面之间延伸的横向柱表面，其中所述底部柱表面是用粘着构件耦合到所述顶部衬底表面，且定位在由所述半导体裸片覆盖的所述顶部衬底表面的区域外部；及
封装材料，其封装所述横向裸片侧表面的至少一部分及所述横向柱表面的至少一部分。
2.如权利要求1所述的半导体装置，其特征在于，其中所述粘着构件包括焊料。
3.如权利要求1所述的半导体装置，其特征在于，其中所述顶部柱表面与所述顶部裸片表面共面。
4.如权利要求3所述的半导体装置，其特征在于，其中所述顶部柱表面与所述封装材料的顶部表面共面。
5.如权利要求1所述的半导体装置，其特征在于，其中所述顶部柱表面与所述封装材料的顶部表面共面。
6.如权利要求1所述的半导体装置，其特征在于，其包括上部衬底，所述上部衬底具有顶部上部衬底表面、底部上部衬底表面，及在所述顶部上部衬底表面与所述底部上部衬底表面之间延伸的横向上部衬底表面。
7.如权利要求6所述的半导体装置，其特征在于，其中所述上部衬底包括与所述金属柱一体地形成的底部导电图案。
8.如权利要求7所述的半导体装置，其特征在于，其中所述金属柱镀覆在所述导电图案上。
9.如权利要求7所述的半导体装置，其特征在于，其中所述上部衬底包括顶部导电图案，所述顶部导电图案直接地定位在所述金属柱上方且与所述底部导电图案及所述金属柱一体地形成。
10.如权利要求6所述的半导体装置，其特征在于，其中所述横向裸片表面中的每一者与所述横向衬底表面中的相应横向衬底表面及所述横向上部衬底表面中的相应横向上部衬底表面共面。
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