1353650 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝結構，且特別是有關於一 種内埋式晶片導接構裝結構。 【先前技術】 在新一代的電子產品中，不斷追求更輕薄短小，更要 求產品具有多功能與高性能，因此，積體電路(Integrated • circuit, 1C)必須在有限的空間中容納更多電子元件以達到 高密度與微型化之要求，為此電子產業開發新型構裝技 術，將半導體晶片埋入基板中，大幅縮小構裝體積’也縮 '短晶片與基板的連接路徑，另外還利用增層技術(build-up) 增加佈線面積，以符合輕薄短小及多功能的潮流趨勢。然 而，配合晶片内埋，其運作過程產生之熱量亦大幅增加， 若熱量無法及時排除，將嚴重影響半導體晶片之性能，此 外，製程中的熱處理（例如烘烤）會造成電路板彎翹的問題 產生，因此，業界提出各種封裝結構以改良上述問題。 * 台灣專利1251916提出一散熱件，在散熱件上形成一 凹槽，接著將晶片與被動元件置入凹槽中，另外將製作完 成之增層結構結合於散熱件上，藉由該散熱件耦合至半導 體晶片，可有效逸散半導體晶片運作產生之熱量。 台灣專利1237885提出由不同材質組成之雙承載件， 第二承載件形成於第一承載件上，並於第二承載件上形成 一凹槽，將半導體晶片置入後，於其上形成介電層，後續 進行增層結構。主要藉由兩種不同材質組成之承載件，使 蝕刻過程中承載結構與晶片的接置面具平整性，以提升後 5 1353650 續製程品質與可靠度。 美國專利US 6709898提出於一散熱件上形成複數個 開孔，接著將晶片置入開孔中，於晶片與散熱板外形成一 介電層，之後於介電層表面進行增層結構，同樣藉由該散 熱件耦合至半導體晶片，可有效逸散熱量。 因此，業界亟需提出一種内埋式晶片導接結構，製程 較為簡易，且同時能提升晶片散熱效果以及改良板彎翹的 問題。 *【發明内容】 • 本發明的目的之一就是提供一種半導體内埋式晶片 - 導接構裝結構及其製法，同時能提升晶片散熱效果以及改 良板彎翹的問題。 為達上述與其他目的，本發明提供一種半導體内埋式 晶片導接構裝結構之製法，係包括以下步驟：提供一金屬 承載件；於該金屬承載件中形成一凹槽與複數個導通孔； 於該金屬承載件上形成一絕緣層，該絕緣層順應地覆蓋該 φ 凹槽及該些導通孔表面；於該絕緣層上順應地形成一金屬 層；以油墨填入該些導通孔中；將該金屬層圖案化以形成 一内層線路；將一半導體晶片置入並固定於該凹槽中；覆 蓋一介電層於該晶片與該内層線路之上；於該介電層中形 成複數個開孔以露出該内層線路；於該金屬承載件之相反 兩側形成一增層線路，該增層線路經由該些開孔電性連接 該内層線路。 本發明亦提供一種半導體内埋式晶片導接構裝結 構，係包括：一金屬承載件，該金屬承載件具有一凹槽與 6 1353650 複數個導通孔；一絕緣層，順應地覆蓋該凹槽及該些導通 孔表面；一内層線路，形成於該絕緣層之上；一油墨，填 入該些導通孔中；一半導體晶片，固定於該凹槽中；一介 電層，形成於該半導體晶片與該内層線路之上；複數個開 孔，露出該内層線路；以及一增層線路，形成於該金屬承 載件之相反兩側，該增層線路經由該些開孔電性連接該内 層線路。 為讓本發明之上述和其他目的、特徵、和優點能更明 _ 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 以下將配合第1圖到第12圖詳細說明本發明實施例 之半導體内埋式晶片導接構裝結構之製法。須注意的是， 該些圖式均為簡化之示意圖，以強調本發明之特徵，因此 圖中之元件尺寸並非完全依實際比例繪製。且本發明之實 施例也可能包含圖中未顯示之元件。 | 請參見第1圖，首先提供一金屬承载件（metal core)l，金屬承載件1之材質可為Cu、Al、Ni等金屬， 但不限於單一金屬，也可以為上述金屬之組合或其合金， 其中較佳為Cu。使用金屬作為承載件之好處在於能提升 晶片散熱效果以及改良板彎翹之問題。 接著請參見第2圖，於該金屬承載件1上形成一凹槽 2(recess)與複數過導通孔（through hole)3，形成凹槽2之方 法可利用物理性的金屬機械加工技術或利用化學性的蝕 刻技術。此凹槽2是為了將晶片内埋於其中，使得整體構 7 1353650 裝體積大幅縮小，而凹槽2尺寸視實際應用時晶片尺寸大 小而定，一般而言，凹槽2之尺寸通常會略大於晶片，使 晶片得以順利地固定與對準。形成導通孔3之目的在於建 立金屬承載件1正反兩面之導電通路，以利後續之雙面增 層線路11 ’方法可利用數値控制工具機（numerical c^ntr〇l， NC)鑽孔或其他鑽孔之技術。 請參見第3圖，於金屬承載件丨上形成絕緣層4。該 絕緣層4可利用塗佈或者是電沉積法順應地覆蓋該凹槽2 籲與導通孔3表面，使金屬承載件】與後續線路電性絕緣。 一般而言’絕緣層4之厚度約5 μιη〜65 μιη。 絕緣層4可為各種高分子材料，例如：環氧樹脂 (expoxy resm)、聚亞醯胺（p〇lyimide)、氰脂㈣⑽批 ester)、雙順丁 細二酸醢亞胺（bismaieimide triazine)、或上 述之組合，也可為高分子複合材料，例如高分子材料混合 玻璃纖維、黏土或陶曼等。 請參見第4圖，於絕緣層4上順應地形成金屬層5。 形成金屬層5之方法，包括但不限於電鍍導通孔(plating • through hole，PTH)技術，也可利用濺鍍（sputter)或者是無 電極電鍍（electroless plating)法，其中金屬層5之材質一 般選擇導電性較高的Cu為主。之後參見第5圖，進行灌 孔製程，將油墨6填入該些導通孔3中，所使用之油墨6 例如是樹脂油墨。 請參見第6圖，將該金屬層5圖案化以形成一内層線 路5a。圖案化製程包括以下步驟：對該些金屬層5進行 内部曝光，以及進行顯影（development)、钱刻（etching)和 去膜（stripping)之步驟，即所謂的DES法。經圖案化後， 8 1353650 在金屬承載件1上下兩側的絕緣層4上形成一圖案化之内 層線路5a。 請參見第7圖，利用一導熱性黏著劑^(thermally conductive adhesive material)將一半導體晶片7置入並固 定於凹槽2中，其中導熱性黏著劑8可為底部填充膠 (underfill)、環氧樹脂（epoxy)、或附模組膠膜（die attach film，DAF)。該導熱性黏著劑8可減少半導體晶片7與金 屬承載件1間因熱膨脹差異所產生之熱應力，並可增加半 鲁導體晶片7之散熱效率。於該半導體晶片7之上經由無電 極電鍍製程形成複數個焊點底墊金屬（under bump metallurgy, UBM)7a’其中該些銲點底層金屬之位置對應 •到晶片上開孔之預定位置，用以防止後續製程中銲料與導 電基材發生反應，UBM之材質較佳為鎳/金。 接著參見第8圖’覆蓋一介電層9於該半導體晶片7 與該内層線5a之上，以利後續增層線路之進行。其中介 電層9可為感光樹脂或非感光性樹脂，例如：環氧樹脂、 雙馬來亞醢胺-三氮雜苯樹脂（bismaleimide triaeine， • BT)、ABF 膜（ajinomoto build-up film)、聚苯鱗（p〇ly phenylene oxide，PPE)、或聚四氟乙烯樹脂 (polytetrafluorcethylene, PTFE)等。 請參見第9圖，利用雷射鑽孔法於該介電層 一開孔10，目的在於露出該内層線路5 藉由此開孔10與後續製程之線路連接。a使内層線路5a 請參見第10圖’於金屬承載件丨 增層線路11 ’使增層線路11經由開子丨，目反兩側形成一 層線路5a。由於第2圖時，於金屬承二電性連接該内 泉戟件1中形成導通 9 側，而形成二:形成於金屬承載件1之相反兩 佈線面積，也因：電；3較:=層結構不但能增加 問題:及提升製程品質與可2均勻’而減少板彎魅之 先形iU::,增層線路之製程需要在承載件與晶片外 片前可直接於已絕绘'線路，而本發明於置入晶 以連接後續之雔面掸展社 载件上形成一内層線路，用 請參見第^阁曰Θ'、Ή構，以降低整體封裝高度。 12，用以保護内埋之2面：層線路11上塗佈上-綠漆 焊接短路。接著二=避免雙面增層線路11氧化和 線路11上，利用^ i 於綠漆12露出的雙面增層 錫球13，使棋肉植球作業（bdl implantati〇n)形成複數個 卽Hi 式晶片7得以電性導接至外部裝置， 玟：i f明之内埋式晶片導接構裝結構之製作。除了錫 幫助電性連接。接腳和或疋金屬凸塾等導電元件 有以;:優t發明之内埋式晶片導接構裝結構與製法’具 問題1:金屬承载件可提升晶片散熱效果’以及改善板彎鍾 成-2内=晶用?連可接直金屬 之整體高度。 連m線路’能降低封裝結構 改善線路之結構，不但能增加佈線面積，也可 本發明之内埋式晶片導接構裝結構，不僅能提升晶片 1353650 散熱效果也可改良板彎翹的問題，再者，藉由雙面增層線 路之設計，使得佈線面積增加，也增加電路板佈局之靈活 性。 雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 1353650 【圖式簡單說明】 第1〜12圖為一系列剖面圖，用以說明本發明實施例製 作内埋式晶片導接構裝結構之流程。 【主要元件符號說明】 2〜凹槽； 4〜絕緣層； 5a~内層線路； 7〜晶片； 8〜黏著劑； 10〜開孔； 12〜綠漆， 1〜金屬承載件； 3〜導通孔； 5 ~金屬層； 6〜油墨； 7a〜鋅點底層金屬； 9〜介電層； 11〜增層線路； 13〜錫球01353650 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor package structures, and more particularly to a buried wafer via structure. [Prior Art] In the new generation of electronic products, the pursuit of thinner, lighter, shorter, more demanding products with versatility and high performance, therefore, integrated circuit (1C) must accommodate more electronics in a limited space In order to achieve high density and miniaturization, the electronic industry has developed a new packaging technology to embed semiconductor wafers in the substrate, greatly reducing the size of the package and shortening the connection path between the short wafer and the substrate. Build-up Increases cabling area to meet the trend of light, short, and versatile. However, in conjunction with the internal burial of the wafer, the heat generated during the operation of the wafer is also greatly increased. If the heat cannot be removed in time, the performance of the semiconductor wafer will be seriously affected. In addition, the heat treatment (such as baking) in the process may cause the board to bend. Produced, therefore, the industry has proposed various package structures to improve the above problems. * Taiwan Patent No. 1251916 proposes a heat sink, a recess is formed on the heat sink, and then the wafer and the passive component are placed in the recess, and the fabricated buildup structure is coupled to the heat sink, and the heat sink is coupled. To the semiconductor wafer, the heat generated by the operation of the semiconductor wafer can be effectively dissipated. Taiwan Patent No. 1,237,885 proposes a double carrier composed of different materials. The second carrier is formed on the first carrier and forms a recess on the second carrier. After the semiconductor wafer is placed, a dielectric is formed thereon. Layer, subsequent buildup structure. The carrier is composed of two different materials, so that the bonding structure of the bearing structure and the wafer during the etching process is flat, so as to improve the quality and reliability of the process after the 5 1353650. U.S. Patent No. 6,709,098 proposes forming a plurality of openings in a heat dissipating member, and then placing the wafer into the opening to form a dielectric layer on the outside of the wafer and the heat dissipating plate, and then forming a layered structure on the surface of the dielectric layer. The heat sink is coupled to the semiconductor wafer to effectively dissipate heat. Therefore, there is a need in the industry to provide a buried wafer guiding structure, which is relatively simple in process, and at the same time, can improve the heat dissipation effect of the wafer and improve the bending of the board. * [Explanation] One of the objects of the present invention is to provide a semiconductor embedded wafer-conducting structure and a method for manufacturing the same, which can improve the heat dissipation effect of the wafer and improve the bending of the board. To achieve the above and other objects, the present invention provides a method for fabricating a semiconductor buried wafer via structure, comprising the steps of: providing a metal carrier; forming a recess and a plurality of vias in the metal carrier; Forming an insulating layer on the metal carrier, the insulating layer conformingly covering the φ groove and the surface of the via holes; forming a metal layer conformally on the insulating layer; filling the via holes with ink Patterning the metal layer to form an inner layer line; placing and fixing a semiconductor wafer in the recess; covering a dielectric layer over the wafer and the inner layer line; forming a plurality of layers in the dielectric layer Openings are formed to expose the inner layer line; and a build-up line is formed on opposite sides of the metal carrier, and the build-up line is electrically connected to the inner layer line via the openings. The present invention also provides a semiconductor embedded wafer guiding structure, comprising: a metal carrier having a recess and a plurality of via holes of 6 1353650; an insulating layer conformingly covering the recess And a surface of the via hole; an inner layer line formed on the insulating layer; an ink filled in the via holes; a semiconductor wafer fixed in the recess; a dielectric layer formed on the semiconductor a plurality of openings to expose the inner layer line; and a build-up line formed on opposite sides of the metal carrier, the build-up line electrically connecting the inner layer via the openings . The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims 1 to 12 illustrate in detail the method of fabricating the semiconductor buried wafer guiding structure of the embodiment of the present invention. It is to be noted that the drawings are a simplified schematic diagram to emphasize the features of the present invention, and thus the element dimensions in the drawings are not drawn to the actual scale. Embodiments of the invention may also include elements not shown in the figures. Referring to FIG. 1 , a metal core 1 is first provided. The metal carrier 1 may be made of a metal such as Cu, Al, or Ni, but is not limited to a single metal, and may be a combination of the above metals or An alloy, of which Cu is preferred. The advantage of using metal as a carrier is that it can improve the heat dissipation of the wafer and improve the bending of the board. Referring to FIG. 2, a recess 2 and a plurality of through holes 3 are formed on the metal carrier 1. The method of forming the recess 2 can utilize physical metal machining techniques or utilize Chemical etching technology. The groove 2 is for embedding the inside of the wafer, so that the volume of the integral structure 7 1353650 is greatly reduced, and the size of the groove 2 depends on the size of the wafer in practical use. Generally, the size of the groove 2 is generally small. Larger than the wafer, the wafer is smoothly fixed and aligned. The purpose of forming the via hole 3 is to establish a conductive path on the front and back sides of the metal carrier 1 so as to facilitate the subsequent double-sided build-up line 11 'method can be drilled by a numerical control tool machine (numerical c^ntr〇l, NC) Or other drilling techniques. Referring to FIG. 3, an insulating layer 4 is formed on the metal carrier. The insulating layer 4 can conformably cover the surface of the groove 2 and the via hole 3 by coating or electrodeposition to electrically insulate the metal carrier from the subsequent line. Generally, the thickness of the insulating layer 4 is about 5 μm to 65 μm. The insulating layer 4 can be various polymer materials, such as: epoxy resin (expoxy resm), polydecylamine (p〇lyimide), cyanide (tetra) (10) batch of ester), bismaieimide triazine (bismaieimide triazine) Or a combination of the above, or a polymer composite material, for example, a polymer material mixed with glass fiber, clay or Tauman. Referring to FIG. 4, the metal layer 5 is formed conformally on the insulating layer 4. The method for forming the metal layer 5 includes, but is not limited to, a plating/through hole (PTH) technique, or a sputtering or an electroless plating method, wherein the metal layer 5 is generally made of a material. Cu with high conductivity is selected. Then, referring to Fig. 5, a potting process is carried out to fill the ink holes 6 into the via holes 3, and the ink 6 used is, for example, a resin ink. Referring to Figure 6, the metal layer 5 is patterned to form an inner layer line 5a. The patterning process includes the steps of internally exposing the metal layers 5, and performing the steps of development, etching, and stripping, the so-called DES method. After patterning, 8 1353650 forms a patterned inner layer line 5a on the insulating layer 4 on the upper and lower sides of the metal carrier 1. Referring to FIG. 7, a semiconductor wafer 7 is placed and fixed in the recess 2 by a thermally conductive adhesive material, wherein the thermally conductive adhesive 8 can be an underfill or a ring. Epoxy, or die attach film (DAF). The thermally conductive adhesive 8 can reduce the thermal stress generated by the difference in thermal expansion between the semiconductor wafer 7 and the metal carrier 1, and can increase the heat dissipation efficiency of the semi-lub conductor wafer 7. Forming a plurality of under bump metallurgy (UBM) 7a' on the semiconductor wafer 7 via an electroless plating process, wherein the positions of the underlying metal of the solder joints correspond to a predetermined position of the opening on the wafer, In order to prevent the solder from reacting with the conductive substrate in the subsequent process, the material of the UBM is preferably nickel/gold. Next, referring to Fig. 8, a dielectric layer 9 is overlaid on the semiconductor wafer 7 and the inner layer line 5a to facilitate the subsequent build-up line. The dielectric layer 9 may be a photosensitive resin or a non-photosensitive resin, for example, an epoxy resin, a bismaleimide triaeine (BT), or an ajinomoto build-up film. , p〇ly phenylene oxide (PPE), or polytetrafluoroethylene (PTFE). Referring to Fig. 9, a hole 10 is formed in the dielectric layer by laser drilling to expose the inner layer 5 through the opening 10 and the subsequent process. a. The inner layer line 5a is shown in Fig. 10' in the metal carrier 增 build-up line 11' so that the build-up line 11 passes through the splitter, and a layer 5a is formed on both sides. In the second figure, the conductive 9 is electrically connected to the inner spring member 1 to form the conduction 9 side, and the second is formed: the opposite two wiring areas formed on the metal carrier 1 are also caused by: electricity; The layer structure not only increases the problem: it also improves the process quality and can be uniform 2 and reduces the shape of the plate. iU::, the process of the layer-added line needs to be directly on the painted line before the carrier and the wafer. In the present invention, an inner layer is formed on the carrier to be connected to the subsequent surface, and the structure is used to reduce the overall package height. 12, to protect the buried 2 sides: layer line 11 coated with - green paint welding short circuit. Then two = avoid oxidation of the double-sided build-up line 11 and on the line 11, using the double-sided layered solder ball 13 exposed by the green paint 12, so that the buck implantati〇n forms a plurality of 卽Hi The wafer 7 is electrically connected to an external device, and the fabrication of the embedded wafer guiding structure is as follows. In addition to tin help electrical connections. Conductive components such as pins and bismuth metal tabs are available;: The embedded wafer layout structure and method of the invention are excellent. The problem is that the metal carrier can improve the heat dissipation effect of the wafer and improve the bending of the board. -2 inside = crystal can be connected to the overall height of the straight metal. The m-line can reduce the structure of the package structure and improve the structure of the circuit, which not only can increase the wiring area, but also can embed the structure of the buried wafer of the present invention, which can not only improve the heat dissipation effect of the 1353650 but also improve the bending of the board. Moreover, the design of the double-sided build-up line increases the wiring area and increases the flexibility of the board layout. While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and it is possible to make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. 1353650 [Brief Description of the Drawings] Figs. 1 to 12 are a series of sectional views for explaining the flow of the buried wafer guiding structure of the embodiment of the present invention. [Main component symbol description] 2~groove; 4~insulating layer; 5a~ inner layer wiring; 7~ wafer; 8~adhesive; 10~opening; 12~green lacquer, 1~metal carrier; 3~via 5 ~ metal layer; 6 ~ ink; 7a ~ zinc point underlying metal; 9 ~ dielectric layer; 11 ~ build-up line; 13 ~ tin ball 0
1212