TW202013652A - 微電子總成 - Google Patents

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TW202013652A
TW202013652A TW108115558A TW108115558A TW202013652A TW 202013652 A TW202013652 A TW 202013652A TW 108115558 A TW108115558 A TW 108115558A TW 108115558 A TW108115558 A TW 108115558A TW 202013652 A TW202013652 A TW 202013652A
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Taiwan
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die
conductive
interconnect
coupled
interconnections
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TW108115558A
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English (en)
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TWI829688B (zh
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艾戴爾 艾爾雪
費洛斯 伊德
喬漢娜 史旺
蕭納 力芙
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美商英特爾股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

微電子總成、相關的裝置及方法被揭露於文中。於一些實施例中，一種微電子總成可包括一封裝基材，其具有一第一表面及一相對的第二表面；一被嵌入一第一電介質層中之第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒之該第一表面係藉由第一互連而被耦合至該封裝基材之該第二表面；一被嵌入一第二電介質層中之第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及一被嵌入一第三電介質層中之第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。

Description

微電子總成
本發明係有關微電子總成。
積體電路(IC)晶粒係傳統上耦合至封裝基材，以利機械穩定性並促進連接至其他組件，諸如電路板。可由傳統基材所達成的互連節距係由製造、材料、及熱考量(除了其他者之外)所侷限。
及
微電子總成(及相關的裝置和方法)被揭露於文中。例如，於一些實施例中，一種微電子總成可包括一封裝基材，其具有一第一表面及一相對的第二表面；一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中且其中該第一晶粒之該第一表面係藉由第一互連而被耦合至該封裝基材之該第二表面；一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中且其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。
由於此等晶粒的漸小尺寸、熱侷限、及功率遞送侷限(除了其他者之外)，在多晶粒IC封裝中的二或更多晶粒之間傳遞大量信號是有挑戰性的。文中所揭露的實施例之個別者可協助達成多數IC晶粒之可靠裝附，以較低的成本、具有增進的功率效率、具有較高的頻寬、及/或具有較大的設計彈性，相對於傳統方式。文中所揭露的微電子總成之個別者可展現較佳的功率遞送及信號速度，而同時減小封裝之大小，相對於傳統方式。文中所揭露之微電子總成可特別地有利於電腦、平板、工業機器人、消費電子裝置(例如，穿戴式裝置)中之小型且低調的應用。
於以下詳細描述中，參考其形成其一部分的後附圖形，其中類似的數字係指定遍及全文之類似部件，且其中係藉由可被實行之說明性實施例來顯示。應理解其他實施例可被利用，且結構或邏輯改變可被實行而不背離本發明之範圍。因此，下列詳細描述不應被視為限制。
各個操作可被描述為多重離散的依序動作或操作，以一種最有助於瞭解所請求標的之方式。然而，描述之順序不應被當作暗示這些操作一定是跟順序相關的。特別地，這些操作可不以所提呈之順序來執行。所述之操作可被執行以與所述實施例不同的順序。各種額外操作可被執行及/或所述的操作可被省略於額外的實施例中。
為了本發明之目的，用語「A及/或B」表示(A)、(B)、或(A及B)。為了本發明之目的，用語「A、B及/或C」表示(A)、(B)、(C)、(A及B)、(A及C)、(B及C)、或(A、B及C)。圖形不一定依比例。雖然許多圖形繪示具有平坦壁及直角角落之直線結構，但此僅為了易於闡明，且使用這些技術所製造的實際裝置將展現圓形角落、表面粗糙度、及其他特徵。
描述係使用用語「於一實施例中」、或「於實施例中」，其可指稱一或更多相同或者不同的實施例。再者，術語「包含」、「包括」、「具有」等等(如針對本發明之實施例所使用者)為同義的。如文中所使用，「封裝」及「IC封裝」是同義的，如「晶粒」及「IC晶粒」也是。術語「頂部」及「底部」可被使用於文中以解釋圖形之各個特徵，但這些術語僅為了討論之簡易，且並未暗示所欲的或需要的定向。如文中所使用，術語「絕緣」係指「電絕緣」，除非另有指明。
當用以描述尺寸之範圍時，用詞「介於X與Y之間」代表其包括X及Y之範圍。為了簡便，用詞「圖4」可被用以指稱圖4A-4I之圖形的集合，用詞「圖6」可被用以指稱圖6A-6F之圖形的集合，依此類推。雖然某些元件可在文中被指稱以單數，但此等元件仍可包括多數子元件。例如，「一絕緣材料」可包括一或更多絕緣材料。如文中所使用，「導電接點」可指稱導電材料(例如，金屬)之一部分，其係作用為介於不同組件之間的電介面；導電接點可被凹陷在、齊平與、或延伸遠離組件之表面，且可具有任何適當形式(例如，導電墊或插口、或者導電線或通孔之部分)。
圖1A為一微電子總成100之側面、橫斷面視圖，依據各個實施例。微電子總成100可包括封裝基材102，其係耦合至具有多階互連之多層晶粒總成104。如文中所使用，術語「多層晶粒總成」可指稱一具有三或更多堆疊電介質層之複合晶粒，以一或更多晶粒嵌入各層中，且導電互連及/或導電路徑係連接該等一或更多晶粒，包括非相鄰層中之晶粒。如文中所使用，術語「多層晶粒總成」及「複合晶粒」可被可交換地使用。如文中所使用，術語「多階互連」可指稱介於第一組件與第二組件之間的互連，其中第一組件及第二組件不在相鄰層中；或者可指稱一跨越一或更多層之互連(例如，介於第一層中的第一晶粒與第三層中的第二晶粒之間的互連、或介於封裝基材與第二層中的晶粒之間的互連)。如圖1A中所示，多層晶粒總成104可包括三層。特別地，多層晶粒總成104可包括具有晶粒114-1和晶粒114-4之第一層104-1、具有晶粒114-2之第二層104-2、及具有晶粒114-3、晶粒114-5、和晶粒114-6之第三層104-3。第一層104-1中之晶粒114-1可藉由晶粒至封裝基材(DTPS)互連150-1而被耦合至封裝基材102，可藉由晶粒至晶粒(DTD)互連130-1而被耦合至第二層104-2中之晶粒114-2，及可藉由多階(ML)互連152而被耦合至第三層104-3中之晶粒114-3。封裝基材102之頂部表面可包括一組導電接點146。晶粒114-1、114-2及114-4可包括晶粒之底部表面上的一組導電接點122、及晶粒之頂部表面上的一組導電接點124。晶粒114-3、114-5、114-6可包括晶粒之底部表面上的一組導電接點122。如針對晶粒114-1所示，晶粒114-1之底部表面上的導電接點122可藉由DTPS互連150-1而被電氣地且機械地耦合至封裝基材102之頂部表面上的導電接點146；晶粒114-1之頂部表面上的導電接點124可藉由DTD互連130-1而被電氣地且機械地耦合至晶粒114-2之底部表面上的導電接點122，並進一步可藉由ML互連152而被電氣地且機械地耦合至晶粒114-3之底部表面上的導電接點122。如針對晶粒114-4所示，晶粒114-4之底部表面上的導電接點122可藉由DTPS互連150-1而被電氣地且機械地耦合至封裝基材102之頂部表面上的導電接點146；晶粒114-4之頂部表面上的導電接點124可藉由DTD互連130-1而被電氣地且機械地耦合至晶粒114-2之底部表面上的導電接點122，並進一步可藉由ML互連152而被電氣地且機械地耦合至晶粒114-5之底部表面上的導電接點122。如針對晶粒114-2所示，晶粒114-2之底部表面上的導電接點122可藉由ML互連152而被電氣地且機械地耦合至封裝基材102之頂部表面上的導電接點146，且可藉由DTD互連130-1而被電氣地且機械地耦合至晶粒114-1及114-4之頂部表面上的導電接點124；晶粒114-2之頂部表面上的導電接點124可藉由DTD互連130-1及130-2而被電氣地且機械地耦合至晶粒114-3和114-5、及114-6之底部表面上的導電接點122，個別地。如針對晶粒114-3所示，晶粒114-3之底部表面上的導電接點122進一步可藉由ML互連152而被電氣地及機械地耦合至晶粒114-2之頂部表面的導電接點124並耦合至封裝基材之頂部表面上的導電接點146。如針對晶粒114-5所示，晶粒114-5之底部表面上的導電接點122進一步可藉由ML互連152而被電氣地及機械地耦合至晶粒114-4之頂部表面的導電接點124。如針對晶粒114-6所示，晶粒114-6之底部表面上的導電接點122進一步可藉由DTD互連130-2而被電氣地及機械地耦合至晶粒114-2之頂部表面的導電接點124。
ML互連152可由任何適當的導電材料所形成，諸如銅、銀、鎳、金、鋁、或者其他金屬或合金，舉例而言。ML互連152可使用任何適當製程來形成，包括(例如)參考圖4所述之製程。於一些實施例中，文中所揭露的ML互連152可具有介於100微米與300微米之間的節距。ML互連152可提供介於多層晶粒總成104的一或更多晶粒114、及/或封裝基材102的一或更多晶粒114之間的更直接導電路徑。ML互連之更直接連接(亦即，更短的導電路徑)可增進微電子總成之性能，藉由增加頻寬、藉由減少電阻值、藉由降低寄生、及/或藉由更有效率地從封裝基材102至一或更多晶粒114遞送功率。
於一些實施例中，封裝基材102可使用一種微影界定的封裝製程來形成。於一些實施例中，封裝基材102可使用標準有機封裝製程來製造，而因此封裝基材102可具有有機封裝之形式。於一些實施例中，封裝基材102可為一組形成在面板載體上之再分佈層(例如，如圖5中所示)，藉由疊層或旋塗在電介質材料上、並藉由雷射鑽孔和電鍍來產生導電通孔。於一些實施例中，封裝基材102可使用任何適當技術(諸如再分佈層技術)而被形成在可移除載體上。用於封裝基材102之製造的本技術中已知的任何方法可被使用，而為了簡潔的緣故，此等方法將不會被更詳細地討論於文中。
於一些實施例中，封裝基材102可為較低密度媒體而晶粒114(例如，晶粒114-4)可為較高密度媒體或具有包括較高密度媒體之區域。如文中所使用，術語「較低密度」及「較高密度」是相對術語，指示其在較低密度媒體中之導電路徑(例如，導電互連、導電線、及導電通孔)係比在較高密度媒體中之導電路徑更大及/或具有較大的節距。於一些實施例中，較高密度媒體可使用具有先進微影(具有藉由先進雷射或微影製程所使用的小型垂直互連特徵)之經修改半附加製程或半附加建立製程來製造，而較低密度媒體可為使用標準印刷電路板(PCB)製程(例如，標準消去製程，其係使用蝕刻化學以移除不想要的銅之區域、且具有藉由標準雷射製程所形成的粗垂直互連特徵)所製造的PCB。於其他實施例中，較高密度媒體可使用半導體製程(諸如單金屬鑲嵌製程或雙金屬鑲嵌製程)來製造。
如圖1中所示，晶粒114-1之DTPS互連150-1可具有與晶粒114-4之DTPS互連150-2不同的節距。於一些實施例中，如晶粒114-4上所示，DTPS互連150可具有在相同晶粒上之不同節距。例如，晶粒114-4之DTPS互連150-1可具有與晶粒114-4之DTPS互連150-2不同的節距。於另一範例中，頂部表面上之晶粒114-2可具有DTD互連130-1，其可具有與相同表面上之DTD互連130-2不同的節距。具有在相同表面上之不同節距的互連130之晶粒114可被稱為混合節距晶粒114。於一些實施例中，DTD互連可具有介於5微米與200微米之間(例如，介於5微米與100微米之間)的節距。於一些實施例中，DTPS互連可具有介於200微米與800微米之間(例如，介於300微米與600微米之間)的節距。
雖然圖1A顯示晶粒114-1、114-2、及114-4為雙側晶粒而晶粒114-3、114-5、及114-6為單側晶粒，但晶粒114亦可為單側或雙側晶粒且可為單節距晶粒或混合節距晶粒。於一些實施例中，額外組件可被配置在晶粒114-3、114-5、及/或114-6之頂部表面上。額外被動組件(諸如表面安裝電阻、電容、及/或電感)可被配置在封裝基材102之頂部表面或底部表面上、或者被嵌入封裝基材102中。於此背景下，雙側晶粒係指稱具有在兩表面上之連接。於一些實施例中，雙側晶粒可包括穿越矽通孔(TSV)，用以形成兩表面上之連接。雙側晶粒之主動表面(其為含有一或更多主動裝置及大部分互連的表面)可根據設計及電氣需求而面對任一方向。
雖然圖1A顯示一特定配置中之晶粒114，但晶粒114可於任何適當的配置中。例如，來自第三層104-3之晶粒114-3可以一重疊距離191延伸在第一層104-1之晶粒114-1上方，並可以一重疊距離193延伸在第二層104-2之晶粒114-2上方。重疊距離191、193可為任何適當的距離。於一些實施例中，重疊距離191可介於0.5毫米與50毫米之間(例如，介於0.75毫米與20毫米之間，或大約10毫米)。於一些實施例中，重疊距離193可介於0.25毫米與5毫米之間。
圖1B為圖1A之微電子總成100的晶粒114-2之頂部視圖，其顯示「較粗的」導電接點124-1及「較細的」導電接點124-2。微電子總成100之晶粒114-2可為單側晶粒(由於晶粒114-2僅具有導電接點在單一表面上)，或者(如圖所示)可為雙側晶粒(由於晶粒114-2具有導電接點122、124在兩表面(例如，頂部表面及底部表面)上)，且可為混合節距晶粒(由於晶粒114-2具有多組包括不同節距之導電接點124-1、124-2)。雖然圖1B繪示導電接點124-1、124-2為配置在矩形陣列中，但導電接點124-1、124-2可被配置以任何適當的型態(例如，三角形、六角形、矩形、介於導電接點124-1、124-2之間的不同配置，等等)。文中所揭露之導電接點的任一者(例如，導電接點122、124及/或146)可包括接合墊、焊料凸塊、導電柱、或任何其他適當的導電接點，舉例而言。
圖1C為圖1A之微電子總成100的晶粒114-2之底部視圖，其顯示「較粗的」導電接點122-1及「較細的」導電接點122-2。微電子總成100之晶粒114-2可為雙側晶粒(如圖所示)，或可為單側晶粒，且可為混合節距晶粒(如圖所示)，或可為單節距晶粒。雖然圖1C繪示導電接點122-1、122-2為配置在矩形陣列中，但導電接點122-1、122-2可被配置以任何適當的型態(例如，三角形、六角形、矩形、介於導電接點122-1、122-2之間的不同配置，等等)。
如以上所討論，在圖1A之實施例中，晶粒114-1可在微電子總成100之局部化區域中提供高密度互連選路。於一些實施例中，晶粒114-1之存在可支援其無法被完整地直接裝附至封裝基材102之細節距半導體晶粒(例如，晶粒114-2、114-3、及114-5)的直接晶片裝附。特別地，如以上所討論，晶粒114-1可支援其無法在封裝基材102中達成的軌線寬度及間隔。穿戴式和行動電子裝置、以及物聯網(IoT)應用的成長正驅使電子系統之大小的減小，但PCB製程之限制以及在使用期間之熱膨脹的機械結果已代表其具有細互連節距之晶片無法被直接地安裝至PCB。文中所揭露之微電子總成100的各個實施例可以支援具有高密度互連之晶片及具有低密度互連之晶片而不犧牲性能或可製造性。
圖1A之微電子總成100亦可包括電路板(未顯示)。封裝基材102可藉由封裝基材102之底部表面上的第二階互連而被耦合至電路板。第二階互連可為任何適當的第二階互連，包括用於球柵陣列配置之焊球、管腳柵陣列配置中之管腳、或陸柵陣列配置中之陸。電路板可為主機板(舉例而言)，且可具有裝附至電路板之其他組件。電路板可包括導電路徑及其他導電接點，用以發送電力、接地、及信號通過電路板，如本技術中所已知者。於一些實施例中，第二階互連可不將封裝基材102耦合至電路板，但可替代地將封裝基材102耦合至另一IC封裝、插入器、或任何其他適當組件。於一些實施例中，多層晶粒總成可不被耦合至封裝基材102，但可替代地被耦合至電路板，諸如PCB。
圖1A之微電子總成100亦可包括下填材料127。於一些實施例中，下填材料127可延伸在晶粒114的一或更多者與相關DTPS互連150周圍的封裝基材102之間。於一些實施例中，下填材料127可延伸在相關DTD互連130周圍之晶粒114的不同者之間。下填材料127可為絕緣材料，諸如適當的環氧樹脂材料。於一些實施例中，下填材料127可包括毛細管下填、非導電膜(NCF)、或模製下填。於一些實施例中，下填材料127可包括環氧樹脂焊劑，其係協助將晶粒114-1、114-4焊接至封裝基材102(當形成DTPS互連150-1及150-2時)，並接著聚合且囊封DTPS互連150-1及150-2。下填材料127可被選擇以具有其可減輕或最小化介於晶粒114與封裝基材102之間的應力之熱膨脹係數(CTE)，該應力係來自微電子總成100中之不均勻熱膨脹。於一些實施例中，下填材料127之CTE可具有其位於封裝基材102之CTE(例如，封裝基材102之電介質材料的CTE)與晶粒114之CTE的中間之值。
文中所揭露之DTPS互連150可具有任何適當形式。於一些實施例中，一組DTPS互連150可包括焊料(例如，其接受熱回流以形成DTPS互連150之焊料凸塊或球)。其包括焊料之DTPS互連150可包括任何適當的焊料材料，諸如鉛/錫、錫/鉍、共晶錫/銀、三元錫/銀/銅、共晶錫/銅、錫/鎳/銅、錫/鉍/銅、錫/銦/銅、錫/鋅/銦/鉍、或其他合金。於一些實施例中，一組DTPS互連150可包括各向異性導電材料，諸如各向異性導電膜或各向異性導電膏。各向異性導電材料可包括散佈在非導電材料中之導電材料。於一些實施例中，各向異性導電材料可包括嵌入在黏結劑或熱固黏著劑膜(例如，熱固聯苯型環氧樹脂、或丙烯酸為基的材料)中之微觀導電粒子。於一些實施例中，導電粒子可包括聚合物及/或一或更多金屬(例如，鎳或金)。例如，導電粒子可包括塗鎳的金或塗銀的銅，其被依次地塗敷以聚合物。於另一範例中，導電粒子可包括鎳。當各向異性導電材料是未壓縮的時，則可能沒有從該材料之一側至另一側的導電路徑。然而，當各向異性導電材料被充分地壓縮(例如，藉由各向異性導電材料之任一側上的導電接點)時，則接近壓縮之區的導電材料可彼此接觸以形成在壓縮之區中從該膜之一側至另一側的導電路徑。
文中所揭露之DTD互連130可具有任何適當形式。DTD互連130可具有比微電子總成中之DTPS互連150更細的節距。於一些實施例中，一組DTD互連130之任一側上的晶粒114可為未封裝晶粒，及/或DTD互連130可包括小型導電凸塊(例如，銅凸塊)，其係藉由焊料而被裝附至導電接點124。DTD互連130可能具有太細的節距而無法直接地耦合至封裝基材102(例如，太細而無法作用為DTPS互連150)。於一些實施例中，一組DTD互連130可包括焊料。包括焊料之DTD互連130可包括任何適當的焊料材料，諸如以上所討論的材料之任一者。於一些實施例中，一組DTD互連130可包括各向異性導電材料，諸如以上所討論的材料之任一者。於一些實施例中，DTD互連130可被使用為資料轉移道，而DTPS互連150可被用於電力及接地線，除了其他者之外。
於一些實施例中，微電子總成100中之DTD互連130的部分或全部可為金屬至金屬互連(例如，銅至銅互連、或電鍍互連)。於此等實施例中，在DTD互連130之任一側上的導電接點122、124可被接合在一起(例如，於升高的壓力及/或溫度之下)而不使用中間焊料或各向異性導電材料。於一些實施例中，焊料之薄蓋可被使用於金屬至金屬互連中以提供平坦度，且此焊料可變為處理期間之介金屬化合物。在其利用併合接合的一些金屬至金屬互連中，電介質材料(例如，氧化矽、氮化矽、碳化矽、或有機層)可存在於其接合在一起的金屬之間(例如，於其提供相關導電接點124的銅墊或柱之間)。於一些實施例中，DTD互連130之一側可包括金屬柱(例如，銅柱)，而DTD互連之另一側可包括凹陷在電介質中之金屬接點(例如，銅接點)。於一些實施例中，金屬至金屬互連(例如，銅至銅互連)可包括貴金屬(例如，金)或其氧化物係可導電的金屬(例如，銀)。於一些實施例中，金屬至金屬互連可包括金屬奈米結構(例如，奈米棒)，其可具有減小的熔點。金屬至金屬互連可以可靠地導通比其他類型互連更高的電流；例如，當電流流動時一些焊料互連可形成脆的介金屬化合物，而通過此等互連所提供的最大電流可被侷限以減輕機械故障。
於一些實施例中，微電子總成100中之DTD互連130的部分或全部可為包括焊料之焊料互連，該焊料具有比DTPS互連150之部分或全部中所包括的焊料更高的熔點。例如，當微電子總成100中之DTD互連130被形成在DTPS互連150被形成以前時(例如，如參考圖4而討論於下)，焊料為基的DTD互連130可使用較高溫度的焊料(例如，具有高於攝氏200度之熔點)，而DTPS互連150可使用較低溫度的焊料(例如，具有低於攝氏200度之熔點)。於一些實施例中，較高溫度的焊料可包括錫；錫和金；或錫、銀、和銅(例如，96.5%錫、3%銀、及0.5%銅)。於一些實施例中，較低溫度的焊料可包括錫和鉍(例如，共晶錫鉍)或錫、銀、和鉍。於一些實施例中，較低溫度的焊料可包括銦、銦和錫、或鎵。
在文中所揭露的微電子總成100中，DTPS互連150之部分或全部可具有比DTD互連130之部分或全部更大的節距。DTD互連130可具有比DTPS互連150更小的節距，由於在一組DTD互連130之任一側上的不同晶粒114中之材料的更大類似度，相較於在一組DTPS互連150之任一側上的晶粒114與封裝基材102之間。特別地，晶粒114及封裝基材102之材料組成中的差異可導致晶粒114及封裝基材102之差分擴張及收縮，由於在操作期間所產生的熱(以及在各個製造操作期間所施加的熱)。為了減輕由此差分擴張及收縮所造成的損害(例如，破裂、焊料橋接，等等)，DTPS互連150可被形成比DTD互連130更大且更遠離，其可經歷較少的熱應力，由於在DTD互連之任一側上的該對晶粒114之較大的材料類似度。於一些實施例中，文中所揭露的DTPS互連150可具有介於80微米與300微米之間的節距，而文中所揭露的DTD互連130可具有介於7微米與100微米之間的節距。
雖然圖1A繪示特定數目及配置的DTPS互連150、DTD互連130、及ML互連152，但這些僅為說明性的，且任何適當的數目及配置均可被使用。文中所揭露的互連(例如，DTPS、DTD、及ML互連)可由任何適當的導電材料所形成，諸如銅、銀、鎳、金、鋁、或者其他金屬或合金，舉例而言。
多層晶粒總成104可包括絕緣材料(例如，多數層中所形成的電介質材料，如本技術中所已知者)以形成多數層並將一或更多晶粒嵌入層中。於一些實施例中，多層晶粒總成之絕緣材料可為電介質材料，諸如有機電介質材料、阻燃第4級材料(FR-4)、雙馬來亞醯胺三氮雜苯(BT)樹脂、聚醯亞胺材料、玻璃強化的環氧樹脂矩陣材料、或低k及超低k電介質(例如，碳摻雜的電介質、氟摻雜的電介質、多孔電介質、及有機聚合物電介質)。多層晶粒總成104可包括通過電介質材料之一或更多ML互連(例如，包括導電通孔及/或導電柱，如圖所示)。多層晶粒總成104可具有任何適當的尺寸。例如，於一些實施例中，多層晶粒總成104之厚度可介於100 um與2000 um之間。多層晶粒總成104可具有任何適當數目的層、任何適當數目的晶粒、及任何適當數目的晶粒配置。例如，於一些實施例中，多層晶粒總成104可具有介於3與20層的晶粒之間。於一些實施例中，多層晶粒總成104可包括一具有介於2與10晶粒之間的層。
封裝基材102可包括絕緣材料(例如，形成在多數層中之電介質材料，如本技術中所已知者)及通過電介質材料之一或更多導電路徑(例如，包括導電軌線及/或導電通孔，如圖所示)。於一些實施例中，封裝基材102之絕緣材料可為電介質材料，諸如有機電介質材料、阻燃第4級材料(FR-4)、BT樹脂、聚醯亞胺材料、玻璃強化的環氧樹脂矩陣材料、具有無機填料或低k及超低k電介質之有機電介質(例如，碳摻雜的電介質、氟摻雜的電介質、多孔電介質、及有機聚合物電介質)。特別地，當封裝基材102係使用標準PCB製程來形成時，封裝基材102可包括FR-4，而封裝基材102中之導電路徑可由銅之圖案化薄片(其係由FR-4之建立層所分離)來形成。封裝基材102中之導電路徑可由襯裡材料來圍住，諸如黏合襯裡及/或障壁襯裡，如適當者。
文中所揭露之晶粒114可包括絕緣材料(例如，在多數層中所形成的電介質材料，如本技術中所已知者)以及透過絕緣材料所形成的多數導電路徑。於一些實施例中，晶粒114之絕緣材料可包括電介質材料，諸如二氧化矽、氮化矽、玻璃強化的環氧樹脂矩陣材料、或低k及超低k電介質(例如，碳摻雜的電介質、氟摻雜的電介質、多孔電介質、及有機聚合物電介質、光可成像電介質、及/或苯環丁烯為基的聚合物)。於一些實施例中，晶粒114之絕緣材料可包括半導體材料，諸如矽、鍺、或III-V材料(例如，氮化鎵)、及一或更多額外材料。例如，絕緣材料可包括氧化矽或氮化矽。晶粒114中之導電路徑可包括導電軌線及/或導電通孔，並可以任何適當方式連接晶粒114中之任何導電接點(例如，連接晶粒114之相同表面上或不同表面上的多數導電接點)。範例結構可被包括在文中所揭露的晶粒114中且參考圖9而被討論於下。晶粒114中之導電路徑可由襯裡材料來圍住，諸如黏合襯裡及/或障壁襯裡，如適當者。
於一些實施例中，晶粒114-1及/或晶粒114-4可包括導電路徑，用以將電力、接地、及/或信號發送至/自微電子總成100中所包括的一些其他晶粒114。例如，晶粒114-1、114-4可包括TSV，包括導電材料通孔，諸如金屬通孔(其係藉由障壁氧化物而被隔離自周圍的矽或其他半導體材料)、或其他導電路徑，透過該等導電路徑可將電力、接地、及/或信號傳輸於晶粒114-1、114-4之「頂部上」(例如在一或更多上層中)的封裝基材102與一或更多晶粒114(例如，於圖1A之實施例中，晶粒114-2、晶粒114-3、晶粒114-5、及/或晶粒114-6)之間。於一些實施例中，晶粒114-1、114-4可包括導電路徑，用以將電力、接地、及/或信號發送於晶粒114-1、114-4之「頂部上」的不同晶粒114(例如，於圖1A之實施例中，晶粒114-2、晶粒114-3、晶粒114-5、及/或晶粒114-6)之間。於一些實施例中，晶粒114-1、114-4可為在微電子總成100中所包括的晶粒114-1、114-4及其他晶粒114之間所傳遞的信號之來源及/或目的地。
於一些實施例中，晶粒114-1無法將電力及/或接地發送至晶粒114-2；取而代之，晶粒114-2可藉由ML互連152而被直接地耦合至封裝基材102中之電力及/或接地線。藉由容許晶粒114-2經由ML互連152而直接地耦合至封裝基材102中之電力及/或接地線，此等電力及/或接地線無須透過晶粒114-1來發送，其容許晶粒114-1變得更小或者包括更多主動電路或信號路徑。
於一些實施例中，晶粒114-1、114-4可僅包括導電路徑，且可不含有主動或被動電路。於其他實施例中，晶粒114-1、114-4可包括主動或被動電路(例如，電晶體、二極體、電阻、電感、及電容，除了其他者之外)。於一些實施例中，晶粒114-1、114-4可包括一或更多裝置層，其包括電晶體(例如，如參考圖9之以下討論者)。當晶粒114-1、114-4包括主動電路時，電力及/或接地信號可被發送通過封裝基材102，且通過晶粒114-1、114-4之底部表面上的導電接點122而至晶粒114-1、114-4。
微電子總成100之元件可具有任何適當的尺寸。附圖之僅一子集被標示以代表尺寸之參考數字，但此僅為了闡明之清晰，且文中所揭露的任何微電子總成100可具有其具有文中所討論之尺寸的組件。於一些實施例中，封裝基材102之厚度164可介於0.1毫米與3毫米之間(例如，介於0.3毫米與2毫米之間，介於0.25毫米與0.8毫米之間，或大約1毫米)。
圖1A之微電子總成100的許多元件被包括在附圖之其他者中；這些元件之討論在當討論這些圖形時不被重複，且這些元件之任一者可具有文中所揭露的任何形式。於一些實施例中，文中所揭露之微電子總成100的個別者可作用為系統級封裝(SiP)，其中包括了具有不同功能之多數晶粒114。於此等實施例中，微電子總成100可被稱為SiP。
圖2A繪示一種配置，其中多數晶粒114A被配置在中間晶粒114B底下，多數晶粒114C被配置在中間晶粒114B之上，而晶粒114D被完全地配置在中間晶粒114B之上(例如，以參考晶粒114-6之文中所揭露的方式)。晶粒114可為相同晶粒或可為不同晶粒，且可包括任何適當的電路。例如，於一些實施例中，晶粒114A、114C、114D可為主動或被動晶粒，而晶粒114B可包括輸入/輸出電路、高頻寬記憶體、及/或增強動態隨機存取記憶體(EDRAM)。晶粒114A可以參考晶粒114-1之文中所揭露的任何方式而被連接至封裝基材102(未顯示)，並藉由文中所揭露的任何DTD互連而被連接至中間晶粒114B。晶粒114C及114D可藉由文中所揭露的任何DTD互連而被連接至中間晶粒114B。於圖2A中，晶粒114A「重疊」相鄰晶粒114C之邊緣205及/或角落207。將晶粒114A至少部分地置於晶粒114C之上可減少選路擁塞且可增進晶粒之利用，藉由以文中所揭露的任何ML互連來致能晶粒114A被連接至晶粒114C。晶粒114A、114C、及114D可為單側晶粒或雙側晶粒且可為單節距晶粒或混合節距晶粒。
圖2B為晶粒114B之頂部視圖，其顯示具有「較粗的」導電接點124-3及「較細的」導電接點124-4，其係配置以較細的導電接點124-4框住較粗的導電接點124-3。圖2A繪示多層晶粒之配置及晶粒之表面上的導電接點之配置，然而，這些配置僅為範例性的，且可使用任何適當的配置。
於圖1A之實施例中，多層晶粒總成104被繪示為具有三個層。於文中所揭露的微電子總成100之一些實施例中，多層晶粒總成104可具有多於三個層。例如，圖3繪示一種微電子總成100之實施例，其中多層晶粒總成104具有四個層104-1、104-2、104-3、104-4。第一層104-1可包括晶粒114-1及114-4，而第二層104-2可包括晶粒114-2，如以上參考圖1A所討論。第三層104-3可包括晶粒114-3及114-5，如以上參考圖1A所討論，其可進一步包括晶粒114-3、114-5之頂部表面上的導電接點124，且可省略晶粒114-6。第四層104-4可包括晶粒114-7、晶粒114-8及晶粒114-9，而晶粒114-7、114-8、114-9可包括晶粒114-7、114-8、114-9之底部表面上的導電接點122。如針對晶粒114-7所示，晶粒114-7之底部表面上的導電接點122可藉由DTD互連130-1及130-2而被電氣地及機械地耦合至晶粒114-3之頂部表面上的導電接點124。如針對晶粒114-8所示，晶粒114-8之底部表面上的導電接點122可藉由ML互連152而被電氣地及機械地耦合至晶粒114-2之頂部表面的導電接點124。如針對晶粒114-9所示，晶粒114-9之底部表面上的導電接點122可藉由DTD互連130-1及130-2而被電氣地及機械地耦合至晶粒114-5之頂部表面上的導電接點124，並可藉由ML互連152而被電氣地及機械地耦合至晶粒114-4之頂部表面上的導電接點124。
任何適當的技術均可被用以製造文中所揭露的微電子總成。例如，圖4A-4I為用以製造圖3之微電子總成100的範例製程中之各個階段的側面、橫斷面視圖，依據各個實施例。雖然參考圖4A-4I(以及代表製程之其他附圖)而討論於下之操作係以特定順序繪示，但這些操作可被履行以任何適當的順序。此外，雖然特定總成被繪示於圖4A-4I(以及代表製程之其他附圖)中，但參考圖4A-4I而討論於下之操作可被用以形成任何適當的總成。於一些實施例中，依據圖4A-4I之製程所製造的微電子總成100(例如，文中所揭露的任何微電子總成100)可具有其為焊料互連之DTPS互連150、及其為非焊料互連(例如，金屬至金屬互連或各向異性導電材料互連)之DTD互連130。於圖4A-4I之實施例中，晶粒114可首先被組合為複合晶粒，且接著複合晶粒可被耦合至封裝基材102。此方式可容許在DTD互連130之形成時的較嚴格的容許度，且針對相對小之晶粒114及針對具有三或更多層之複合晶粒是特別理想的。
圖4A繪示一種包括載體402之總成400A，在形成導電柱434於載體402之頂部表面上以後。載體402可包括用以在製造操作期間提供機械穩定性的任何適當材料。導電柱434可被配置以形成一或更多去填充區455，其中並無導電柱434存在。導電柱434可具有文中所揭露的任何實施例之形式，且可使用任何適當技術來形成，例如，微影製程或附加製程(諸如冷噴或3D列印)。例如，導電柱434可藉由沈積、曝光、及顯影載體402之頂部表面上的光阻劑層來形成。光阻劑層可被圖案化以形成導電柱之形狀的空腔。導電材料(諸如銅)可被沈積在經圖案化之光阻劑層中的開口中以形成導電柱434。導電材料可使用任何適當製程(諸如電鍍、濺射、或無電電鍍)而被沈積。光阻劑可被移除以暴露導電柱434。導電柱434可包括任何適當的導電材料，例如，金屬(諸如銅)。導電柱434可被形成以具有其約略等於該層中之最厚晶粒的厚度之厚度。於一些實施例中，晶粒114-1及114-4可具有相同的厚度。於一些實施例中，晶粒114-1及114-4可具有不同的厚度，而導電柱可具有等於更大厚度之厚度(例如，如圖5中所示)。於一些實施例中，種晶層483可被形成在載體之頂部表面上，於沈積光阻劑材料及導電材料之前。種晶層483可為任何適當的導電材料，包括銅。種晶層483可被移除，在移除光阻劑層後，使用任何適當的製程(包括化學蝕刻，除了其他者之外)。於某些實施例中，種晶層可被省略。
導電柱434可由任何適當的導電材料(諸如金屬)所形成。於某些實施例中，導電柱434可包括銅。導電柱434可具有任何適當的尺寸且可涵蓋一或更多層以形成ML互連。例如，於一些實施例中，個別導電柱434可具有介於1：1與4：1之間(例如，介於1：1與3：1之間)的高寬比(高度：直徑)。於一些實施例中，個別導電柱434可具有介於10微米與300微米之間的直徑。於一些實施例中，個別導電柱434可具有介於50微米與400微米之間的直徑。於一些實施例中，銅柱可具有介於10與300微米之間的高度。導電柱可具有任何適當的橫斷面形狀，例如，方形、三角形、及橢圓形，除了其他者之外。於一些實施例中，導電柱可被耦合至晶粒114之頂部表面，以供熱導通目的。
圖4B繪示總成400B，在將晶粒114-1、114-4置於總成400A之去填充區455中以後(圖4A)。晶粒114可被置於載體402上，使用任何適當的技術，諸如晶粒裝附膜(DAF)。晶粒114可包括無電材料層(未顯示)或載體(未顯示)於晶粒114之頂部上，其係提供增進的機械穩定性。無電材料層(其為晶粒114之不活動部分)可包括矽、陶瓷、或石英，除了其他材料之外。無電材料層可被裝附至晶粒114，使用任何適當的技術，包括(例如)釋放層。釋放層(文中亦稱為脫結層)可包括暫時黏著劑、或者當暴露至熱或光時釋放的其他材料，舉例而言。無電材料層可使用任何適當的技術來移除，包括(例如)研磨、蝕刻，諸如反應性離子蝕刻(RIE)或化學蝕刻；或者，假如脫結層包括光反應性或熱反應性材料的話，則施加光或熱。載體可包括用以提供機械穩定性的任何適當材料。載體可被裝附至晶粒114，使用任何適當的技術，包括(例如)可移除式黏著劑。
圖4C繪示一總成400C，在提供絕緣材料430於總成400B(圖4B)之晶粒114-1、114-4及導電柱434周圍以後。於一些實施例中，絕緣材料430可被初始地沈積在導電柱434及晶粒114-1、114-4之頂部上或上方，接著被拋光回以在晶粒114-1、114-4之頂部表面上以及導電柱434之頂部表面上暴露導電接點124。於一些實施例中，絕緣材料430為模製材料，諸如具有無機矽土粒子之有機聚合物。於一些實施例中，絕緣材料430為一種電介質材料。於一些實施例中，電介質材料可包括有機電介質材料、阻燃第4級材料(FR-4)、BT樹脂、聚醯亞胺材料、玻璃強化的環氧樹脂矩陣材料、或低k及超低k電介質(例如，碳摻雜的電介質、氟摻雜的電介質、多孔電介質、及有機聚合物電介質)。電介質材料可使用任何適當的製程來形成，包括疊片、狹縫塗佈及硬化。假如電介質層被形成以完全地覆蓋導電柱434及晶粒114-1、114-4，則電介質層可被移除以在晶粒114-1、114-4之頂部表面上及導電柱434之頂部表面上暴露導電接點124，使用任何適當的技術，包括研磨、或蝕刻，諸如濕式蝕刻、乾式蝕刻(例如，電漿蝕刻)、濕式爆破、或雷射消熔(例如，使用準分子雷射)。於一些實施例中，，絕緣層430之厚度可被最小化以減少所需的蝕刻時間。
圖4D繪示一總成400D，於形成導電柱435在晶粒114-1、114-4之頂部表面上及一或更多導電柱434之頂部表面上的導電接點124上以後。導電柱435可具有文中所揭露的任何實施例之形式，且可使用任何適當技術(例如，如以上參考圖4A所述者)來形成。導電柱435可被配置以形成一或更多去填充區456，其中並無導電柱435存在。
圖4E繪示總成400E，在將晶粒114-2置於總成400D(圖4D)之去填充區456中並將晶粒114-2耦合至晶粒114-1及114-4以後，以使得晶粒114-2之底部表面上的導電接點122可被耦合至晶粒114-1及114-4之頂部表面上的導電接點124(經由DTD互連130-1)。任何適當的技術均可被使用以形成總成400E之DTD互連130，諸如金屬至金屬裝附技術、焊接技術、或各向異性導電材料技術，揭露於文中。晶粒114-2可被置於載體402上，使用任何適當的技術，諸如參考圖4B而描述於上者。於一些實施例中，下填材料可被塗敷在晶粒114-2與晶粒114-1、114-4之間、及/或可被塗敷至DTD互連130。於一些實施例中，晶粒可包括預裝附的NCF。
圖4F繪示一總成400F，在提供絕緣材料431於總成400E(圖4E)之晶粒114-2及導電柱435周圍以後。絕緣材料431可被形成如以上參考圖4C所述。
圖4G繪示一總成400G，於藉由重複圖4D-4F中所述之製程以在總成400F上形成另一層以後。如圖4G中所示，總成400G可藉由以下方式來形成：在晶粒114-2之頂部表面上及在一或更多導電柱435之頂部表面上的導電接點124上形成導電柱436；經由DTD互連以將晶粒114-3、114-5放置並耦合至晶粒114-2；及在晶粒114-3、114-5和導電柱436周圍提供絕緣材料432。晶粒114-3可藉由ML互連152而被耦合至晶粒114-1，且晶粒114-5可藉由ML互連152而被耦合至晶粒114-4。
圖4H繪示一總成400H，於藉由重複圖4E-4F中所述之製程以在總成400G上形成另一層以後。如圖4H中所示，總成400H可藉由以下方式來形成：放置晶粒114-7、114-8、114-9；及在該等晶粒周圍提供絕緣材料433。晶粒114-7可藉由DTD互連130-1、130-2而被耦合至晶粒114-3。晶粒114-8可藉由ML互連152而被耦合至晶粒114-2。晶粒114-9可藉由DTD互連130-1、130-2而被耦合至晶粒114-5，且可藉由ML互連152而被耦合至晶粒114-4。複合晶粒之額外層可藉由重複如關於圖4D-4F所描述的製程來建立。
圖4I繪示一總成400I，在移除載體402並單片化複合晶粒以後。進一步操作可被適當地履行，無論是在單片化之前或之後(例如，沈積模製材料、裝附散熱器、沈積焊料抗蝕劑層、裝附用以耦合至封裝基材或至電路板之焊球，等等)。雖然總成400I具有在晶粒114-1及114-4之底部表面上的導電接點122，用以電氣耦合至封裝基材或電路板，於一些實施例中，晶粒114-7、114-8、及/或114-9可包括在頂部表面上之導電接點以致其總成可被反轉或「翻轉」並經由晶粒114-7、114-8、及/或144-9之頂部表面上的互連而耦合至封裝基材或電路板。
於文中所揭露的微電子總成100之一些實施例中，多層晶粒總成104可包括再分佈層(RDL)148，亦於文中稱為封裝基材部分。例如，圖5繪示一種微電子總成100之實施例，其中多層晶粒總成104具有四個層104-1、104-2、104-3、104-4；及一介於第二層104-2與第三層104-3之間的RDL。第一層104-1可包括晶粒114-1及114-4，而第二層104-2可包括晶粒114-2，如以上參考圖3所討論。第三層104-3可包括晶粒114-3及114-10，其可包括在晶粒114-3、114-10之底部表面上的導電接點122及在晶粒114-3、114-10之頂部表面上的導電接點124。如針對晶粒114-3所示，晶粒114-3之底部表面上的導電接點122可藉由晶粒至RDL(DTRDL)互連155-1、155-2而被電氣地及機械地耦合至RDL 148之頂部表面上的導電接點174。如針對晶粒114-10所示，晶粒114-10之底部表面上的導電接點122可藉由DTRDL互連155-2、155-3而被電氣地及機械地耦合至RDL 148之頂部表面上的導電接點174。任何適當的技術均可被使用以形成文中所揭露之DTRDL互連155，諸如電鍍技術、焊接技術、或各向異性導電材料技術。第四層104-4可包括晶粒114-11、晶粒114-12及晶粒114-13，而晶粒114-11、114-12、114-13可包括晶粒114-11、114-12、114-13之底部表面上的導電接點122。如針對晶粒114-11所示，晶粒114-11之底部表面上的導電接點122可藉由DTD互連130-1及130-2而被電氣地及機械地耦合至晶粒114-3之頂部表面上的導電接點124。如針對晶粒114-12所示，晶粒114-12之底部表面上的導電接點122可藉由ML互連152而被電氣地及機械地耦合至RDL 148之頂部表面上的導電接點174。如針對晶粒114-13所示，晶粒114-13之底部表面上的導電接點122可藉由DTD互連130-1及130-2而被電氣地及機械地耦合至晶粒114-10之頂部表面上的導電接點124，並可藉由ML互連152而被電氣地及機械地耦合至RDL 148之頂部表面上的導電接點174。
雖然圖5顯示具有單一RDL之多層晶粒總成104，但任何數目的RDL可被包括在複合晶粒中且可被置於任何晶粒層之間。於一些實施例中，微電子總成可包括一RDL在一具有導電柱之層之上，以提供額外的選路能力。RDL 148可使用任何適當的技術來形成，諸如以上參考圖1A之封裝基材102的形成所討論的任何技術。於一些實施例中，形成RDL 148可包括以金屬或其他導電材料電鍍晶粒114-1之導電接點122而成為形成RDL 148之鄰近導電接點174的部分；於是，介於晶粒114-3、114-10與RDL 148之間的DTPS互連150-4可為經電鍍的互連。晶粒114-3及114-10可接著依據文中所揭露的任何技術而被裝附至RDL 148之頂部表面，包括其為焊料互連之DTPS互連150、及其為非焊料互連之DTPS互連150(例如，經電鍍互連)。
於文中所揭露的微電子總成100之一些實施例中，多層晶粒總成104中所包括的晶粒114可具有不同的厚度。例如，如圖5中所示，晶粒114-10可具有其小於晶粒114-3之厚度167的厚度165，而晶粒114-11、114-12、114-13可具有其大於晶粒114-3之厚度167的厚度169。雖然圖5繪示晶粒114-11、114-12、114-13為具有相同的厚度，但晶粒114可具有任何適當的厚度且可具有變化的厚度。於一些實施例中，頂部層中之晶粒的厚度可大於除了頂部層之外的層中之晶粒的厚度以防止單片化期間之斷裂，因為較大的晶粒厚度可提供增加的機械強度及支持。於一些實施例中，晶粒114可為了熱及/或電之目的而被形成為更厚或更薄。
圖6A-6F為用以製造圖5之微電子總成100的範例製程中之各個階段的側面、橫斷面視圖，依據各個實施例。 圖6A繪示一種包括載體602之總成600A，在形成導電柱634於載體602之頂部表面上以後。載體402可包括用以在製造操作期間提供機械穩定性的任何適當材料，如以上參考圖4所述者。導電柱634可被配置以形成一或更多去填充區655，其中並無導電柱634存在。導電柱634可具有文中所揭露的任何實施例之形式，且可使用任何適當技術(例如，如以上參考圖4所述者)來形成。
圖6B繪示一總成600B，在將晶粒114-1、114-4置於總成600A(圖6A)之去填充區655中；並提供絕緣材料630於總成600A(圖6A)之晶粒114-1、114-4及導電柱634周圍以後。晶粒114可使用任何適當的技術而被置於載體602上，且絕緣材料可使用任何適當的技術而被提供，諸如參考圖4而描述於上者。
圖6C繪示一總成600C，在形成第二晶粒層於總成600B上以後。第二晶粒層可藉由以下方式來形成：在晶粒114-1、114-4之頂部表面上及在一或更多導電柱634之頂部表面上的導電接點124上形成導電柱635；放置晶粒114-2；及在晶粒114-2和導電柱635周圍提供絕緣材料631。導電柱635可具有文中所揭露的任何實施例之形式，且可使用任何適當技術(例如，如以上參考圖4所述者)來形成。晶粒114-2可藉由DTD互連130-2而被耦合至晶粒114-1、114-4以及至導電柱634，如以上參考圖4所述者。
圖6D繪示一總成600D，在形成RDL 648於總成600C上以後。RDL 148可使用任何適當的技術來製造，諸如PCB技術或再分佈層技術。RDL 648可包括RDL 648之底部表面上的導電接點672及頂部表面上的導電接點674。
圖6E繪示一總成600E，在形成第三晶粒層於總成600D上以後。第三晶粒層可藉由以下方式來形成：在RDL 648之頂部表面上的導電接點674上形成導電柱636；放置並耦合晶粒114-3和114-10；及在晶粒114-3、114-10和導電柱636周圍提供絕緣材料632。導電柱635可具有文中所揭露的任何實施例之形式，且可使用任何適當技術(例如，如以上參考圖4所述者)來形成。晶粒114-3及114-10可藉由DTRDL互連155-1、155-2、及155-3而被耦合至RDL 648之頂部表面的導電接點174，如以上參考圖5所述者。
圖6F繪示一總成600F，於藉由重複圖6C及/或圖4D-4F中所述之製程以在總成600E上形成第四晶粒層以後。如圖6F中所示，總成600F可藉由以下方式來形成：放置並耦合晶粒114-11、114-12、和114-13；及在晶粒114-11、114-12、114-13周圍提供絕緣材料。晶粒114-11可藉由DTD互連130-1、130-2而被耦合至晶粒114-3；晶粒114-12可藉由ML互連152而被耦合至RDL 648；及晶粒114-13可藉由DTD互連130-1、130-2而被耦合至晶粒114-10並藉由ML互連152而被耦合至RDL 648。額外的晶粒層及/或RDL可藉由重複如關於圖6A-6F所描述的製程來建立。雖然圖6顯示總成600為單一多層晶粒總成，但多數總成可被形成在載體602上、移除自載體602、並接著單片化。總成600F可被移除自載體602且進一步操作可盡可能適當地被履行(例如，裝附至封裝基材102，等等)。
於文中所揭露的微電子總成100之一些實施例中，多層晶粒總成104可包括嵌入在封裝基材部分149中之晶粒114。例如，圖7繪示一種微電子總成100之實施例，其中多層晶粒總成104具有六個晶粒層104-1、104-2、104-3、104-4、104-5、104-6；且兩個層(例如，第一層104-1及第四層104-4)可包括封裝基材部分149。封裝基材部分149可包括在封裝基材部分149之底部表面上的導電接點172及頂部表面上的導電接點174。任何適當的技術可被用以形成封裝基材部分149，包括(例如)無擾動增強層技術、載體為基的面板級無核封裝基材製造技術、或嵌入式面板級接合技術。於一些實施例中，形成封裝基材部分149可包括以金屬或其他導電材料電鍍晶粒114之頂部表面上的導電接點124而成為形成封裝基材部分149之頂部表面上的鄰近導電接點174之部分；於是，介於晶粒114與封裝基材部分149之間的DTPS互連150可為經電鍍的互連。
如圖7中所示，第一層104-1可包括嵌入封裝基材部分149-1中之晶粒114-14。晶粒114-14可藉由DTPS互連150-1、150-2而被耦合至封裝基材102。第二層104-2可包括晶粒114-15及114-16。晶粒114-15可藉由DTPS互連150-1而被耦合至封裝基材部分149-1，且藉由DTD互連130-2而被耦合至晶粒114-14。晶粒114-16可藉由DTPS互連150-1而被耦合至封裝基材部分149-1，且可藉由DTD互連130-2而被耦合至晶粒114-14。第三層104-3可包括晶粒114-17、114-18、及114-19。晶粒114-17可藉由DTD互連130-1、130-2而被耦合至晶粒114-15。晶粒114-18可藉由ML互連152而被耦合至晶粒114-14。晶粒114-19可藉由DTD互連130-1、130-2而被耦合至晶粒114-16，且藉由ML互連152而被耦合至封裝基材部分149-1。第四層104-4可包括嵌入封裝基材部分149-2中之晶粒114-20。晶粒114-20可藉由DTD互連130-2而被耦合至晶粒114-17及114-19。第五層104-5可包括晶粒114-21及114-22。晶粒114-21可藉由DTPS互連150-1而被耦合至封裝基材部分149-2，且可藉由DTD互連130-2而被耦合至晶粒114-20。晶粒114-22可藉由DTD互連130-2而被耦合至晶粒114-20，且可藉由DTPS互連150-1而被耦合至封裝基材部分149-2。第六層104-6可包括晶粒114-23、114-24、及114-25。晶粒114-23可藉由DTD互連130-1、130-2而被耦合至晶粒114-21。晶粒114-24可藉由ML互連152而被耦合至晶粒114-20。晶粒114-25可藉由DTD互連130-1、130-2而被耦合至晶粒114-22，且可藉由ML互連152而被耦合至封裝基材部分149-2。DTPS互連150、DTD互連130、及ML互連152可為文中所揭露的個別互連之任一者。
雖然圖7顯示特定數目和配置的晶粒、互連、及封裝基材部分，但任何數目和配置的晶粒、互連、及封裝基材部分可被使用，且可進一步包括一或更多RDL。
文中所揭露的微電子總成100可被用於任何適當的應用。例如，於一些實施例中，微電子總成100可被用以提供場可編程閘極陣列(FPGA)收發器及III-V族放大器之超高密度且高頻寬的互連。
更一般地，文中所揭露的微電子總成100可容許不同種類的功能性電路之「區塊」被分佈於晶粒114之不同者中，取代使所有電路包括於單一大型晶粒中，透過一些習知方式。在一些此類習知方式中，單一大型晶粒將包括所有這些不同的電路以達成介於電路之間的高頻寬、低損失通訊，且部分或所有這些電路可被選擇性地除能以調整大型晶粒的能力。然而，因為微電子總成100之ML互連152、及/或DTD互連130可容許晶粒114的不同者之間以及晶粒114與封裝基材102的不同者之間的高頻寬、低損失通訊，所以不同的電路可被分佈於不同的晶粒114之間，其藉由容許不同的晶粒114(例如，使用不同製造技術所形成的晶粒114)被輕易地交換以達成不同功能而減少了製造之總成本、增進了良率、並增加了設計彈性。
於另一範例中，其包括微電子總成100中之主動電路的晶粒114-2可被用以提供介於其他晶粒114之間的「主動」橋(例如，介於晶粒114-1與114-4之間、或介於晶粒114-1與114-3之間，於各個實施例中)。於另一範例中，微電子總成100中之晶粒114-1可為處理裝置(例如，中央處理單元、圖形處理單元、FPGA、數據機、應用程式處理器，等等)，且晶粒114-2可包括高頻寬記憶體、收發器電路、及/或輸入/輸出電路(例如，雙資料速率轉移電路、快速周邊組件互連電路，等等)。於一些實施例中，晶粒114-1可包括：一組導電接點124，用以與高頻寬記憶體晶粒114-2介接、一不同組導電接點124，用以與輸入/輸出電路晶粒114-2介接、等等。特定的高頻寬記憶體晶粒114-2、輸入/輸出電路晶粒114-2(等等)可被選擇以用於待處理應用程式。
於另一範例中，微電子總成100中之晶粒114-2可為快取記憶體(例如，第三級快取記憶體)、而一或更多晶粒114-1、114-4、114-3、及/或114-5可為處理裝置(例如，中央處理單元、圖形處理單元、FPGA、數據機、應用程式處理器，等等)，其係共用晶粒114-2之快取記憶體。
於另一範例中，晶粒114可為單一矽基材或可為複合晶粒，諸如記憶體堆疊。
文中所揭露的微電子總成100可被包括在任何適當的電子組件中。圖8-11繪示設備之各種範例，其可包括(或被包括在)文中所揭露的微電子總成100之任一者中。
圖8為其可包括在文中所揭露的微電子總成100之微電子總成100的任一者中之晶圓1500及晶粒1502(例如，如晶粒114之任何適當者)之頂部視圖。晶圓1500可由半導體材料所組成且可包括一或更多晶粒1502，其具有在晶圓1500之表面上所形成的IC結構。晶粒1502之各者可為包括任何適當IC之半導體產品的重複單元。在半導體產品之製造程序完成後，晶圓1500可經歷一種單片化製程，其中晶粒1502被彼此分離以提供半導體產品之離散「晶片」。晶粒1502可為文中所揭露的晶粒114之任一者。晶粒1502可包括一或更多電晶體(例如，圖9之一些電晶體1640，討論於下)、支援電路，用以發送電信號至電晶體、被動組件(例如，信號軌線、電阻、電容、或電感)、及/或任何其他IC組件。於一些實施例中，晶圓1500或晶粒1502可包括記憶體裝置(例如，隨機存取記憶體(RAM)裝置，諸如靜態RAM(SRAM)裝置、磁性RAM (MRAM)裝置、電阻RAM(RRAM)裝置、導電橋接RAM (CBRAM)裝置，等等)、邏輯裝置(例如，AND、OR、NAND、或NOR閘)、或任何其他適當的電路元件。這些裝置之多者可被結合在單一晶粒1502上。例如，由多數記憶體裝置所形成的記憶體陣列可被形成在相同晶粒1502上而成為處理裝置(例如，圖11之處理裝置1802)或其他邏輯，其被組態成儲存記憶體裝置中之資訊或執行記憶體陣列中所儲存的指令。文中所揭露的微電子總成100之各者可使用一種晶粒至晶圓總成技術來製造，其中一些晶粒114被裝附至晶圓1500，其包括晶粒114之其他者，且晶圓1500被接著單片化。
圖9為其可包括在文中所揭露的微電子總成100之微電子總成100的任一者中之IC裝置1600(例如，於晶粒114之任何者中)之橫斷面側視圖。IC裝置1600之一或更多者可被包括在一或更多晶粒1502中(圖8)。IC裝置1600可被形成在晶粒基材1602(例如，圖8之晶圓1500)上且可被包括在晶粒(例如，圖8之晶粒1502)中。晶粒基材1602可為由半導體材料系統所組成的半導體基材，該等半導體材料系統包括(例如)n型或p型材料系統(或兩者之組合)。晶粒基材1602可包括(例如)使用大塊矽或矽絕緣體(SOI)子結構所形成的結晶基材。於一些實施例中，晶粒基材1602可使用替代材料而被形成，該些材料可或可不與矽結合，其包括(但不限定於)鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、或銻化鎵。被分類為族II-VI、III-V、或IV之進一步材料亦可被使用以形成晶粒基材1602。雖然其可用來形成晶粒基材1602之材料的一些範例被描述於此，但其可作用為IC裝置1600之基礎的任何材料均可被使用。晶粒基材1602可為單片化晶粒(例如，圖8之晶粒1502)或晶圓(例如，圖8之晶圓1500)的部分。
IC裝置1600可包括配置在晶粒基材1602上之一或更多裝置層1604。裝置層1604可包括形成在晶粒基材1602上之一或更多電晶體1640(例如，金氧半導體場效電晶體(MOSFET))的特徵。裝置層1604可包括(例如)一或更多源極及/或汲極(S/D)區1620、用以控制介於S/D區1620間之電晶體1640中的電流之閘極1622、及用以將電信號發送至/自S/D區1620之一或更多S/D接點1624。電晶體1640可包括為了簡潔之目的而未描繪出之額外特徵，諸如裝置隔離區、閘極接點，等等。電晶體1640不限於圖9中所描繪的類型及組態且可包括多種其他類型及組態，諸如(例如)平面電晶體、非平面電晶體、或兩者之組合。非平面電晶體可包括FinFET電晶體(諸如雙閘極電晶體或三閘極電晶體)、及圍繞或包圍閘極電晶體(諸如奈米帶及奈米線電晶體)。
各電晶體1640可包括由至少兩層(閘極電介質及閘極電極)所形成的閘極1622。閘極電介質可包括一層或層之堆疊。一或更多層可包括氧化矽、二氧化矽、碳化矽、及/或高k電介質材料。高k電介質材料可包括元件，諸如鉿、矽、氧、鈦、鉭、鋁、鋯、鋇、鍶、釔、鉛、鈧、鈮、及鋅。可用於閘極電介質之高k材料的範例包括(但不限定於)氧化鉿、氧化鉿矽、氧化鑭、氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭、及鈮酸鉛鋅。於一些實施例中，退火製程可被執行在閘極電介質上以增進其品質，當使用高k材料時。
閘極電極可被形成在閘極電介質上且可包括至少一p型工作函數金屬或n型工作函數金屬，根據電晶體1640將為p型金氧半導體(PMOS)或n型金氧半導體(NMOS)電晶體。在一些實施方式中，閘極電極層可包括二或更多金屬層之堆疊，其中一或更多金屬層為工作函數金屬層且至少一金屬層為填充金屬層。進一步金屬層可被包括以供其他目的，諸如障壁層。針對PMOS電晶體，其可被用於閘極電極之金屬包括(但不限定於)釕、鈀、鉑、鈷、鎳、導電金屬氧化物(例如，氧化釕)、以及參考NMOS電晶體而討論於下之任何金屬(例如，用於工作函數調諧)。針對NMOS電晶體，可用於閘極電極之金屬包括(但不限定於)鉿、鋯、鈦、鉭、鋁、這些金屬之合金、這些金屬之碳化物(例如，碳化鉿、碳化鋯、碳化鈦、碳化鉭、及碳化鋁)、以及參考PMOS電晶體而討論於上之任何金屬(例如，用於工作函數調諧)。
於一些實施例中，當觀察為沿著源極-通道-汲極方向之電晶體1640的橫斷面時，閘極電極可包括U狀結構，其包括實質上平行於晶粒基材1602之表面的底部部分及實質上垂直於晶粒基材1602之頂部表面的兩側壁部分。於其他實施例中，形成閘極電極之金屬層的至少一者可僅為平面層，其係實質上平行於晶粒基材1602之頂部表面而不包括實質上垂直於晶粒基材1602之頂部表面的側壁部分。於其他實施例中，閘極電極可包括U狀結構及平面、非U狀結構之組合。例如，閘極電極可包括一或更多U狀金屬層，其係形成於一或更多平面、非U狀層之頂部上。
於一些實施例中，一對側壁間隔物可被形成於用以包圍閘極堆疊之閘極堆疊的相對側上。側壁間隔物可被形成自材料，諸如氮化矽、氧化矽、碳化矽、摻雜碳之氮化矽、及氧氮化矽。用以形成側壁間隔物之程序為本技術中眾所周知的，且通常包括沈積及蝕刻製程步驟。於一些實施例中，複數間隔物對可被使用；例如，兩對、三對、或四對側壁間隔物可被形成於閘極堆疊之相對側上。
S/D區1620可被形成在相鄰於各電晶體1640之閘極1622的晶粒基材1602內。S/D區1620可使用植入/擴散製程或蝕刻/沈積製程來形成，舉例而言。於前者之製程中，諸如硼、鋁、銻、磷或砷等摻雜物可被離子植入晶粒基材1602內以形成S/D區1620。一種活化摻雜物並致使其進一步擴散入晶粒基材1602之退火製程可接續於離子植入製程之後。於後者之製程中，晶粒基材1602可首先被蝕刻以形成凹陷於S/D區1620之位置上。外延沈積製程可接著被執行而利用其用來製造S/D區1620之材料以填充該等凹陷。在一些實施方式中，S/D區1620可使用諸如矽鍺或碳化矽等矽合金來製造。於一些實施例中，外延地沈積的矽合金可被原處摻雜以諸如硼、砷、或磷等摻雜物。於一些實施例中，S/D區1620可使用一或更多替代的半導體材料(諸如鍺或III-V族材料或合金)來形成。於進一步實施例中，一或更多層金屬及/或金屬合金可被用以形成S/D區1620。
電信號，諸如電力及/或輸入/輸出(I/O)信號，可透過一或更多配置於裝置層1604上之互連層(於圖9中繪示為互連層1606-1610)而被發送至及/或自裝置層1604之裝置(例如，電晶體1640)。 例如，裝置層1604之導電特徵(例如，閘極1622及S/D接點1624)可被電耦合與互連層1606-1610之互連結構1628。一或更多互連層1606-1610可形成IC裝置1600之金屬化堆疊(亦稱為「ILD堆疊」)1619。
互連結構1628可被配置於互連層1606-1610內以依據多種設計來發送電信號；特別地，該配置不限於圖9中所描繪之互連結構1628的特定組態。雖然特定數目的互連層1606-1610被描繪於圖9中，但本發明之實施例包括具有比所描繪者更多或更少互連層之IC裝置。
於一些實施例中，互連結構1628可包括線1628a及/或通孔1628b，其係填充以導電材料(諸如金屬)。線1628a可被配置以於一平面之方向發送電信號，該平面係實質上與晶粒基材1602(於其上形成裝置層1604)之表面平行。例如，線1628a可於入及出頁面(從圖9之觀點)之方向發送電信號。通孔1628b可被配置以於一平面之方向發送電信號，該平面係實質上與晶粒基材1602(於其上形成裝置層1604)之表面垂直。於一些實施例中，通孔1628b可將不同互連層1606-1610之線1628a電耦合在一起。
互連層1606-1610可包括配置於互連結構1628之間的電介質材料1626，如圖9中所示。於一些實施例中，配置於不同互連層1606-1610的互連結構1628之間的電介質材料1626可具有不同的組成；於其他實施例中，介於不同互連層1606-1610之間的電介質材料1626之組成可為相同的。
第一互連層1606(稱為金屬1或「M1」)可被形成直接於裝置層1604上。於一些實施例中，第一互連層1606可包括線1628a及/或通孔1628b，如圖所示。第一互連層1606之線1628a可與裝置層1604之接點(例如，S/D接點1624)耦合。
第二互連層1608(稱為金屬2或「M2」)可被形成直接於第一互連層1606上。於一些實施例中，第二互連層1608可包括通孔1628b，用以將第二互連層1608之線1628a與第一互連層1606之線1628a耦合。雖然線1628a及通孔1628b係以各互連層內(例如，第二互連層1608內)之線來結構上描繪(為了簡潔的緣故)，但線1628a及通孔1628b可為結構上及/或材料上相連的(例如，於雙金屬鑲嵌製程期間同時地填充)，於一些實施例中。
第三互連層1610(稱為金屬3或「M3」)(及額外互連層，如所欲)可被依序形成在第二互連層1608上，依據相關於第二互連層1608或第一互連層1606所述的類似技術及組態。於一些實施例中，其為IC裝置1600中之金屬化堆疊1619中的「高層」(亦即，遠離自裝置層1604)之互連層可為較厚的。
IC裝置1600可包括焊料抗蝕劑材料1634(例如，聚醯亞胺或類似材料)以及形成在互連層1606-1610上之一或更多導電接點1636。於圖9中，導電接點1636被繪示為具有接合墊之形式。導電接點1636可被電耦合與互連結構1628並組態成將電晶體1640之電信號發送至其他外部裝置。例如，焊料接合可被形成於一或更多導電接點1636上以將包括IC裝置1600之晶片機械地及/或電地耦合與另一組件(例如，電路板)。IC裝置1600可包括額外或替代結構，用以發送來自互連層1606-1610之電信號；例如，導電接點1636可包括其他類似特徵(例如，柱)，其係發送電信號至外部組件。導電接點1636可作用為導電接點122或124，適當地。
於一些實施例中，其中IC裝置1600為雙側晶粒(例如，如同晶粒114-1)，IC裝置1600可包括在裝置層1604之相反側上的另一金屬化堆疊(未顯示)。此金屬化堆疊可包括如參考互連層1606-1610之以上所討論的多數互連層，用以提供介於裝置層1604與額外導電接點(未顯示)之間的導電路徑(例如，包括導電線及通孔)，該等額外導電接點係位於與導電接點1636相反的IC裝置1600之側上。這些額外導電接點可作用為導電接點122或124，適當地。
於其他實施例中，其中IC裝置1600為雙側晶粒(例如，如同晶粒114-1)，IC裝置1600可包括通過晶粒基材1602之一或更多TSV；這些TSV可與裝置層1604接觸，且可提供介於裝置層1604與額外導電接點(未顯示)之間的導電路徑，該等額外導電接點係位於與導電接點1636相反的IC裝置1600之側上。這些額外導電接點可作用為導電接點122或124，適當地。
圖10為其可包括在文中所揭露的微電子總成100之任一者中的IC裝置總成1700之橫斷面側視圖。於某些實施例中，IC裝置總成1700可為微電子總成100。IC裝置總成1700包括配置在電路板1702(其可為，例如，主機板)上之數個組件。IC裝置總成1700包括配置在電路板1702之第一面1740以及電路板1702之相對第二面1742上的組件；通常，組件被配置在一或兩面1740和1742上。以下參考IC裝置總成1700所討論的任何IC封裝可具有文中所揭露的微電子總成100之任何適當實施例的形式。
於一些實施例中，電路板1702可為一種PCB，其包括藉由電介質材料之層而彼此分離且藉由導電通孔而互連的多數金屬層。金屬層之任何一或更多者可被形成以所欲的電路型態來發送電信號(選擇性地配合其他金屬層)於其耦合至電路板1702的組件之間。於其他實施例中，電路板1702可為非PCB基材。於一些實施例中，電路板1702可為(例如)電路板。
圖10中所繪示的IC裝置總成1700包括中介層上封裝(package-on-interposer)結構1736，其係藉由耦合組件1716而被耦合至電路板1702之第一面1740。耦合組件1716可電氣地且機械地耦合中介層上封裝結構1736至電路板1702，且可包括焊球(如圖10中所示)、插座之公和母部分、黏著劑、下填材料、及/或任何其他適當的電氣及/或機械耦合結構。
中介層上封裝結構1736可包括IC封裝1720，其係藉由耦合組件1718而被耦合至中介層1704。耦合組件1718可具有針對應用之任何適當的形式，諸如以上參考耦合組件1716所討論的形式。雖然圖10係顯示單一IC封裝1720，但多數IC封裝可被耦合至中介層1704；確實，額外中介層可被耦合至中介層1704。中介層1704可提供用以橋接電路板1702與IC封裝1720之中間基材。IC封裝1720可為或包括(例如)晶粒(圖8之晶粒1502)、IC裝置(例如，圖9之IC裝置1600)、或任何其他適當的組件。通常，中介層1704可將連接延伸至較寬的節距或者將連接重新路由至不同連接。例如，中介層1704可將IC封裝1720(例如，晶粒)耦合至耦合組件1716之一組球柵陣列(BGA)導電接點，以供耦合至電路板1702。於圖10所繪示的實施例中，IC封裝1720及電路板1702被裝附至中介層1704之相反側；於其他實施例中，IC封裝1720及電路板1702可被裝附至中介層1704之相同側。於一些實施例中，三或更多組件係經由中介層1704而被互連。
於一些實施例中，中介層1704可被形成為一種PCB，其包括藉由電介質材料之層而彼此分離且藉由導電通孔而互連的多數金屬層。於一些實施例中，中介層1704可由以下所形成：環氧樹脂、玻璃纖維強化環氧樹脂、具有無機填料之環氧樹脂、陶瓷材料、或聚合物材料(諸如聚醯亞胺)。於一些實施例中，中介層1704可被形成以替代的堅硬或彈性材料，其可包括用於半導體基材中之上述的相同材料，諸如矽、鍺、及其他III-V族及IV族材料。中介層1704可包括金屬互連1708及通孔1710，包括(但不限定於)TSV 1706。中介層1704可進一步包括嵌入式裝置1714，包括被動和主動裝置兩者。此等裝置可包括(但不限定於)電容、解耦電容、電阻、電感、熔絲、二極體、變壓器、感應器、靜電放電(ESD)裝置、及記憶體裝置。諸如射頻裝置、功率放大器、功率管理裝置、天線、陣列、感應器、及微電機系統(MEMS)裝置等更複雜的裝置亦可被形成於中介層1704上。中介層上封裝結構1736可具有本技術中所已知的任何中介層上封裝的形式。
IC裝置總成1700包括IC封裝1724，其係藉由耦合組件1722而被耦合至電路板1702之第一面1740。耦合組件1722可具有以上參考耦合組件1716所討論之任何實施例的形式，而IC封裝1724可具有以上參考IC封裝1720所討論之任何實施例的形式。
圖10中所繪示的IC裝置總成1700包括堆疊式封裝(package-on-package)結構1734，其係藉由耦合組件1728而被耦合至電路板1702之第二面1742。堆疊式封裝結構1734可包括藉由耦合組件1730而被耦合在一起的IC封裝1726及IC封裝1732，以致其IC封裝1726被配置在電路板1702與IC封裝1732之間。耦合組件1728和1730可具有以上所討論之耦合組件1716的任何實施例之形式，而IC封裝1726和1732可具有以上所討論之IC封裝1720的任何實施例之形式。堆疊式封裝結構1734可依據本技術中所已知的任何堆疊式封裝結構而被組態。
圖11為其可包括在文中所揭露的微電子總成100之一或更多者的範例電氣裝置1800之方塊圖。例如，電氣裝置1800之組件的任何適當者可包括文中所揭露的IC裝置總成1700、IC裝置1600、或晶粒1502之一或更多者，且可配置在文中所揭露的微電子總成100之任一者中。數個組件被繪示在圖11中為包括在電氣裝置1800中，但這些組件之任何一或更多者可被省略或複製，如針對應用所適當的。於一些實施例中，電氣裝置1800中所包括之組件的部分或全部可被裝附至一或更多主機板。於一些實施例中，這些組件之部分或全部被製造至單一系統單晶片(SoC)晶粒上。
此外，於各個實施例中，電氣裝置1800可不包括圖11中所繪示之組件的一或更多者，但電氣裝置1800可包括用以耦合至一或更多組件的介面電路。例如，電氣裝置1800可不包括顯示裝置1806，但可包括顯示裝置介面電路(例如，連接器及驅動程式電路)，顯示裝置1806可被耦合至該顯示裝置介面電路。於另一組範例中，電氣裝置1800可不包括音頻輸入裝置1824及音頻輸出裝置1808，但可包括音頻輸入或輸出裝置介面電路(例如，連接器及支援電路)，音頻輸入裝置1824或音頻輸出裝置1808可被耦合至該輸出裝置介面電路。
電氣裝置1800可包括處理裝置1802(例如，一或更多處理裝置1802)。如文中所使用，術語「處理裝置」或「處理器」可指稱任何裝置或裝置之部分，其處理來自暫存器及/或記憶體之電子資料以將該電子資料轉變為其可被儲存於暫存器及/或記憶體中之其他電子資料。處理裝置1802可包括一或更多數位信號處理器(DSP)、特定應用IC(ASIC)、中央處理單元(CPU)、圖形處理單元(GPU)、密碼處理器(執行硬體內之密碼演算法的特殊化處理器)、伺服器處理器、或任何其他適當的處理裝置。電氣裝置1800可包括記憶體1804，其本身可包括一或更多記憶體裝置，諸如揮發性記憶體(例如，動態隨機存取記憶體(DRAM))、非揮發性記憶體(例如，唯讀記憶體(ROM))、快閃記憶體、固態記憶體、及/或硬碟。於一些實施例中，記憶體1804可包括其與處理裝置1802共用晶粒之記憶體。此記憶體可被使用為快取記憶體且可包括嵌入式動態隨機存取記憶體(eDRAM)或自旋轉移力矩磁性隨機存取記憶體(STT-MRAM)。
於一些實施例中，電氣裝置1800可包括通訊晶片1812(例如，一或更多通訊晶片)。例如，通訊晶片1812可組態成管理無線通訊，以供資料之轉移至及自電氣裝置1800。術語「無線」及其衍生詞可被用以描述電路、裝置、系統、方法、技術、通訊頻道，等等，其可藉由使用透過非固體媒體之經調變的電磁輻射來傳遞資料。該術語並未暗示其相關裝置不含有任何佈線，雖然於某些實施例中其可能不含有。
通訊晶片1812可實施任何數目的無線標準或協定，包括(但不限定於)電機電子工程師學會(IEEE)標準，其包括Wi-Fi(IEEE 802.11家族)、IEEE 802.16標準(例如，IEEE 802.16-2005修正)、長期演進(LTE)計畫連同任何修正、更新、及/或修訂(例如，先進LTE計畫、超行動寬頻(UMB)計畫(亦稱為「3GPP2」)等等)。IEEE 802.16相容的寬頻無線存取(BWA)網路通常被稱為WiMAX網路，其為代表全球互通微波存取之縮寫，其為通過IEEE 802.16標準之符合性及可交互操作性測試的產品之驗證標記。通訊晶片1812可依據全球行動通訊系統(GSM)、通用封包無線電服務(GPRS)、環球行動電訊系統(UMLS)、高速封包存取(HSPA)、演進的HSPA(E-HSPA)、或LTE網路而操作。通訊晶片1812可依據GSM演進之增強資料(EDGE)、GSM EDGE無線電存取網路(GERAN)、環球陸地無線電存取網路(UTRAN)、或演進的UTRAN(E-UTRAN)而操作。通訊晶片1812可依據分碼多重存取(CDMA)、分時多重存取(TDMA)、數位增強的無線電訊(DECT)、演進資料最佳化(EV-DO)、及其衍生者、以及其被設計為3G、4G、5G及以上之任何其他無線協定而操作。通訊晶片1812可依據其他實施例中之其他無線協定而操作。電氣裝置1800可包括天線1822，用以促進無線通訊及/或用以接收其他無線通訊(諸如AM或FM無線電傳輸)。
於一些實施例中，通訊晶片1812可管理有線通訊，諸如電氣、光學、或任何其他適當的通訊協定(例如，乙太網路)。如上所述，通訊晶片1812可包括多數通訊晶片。例如，第一通訊晶片1812可專用於較短距離無線通訊，諸如Wi-Fi或藍牙；而第二通訊晶片1812可專用於較長距離無線通訊，諸如全球定位系統(GPS)、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO或其他。於一些實施例中，第一通訊晶片1812可專用於無線通訊，而第二通訊晶片1812可專用於有線通訊。
電氣裝置1800可包括電池/電源電路1814。電池/電源電路1814可包括一或更多能量儲存裝置(例如，電池或電容)及/或電路，用以將電氣裝置1800之組件耦合至一與電氣裝置1800分離的能量來源(例如，AC線電源)。
電氣裝置1800可包括顯示裝置1806(或相應的介面電路，如以上所討論)。顯示裝置1806可包括任何視覺指示器，諸如抬頭顯示、電腦監視器、投影器、觸控式螢幕顯示、液晶顯示(LCD)、發光二極體顯示、或平板顯示。
電氣裝置1800可包括音頻輸出裝置1808(或相應的介面電路，如以上所討論)。音頻輸出裝置1808可包括任何產生聽得到的指示器之裝置，諸如揚聲器、頭戴式耳機、或耳塞式耳機。
電氣裝置1800可包括音頻輸入裝置1824(或相應的介面電路，如以上所討論)。音頻輸入裝置1824可包括任何產生代表聲音之信號的裝置，諸如麥克風、麥克風陣列、或數位儀器(例如，具有音樂儀器數位介面(MIDI)輸出之儀器)。
電氣裝置1800可包括GPS裝置1818(或相應的介面電路，如以上所討論)。GPS裝置1818可與衛星為基的系統通訊且可接收電氣裝置1800之位置，如本技術中所已知。
電氣裝置1800可包括其他輸出裝置1810(或相應的介面電路，如以上所討論)。其他輸出裝置1810之範例可包括音頻編碼解碼器、視頻編碼解碼器、印表機、有線或無線傳輸器，用以提供資訊至其他裝置、或額外儲存裝置。
電氣裝置1800可包括其他輸入裝置1820(或相應的介面電路，如以上所討論)。其他輸入裝置1820之範例可包括加速計、迴轉儀、羅盤、影像擷取裝置、鍵盤、游標控制裝置，諸如滑鼠、尖筆、觸控板、條碼讀取器、快速回應(QR)碼讀取器、任何感測器、或射頻識別(RFID)讀取器。
電氣裝置1800可具有任何所欲的形狀因數，諸如計算裝置或者手持式、可攜式或行動電氣裝置(例如，行動電話、智慧型手機、行動網際網路裝置、音樂播放器、平板電腦、膝上型電腦、小筆電、輕薄型筆電、個人數位助理(PDA)、超行動個人電腦，等等)、桌上型電氣裝置、伺服器、或其他網路連接計算組件、印表機、掃描器、監視器、機上盒、娛樂控制單元、汽車控制單元、數位相機、數位攝影機、或穿戴式電氣裝置。於一些實施例中，電氣裝置1800可為處理資料之任何其他電子裝置。
以下段落提供文中所揭露的實施例之各種範例。
範例1為一種微電子總成，包括：一封裝基材，其具有一第一表面及一相對的第二表面；一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中且其中該第一晶粒之該第一表面係藉由第一互連而被耦合至該封裝基材之該第二表面；一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中且其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。
範例2可包括範例1之請求標的，且可進一步指明其該第二晶粒之該第一表面係藉由第四互連而被耦合至該封裝基材之該第二表面。
範例3可包括範例2之請求標的，且可進一步指明其該等第四互連包括一導電柱。
範例4可包括範例3之請求標的，且可進一步指明其一個別導電柱具有介於50微米與400微米之間的直徑。
範例5可包括範例1之請求標的，且可進一步指明其該第三晶粒之該第一表面係藉由第五互連而被耦合至該封裝基材之該第二表面。
範例6可包括範例5之請求標的，且可進一步指明其該等第五互連包括一導電柱。
範例7可包括範例6之請求標的，且可進一步指明其一個別導電柱具有介於50微米與400微米之間的直徑。
範例8可包括範例1之請求標的，且可進一步指明其該第三晶粒之該第一表面係藉由第六互連而被耦合至該第一晶粒之該第二表面。
範例9可包括範例8之請求標的，且可進一步指明其該等第六互連包括一導電柱。
範例10可包括範例9之請求標的，且可進一步指明其一個別導電柱具有介於10微米與300微米之間的直徑。
範例11可包括範例1之請求標的，且可進一步包括：一第四晶粒，其具有一第一表面及一相對的第二表面，其中該第四晶粒被嵌入該第一電介質層中，其中該第四晶粒之該第一表面係藉由第七互連而被耦合至該封裝基材之該第二表面，且其中該第四晶粒之該第二表面係藉由第八互連而被耦合至該第二晶粒之該第一表面。
範例12可包括範例11之請求標的，且可進一步指明其該等第二互連之一節距係不同於該等第八互連之一節距。
範例13可包括範例1之請求標的，且可進一步包括：一第五晶粒，其具有一第一表面及一相對的第二表面，其中該第五晶粒被嵌入該第三電介質層中，且其中該第五晶粒之該第一表面係藉由第九互連而被耦合至該第二晶粒之該第二表面。
範例14可包括範例13之請求標的，且可進一步指明其該等第三互連之一節距係不同於該等第九互連之一節距。
範例15可包括範例13之請求標的，且可進一步指明其該第三晶粒之一厚度係不同於該第五晶粒之一厚度。
範例16可包括範例1之請求標的，且可進一步包括：一第六晶粒，其具有一第一表面及一相對的第二表面，其中該第六晶粒被嵌入該第四電介質層中，其中該第六晶粒之該第一表面係藉由第十互連而被耦合至該第三晶粒之該第二表面。
範例17可包括範例1之請求標的，且可進一步包括：一再分佈層，介於該第一電介質層與該第二電介質層之間、或介於該第二電介質層與該第三電介質層之間。
範例18可包括範例1之請求標的，且可進一步指明其該等第一互連之一節距係不同於該等第二互連之一節距。
範例19可包括範例1之請求標的，且可進一步指明其該等第二互連之一節距係不同於該等第三互連之一節距。
範例20可包括範例1之請求標的，且可進一步指明其該等第一互連具有介於200微米與800微米之間的節距。
範例21可包括範例1之請求標的，且可進一步指明其該等第二互連具有介於5微米與100微米之間的節距。
範例22可包括範例1之請求標的，且可進一步指明其該等第三互連具有介於5微米與100微米之間的節距。
範例23可包括範例1之請求標的，且可進一步指明其該第二晶粒重疊該第一晶粒以一介於範例0.5毫米與5毫米之間的距離。
範例24可包括範例1之請求標的，且可進一步指明其該第三晶粒重疊該第二晶粒以一介於範例0.5毫米與5毫米之間的距離。
範例25可包括範例1之請求標的，且可進一步指明其該等第一互連、該等第二互連、或該等第三互連包括焊料。
範例26可包括範例1之請求標的，且可進一步指明其該等第一互連、該等第二互連、或該等第三互連包括各向異性導電材料。
範例27可包括範例1之請求標的，且可進一步指明其該等第一互連、該等第二互連、或該等第三互連包括經電鍍的互連。
範例28可包括範例1之請求標的，且可進一步指明其該等第一互連、該等第二互連、或該等第三互連包括下填材料。
範例29可包括範例1之請求標的，且可進一步指明其該第一晶粒為一雙側晶粒。
範例30可包括範例1之請求標的，且可進一步指明其該第二晶粒為一雙側晶粒。
範例31可包括範例1之請求標的，且可進一步指明其該第三晶粒為一雙側晶粒。
範例32可包括範例1之請求標的，且可進一步指明其該第三晶粒為一單側晶粒。
範例33可包括範例1之請求標的，且可進一步指明其該第一晶粒或該第三晶粒為一中央處理單元。
範例34可包括範例1之請求標的，且可進一步指明其該第二晶粒包括一記憶體裝置。
範例35可包括範例1之請求標的，且可進一步指明其該第二晶粒為一高頻寬記憶體裝置。
範例36可包括範例1之請求標的，且可進一步指明其該封裝基材為一印刷電路板。
範例37可包括範例1之請求標的，且可進一步指明其該微電子總成被包括在一伺服器裝置中。
範例38可包括範例1之請求標的，且可進一步指明其該微電子總成被包括在一可攜式計算裝置中。
範例39可包括範例1之請求標的，且可進一步指明其該微電子總成被包括在一穿戴式計算裝置中。
範例40為一種計算裝置，包括：一微電子總成，其包括：一封裝基材，其具有一第一表面及一相對的第二表面；一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中且其中該第一晶粒之該第一表面係藉由第一互連而被耦合至該封裝基材之該第二表面；一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中且其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。
範例41可包括範例40之請求標的，且可進一步指明其該第二晶粒之該第一表面係藉由第四互連而被耦合至該封裝基材之該第二表面。
範例42可包括範例41之請求標的，且可進一步指明其該等第四互連包括一導電柱。
範例43可包括範例42之請求標的，且可進一步指明其一個別導電柱具有介於50微米與400微米之間的直徑。
範例44可包括範例40之請求標的，且可進一步指明其該第三晶粒之該第一表面係藉由第五互連而被耦合至該封裝基材之該第二表面。
範例45可包括範例44之請求標的，且可進一步指明其該等第五互連包括一導電柱。
範例46可包括範例45之請求標的，且可進一步指明其一個別導電柱具有介於50微米與400微米之間的直徑。
範例47可包括範例40之請求標的，且可進一步指明其該第三晶粒之該第一表面係藉由第六互連而被耦合至該第一晶粒之該第二表面。
範例48可包括範例47之請求標的，且可進一步指明其該等第六互連包括一導電柱。
範例49可包括範例48之請求標的，且可進一步指明其一個別導電柱具有介於10微米與300微米之間的直徑。
範例50可包括範例40之請求標的，且可進一步包括：一再分佈層，介於該第一電介質層與該第二電介質層之間、或介於該第二電介質層與該第三電介質層之間。
範例51可包括範例40之請求標的，且可進一步指明其該等第一互連之一節距係不同於該等第二互連之一節距。
範例52可包括範例40之請求標的，且可進一步指明其該等第二互連之一節距係不同於該等第三互連之一節距。
範例53可包括範例40之請求標的，且可進一步指明其該等第一互連具有介於200微米與800微米之間的節距。
範例54可包括範例40之請求標的，且可進一步指明其該等第二互連具有介於5微米與100微米之間的節距。
範例55可包括範例40之請求標的，且可進一步指明其該等第三互連具有介於5微米與100微米之間的節距。
範例56為一種微電子總成，包括：一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中；一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第一互連而被耦合至該第一晶粒之該第二表面；及一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中，且其中該第三晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面，其中該等第二互連包括一導電柱。
範例57可包括範例56之請求標的，且可進一步指明其一個別導電柱具有介於10微米與300微米之間的直徑。
範例58可包括範例56之請求標的，且可進一步指明其該等第一互連之一節距係不同於該等第二互連之一節距。
範例59可包括範例56之請求標的，且可進一步指明其該等第一互連具有介於5微米與100微米之間的節距。
範例60可包括範例56之請求標的，且可進一步指明其該等第二互連具有介於200微米與800微米之間的節距。
範例61可包括範例56之請求標的，且可進一步包括：一再分佈層，介於該第一電介質層與該第二電介質層之間、或介於該第二電介質層與該第三電介質層之間。
範例62可包括範例56之請求標的，且可進一步包括：一第四晶粒，其具有一表面，其中該第四晶粒被嵌入一第四電介質層中且其中該第四晶粒之該表面係藉由第三互連而被耦合至該第二晶粒之該第二表面或者至該第一晶粒之該第二表面，以及其中該等第三互連包括一導電柱。
範例63為一種製造一微電子總成之方法，包括：形成第一互連於一第一晶粒與一第二晶粒之間，其中該第一晶粒具有一具備第一導電接點之第一表面及一具備第二導電接點之相對的第二表面，其中該第二晶粒具有一具備第一導電接點之第一表面及一具備第二導電接點之相對的第二表面，且其中該等第一互連將該第一晶粒之該等第二導電接點耦合至該第二晶粒之該等第一導電接點；形成第二互連於該第二晶粒與一第三晶粒之間，其中該第三晶粒具有一具備導電接點之第一表面及一相對的第二表面，且其中該等第二互連將該第二晶粒之該等第二導電接點耦合至該第三晶粒之該等導電接點；及形成第三互連於該第一晶粒與該第三晶粒之間，其中該等第三互連將該第三晶粒之該等導電接點耦合至該第一晶粒之該等第二導電接點。
範例64可包括範例63之請求標的，且可進一步指明其該等第三互連包括一導電柱。
範例65可包括範例64之請求標的，且可進一步指明其該導電柱係藉由以下方式來形成：沈積並圖案化光阻劑材料以形成一或更多開口、沈積導電材料於該等一或更多開口中、及移除該光阻劑材料。
範例66可包括範例63之請求標的，且可進一步指明其該等第一互連或該等第二互連不包括焊料。
範例67可包括範例63之請求標的，且可進一步指明其該等第一互連或該等第二互連為金屬至金屬互連。
範例68可包括範例63之請求標的，且可進一步指明其該等第一互連或該等第二互連包括各向異性導電材料。
範例69可包括範例63之請求標的，且可進一步指明其該等第一互連之一節距係不同於該等第二互連之一節距。
範例70可包括範例63之請求標的，且可進一步指明其該等第二互連之一節距係不同於該等第三互連之一節距。
範例71可包括範例63之請求標的，且可進一步包括：形成一再分佈層於該第一晶粒與該第二晶粒之間或者於該第二晶粒與該第三晶粒之間。
範例72可包括範例63之請求標的，且可進一步包括：形成第四互連於該第一晶粒與一封裝基材之間，其中該第四互連將該第一晶粒上之該等第一導電接點耦合至該封裝基材之一表面上的導電接點。
100:微電子總成 102:封裝基材 104:多層晶粒總成 104-1:第一層 104-2:第二層 104-3:第三層 104-4:第四層 104-5:第五層 104-6:第六層 114、114-1~114-25:晶粒 114A、114B、114C、114D:晶粒 122、122-1、122-2:導電接點 124、124-1、124-2、124-3、124-4:導電接點 127:下填材料 130、130-1、130-2:晶粒至晶粒(DTD)互連 146:導電接點 148:再分佈層(RDL) 149、149-1、149-2:封裝基材部分 150、150-1、150-2:晶粒至封裝基材(DTPS)互連 152:多階(ML)互連 155、155-1、155-2、155-3:藉由晶粒至RDL(DTRDL)互連 164:厚度 165:厚度 167:厚度 169:厚度 172、174:導電接點 191、193:重疊距離 205:邊緣 207:角落 400A、400B、400C、400D、400E、400F、400G、400H、400I:總成 402:載體 430、431、432、433:絕緣材料 434、435、436:導電柱 455、456:去填充區 483:種晶層 600A、600B、600C、600D、600E、600F:總成 602:載體 630、631、632:絕緣材料 634、635、636:導電柱 648:RDL 655:去填充區 672、674:導電接點 1500:晶圓 1502:晶粒 1600:IC裝置 1602:晶粒基材 1604:裝置層 1606-1610:互連層 1619:金屬化堆疊 1620:源極及/或汲極(S/D)區 1622:閘極 1624:S/D接點 1626:電介質材料 1628:互連結構 1628a:線 1628b:通孔 1634:焊料抗蝕劑材料 1636:導電接點 1640:電晶體 1700:IC裝置總成 1702:電路板 1704:中介層 1706:TSV 1708:金屬互連 1710:通孔 1714:嵌入式裝置 1716、1718:耦合組件 1720:IC封裝 1722:耦合組件 1724、1726、1732:IC封裝 1728、1730:耦合組件 1734:堆疊式封裝結構 1736:中介層上封裝結構 1800:電氣裝置 1802:處理裝置 1804:記憶體 1806:顯示裝置 1808:音頻輸出裝置 1810:其他輸出裝置 1812:通訊晶片 1814:電池/電源電路 1818:GPS裝置 1820:其他輸入裝置 1822:天線 1824:音頻輸入裝置
實施例將藉由以下配合後附圖形之詳細描述而被輕易地瞭解。為了協助此描述，類似的參考數字係指定類似的結構元件。實施例係以範例之方式(非以限制之方式)被闡明於附圖之圖形中。
圖1A為一範例微電子總成之側面、橫斷面視圖，依據各個實施例。
圖1B為圖1A之微電子總成中所包括的晶粒之頂部視圖，依據各個實施例。
圖1C為圖1A之微電子總成中所包括的晶粒之底部視圖，依據各個實施例。
圖2A為一微電子總成中之多數晶粒的範例配置之頂部視圖，依據各個實施例。
圖2B為圖2A之範例配置中所包括的晶粒之頂部視圖，依據各個實施例。
圖3為一範例微電子總成之側面、橫斷面視圖，依據各個實施例。
圖4A-4I為用以製造圖3之微電子總成的範例製程中之各個階段的側面、橫斷面視圖，依據各個實施例。
圖5為一範例微電子總成之側面、橫斷面視圖，依據各個實施例。
圖6A-6F為用以製造圖5之微電子總成的範例製程中之各個階段的側面、橫斷面視圖，依據各個實施例。
圖7為一範例微電子總成之側面、橫斷面視圖，依據各個實施例。
圖8為一微電子總成中可包括之晶圓及晶粒的頂部視圖，依據文中所揭露的實施例之任一者。
圖9為一微電子總成中可包括之IC裝置的橫斷面側視圖，依據文中所揭露的實施例之任一者。
圖10為一可包括微電子總成之IC裝置總成的橫斷面側視圖，依據文中所揭露的實施例之任一者。
圖11為一可包括微電子總成之範例電氣裝置的方塊圖，依據文中所揭露的實施例之任一者。
100:微電子總成
102:封裝基材
104:多層晶粒總成
104-1:第一層
104-2:第二層
104-3:第三層
114-1~114-6:晶粒
122:導電接點
124:導電接點
127:下填材料
130-1、130-2:晶粒至晶粒(DTD)互連
146:導電接點
150-1、150-2:晶粒至封裝基材(DTPS)互連
152:多階(ML)互連
164:厚度
191、193:重疊距離

Claims (25)

  1. 一種微電子總成，包含： 一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中且其中該第一晶粒之該第一表面係藉由第一互連而被耦合至一封裝基材之一表面； 一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及 一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中且其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。
  2. 如申請專利範圍第1項之微電子總成，其中該第二晶粒之該第一表面係藉由第四互連而被耦合至該封裝基材之該表面。
  3. 如申請專利範圍第2項之微電子總成，其中該等第四互連包括一導電柱。
  4. 如申請專利範圍第3項之微電子總成，其中一個別導電柱具有介於50微米與400微米之間的直徑。
  5. 如申請專利範圍第1項之微電子總成，其中該第三晶粒之該第一表面係藉由第五互連而被耦合至該封裝基材之該表面。
  6. 如申請專利範圍第1項之微電子總成，其中該第三晶粒之該第一表面係藉由第六互連而被耦合至該第一晶粒之該第二表面。
  7. 如申請專利範圍第6項之微電子總成，其中該等第六互連包括一導電柱。
  8. 如申請專利範圍第7項之微電子總成，其中一個別導電柱具有介於10微米與300微米之間的直徑。
  9. 如申請專利範圍第1項之微電子總成，進一步包含： 一第四晶粒，其具有一第一表面及一相對的第二表面，其中該第四晶粒被嵌入該第一電介質層中，其中該第四晶粒之該第一表面係藉由第七互連而被耦合至該封裝基材之該表面，且其中該第四晶粒之該第二表面係藉由第八互連而被耦合至該第二晶粒之該第一表面。
  10. 如申請專利範圍第1項之微電子總成，進一步包含： 一第五晶粒，其具有一第一表面及一相對的第二表面，其中該第五晶粒被嵌入該第三電介質層中，且其中該第五晶粒之該第一表面係藉由第九互連而被耦合至該第二晶粒之該第二表面。
  11. 如申請專利範圍第10項之微電子總成，其中該第三晶粒之厚度係不同於該第五晶粒之厚度。
  12. 如申請專利範圍第1項之微電子總成，其中該等第一互連之節距係不同於該等第二互連之節距。
  13. 如申請專利範圍第1項之微電子總成，其中該等第二互連之節距係不同於該等第三互連之節距。
  14. 一種計算裝置，包含： 一微電子總成，其包含： 一封裝基材，其具有一表面； 一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中且其中該第一晶粒之該第一表面係藉由第一互連而被耦合至該封裝基材之該表面； 一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面；及 一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中且其中該第三晶粒之該第一表面係藉由第三互連而被耦合至該第二晶粒之該第二表面。
  15. 如申請專利範圍第14項之計算裝置，進一步包含： 一再分佈層，介於該第一電介質層與該第二電介質層之間、或介於該第二電介質層與該第三電介質層之間。
  16. 如申請專利範圍第14項之計算裝置，其中該等第一互連之節距係不同於該等第二互連之節距。
  17. 如申請專利範圍第14項之計算裝置，其中該等第二互連之節距係不同於該等第三互連之節距。
  18. 一種微電子總成，包含： 一第一晶粒，其具有一第一表面及一相對的第二表面，其中該第一晶粒被嵌入一第一電介質層中； 一第二晶粒，其具有一第一表面及一相對的第二表面，其中該第二晶粒被嵌入一第二電介質層中且其中該第二晶粒之該第一表面係藉由第一互連而被耦合至該第一晶粒之該第二表面；及 一第三晶粒，其具有一第一表面及一相對的第二表面，其中該第三晶粒被嵌入一第三電介質層中，且其中該第三晶粒之該第一表面係藉由第二互連而被耦合至該第一晶粒之該第二表面，其中該第二互連包括一導電柱。
  19. 如申請專利範圍第18項之微電子總成，其中一個別導電柱具有介於10微米與300微米之間的直徑。
  20. 如申請專利範圍第18項之微電子總成，其中該等第一互連之節距係不同於該等第二互連之節距。
  21. 如申請專利範圍第18項之微電子總成，進一步包含： 一再分佈層，介於該第一電介質層與該第二電介質層之間、或介於該第二電介質層與該第三電介質層之間。
  22. 一種製造微電子總成之方法，包含： 形成第一互連於一第一晶粒與一第二晶粒之間，其中該第一晶粒具有一具備第一導電接點之第一表面及一具備第二導電接點之相對的第二表面，其中該第二晶粒具有一具備第一導電接點之第一表面及一具備第二導電接點之相對的第二表面，且其中該等第一互連將該第一晶粒之該等第二導電接點耦合至該第二晶粒之該等第一導電接點； 形成第二互連於該第二晶粒與一第三晶粒之間，其中該第三晶粒具有一具備導電接點之第一表面及一相對的第二表面，且其中該等第二互連將該第二晶粒之該等第二導電接點耦合至該第三晶粒之該等導電接點；及 形成第三互連於該第一晶粒與該第三晶粒之間，其中該等第三互連將該第三晶粒之該等導電接點耦合至該第一晶粒之該等第二導電接點。
  23. 如申請專利範圍第22項之方法，其中該等第三互連包括一導電柱。
  24. 如申請專利範圍第23項之方法，其中該導電柱係藉由以下方式來形成：沈積並圖案化光阻劑材料以形成一或更多開口、沈積導電材料於該等一或更多開口中、及移除該光阻劑材料。
  25. 如申請專利範圍第22項之方法，進一步包含： 形成第四互連於該第一晶粒與一封裝基材之間，其中該第四互連將該第一晶粒上之該等第一導電接點耦合至該封裝基材之一表面上的導電接點。
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