TWI792384B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI792384B
TWI792384B TW110124426A TW110124426A TWI792384B TW I792384 B TWI792384 B TW I792384B TW 110124426 A TW110124426 A TW 110124426A TW 110124426 A TW110124426 A TW 110124426A TW I792384 B TWI792384 B TW I792384B
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Taiwan
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semiconductor
laminate
columnar electrode
chip
electrode
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TW110124426A
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TW202236559A (zh
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佐野雄一
三浦正幸
長谷川一磨
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日商鎧俠股份有限公司
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Abstract

本實施形態之半導體裝置具備第1積層體、第1柱狀電極、第2積層體、及第2柱狀電極。第1積層體由複數個第1半導體晶片向垂直於積層方向之方向偏移而積層。第1柱狀電極與第1半導體晶片之電極墊連接，沿第1半導體晶片之積層方向延伸。第2積層體由複數個第2半導體晶片向垂直於積層方向之方向偏移而積層，且積層為較第1積層體高，且，配置為自積層方向觀察，與第1積層體之至少一部分重疊。第2柱狀電極係與第2半導體晶片之電極墊連接，沿第2半導體晶片之積層方向延伸。

Description

半導體裝置及其製造方法
本實施形態係關於一種半導體裝置及其製造方法。
於半導體裝置之封裝構造中，記憶體晶片等之半導體晶片設置於基板上。期望封裝小型化。
一實施形態提供一種可使封裝更小之半導體裝置及其製造方法。
本實施形態之半導體裝置具備第1積層體、第1柱狀電極、第2積層體、及第2柱狀電極。第1積層體由複數個第1半導體晶片向垂直於積層方向之方向偏移而積層。第1柱狀電極與第1半導體晶片之電極墊連接，沿第1半導體晶片之積層方向延伸。第2積層體由複數個第2半導體晶片向垂直於積層方向之方向偏移而積層，且積層為較第1積層體高，且，配置為自積層方向觀察，與第1積層體之至少一部分重疊。第2柱狀電極與第2半導體晶片之電極墊連接，沿第2半導體晶片之積層方向延伸。
根據上述構成，可提供一種可使封裝更小之半導體裝置及其製造方法。
以下，參照圖式說明本發明之實施形態。本實施形態並非限定本發明。以下實施形態中，上下方向有時表示將半導體晶片之積層方向設為上或下之情形之相對方向，與根據重力加速度之上下方向不同。圖式為模式性或概念性者，各部分之比例等未必與實物相同。於說明書與圖式中，對與已出現之圖式相關描述者同樣之要件，標註相同符號且適當省略詳細說明。
(第1實施形態) 圖1係顯示第1實施形態之半導體裝置1之構成之一例之剖視圖。半導體裝置1具備積層體S1、柱狀電極30、積層體S2、柱狀電極70、半導體晶片200、連接柱210、樹脂層90、再配線層100、及金屬凸塊150。半導體裝置1亦可為例如NAND(Not-AND：反及)型快閃記憶體、LSI(Large Scale Integration：大型積體電路)等之半導體封裝。
積層體S1具有半導體晶片10、及接著層20。接著層20為例如DAF(Die Attachment Film：晶粒附著膜)。積層體S1為複數個半導體晶片10向垂直於積層方向之方向偏移而積層之積層體。
複數個半導體晶片10分別具有第1面F10a、及第1面之相反側之第2面F10b。記憶胞陣列、電晶體或電容器等之半導體元件(未圖示)形成於各半導體晶片10之第1面F10a上。半導體晶片10之第1面F10a上之半導體元件由未圖示之絕緣膜被覆且保護。 該絕緣膜例如使用氧化矽膜或氮化矽膜等之無機系絕緣材料。此外，該絕緣膜亦可使用將有機系絕緣材料形成於無機系絕緣材料上之材料。作為有機系絕緣材料，例如使用苯酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole：聚對苯撐苯並雙噁唑)系樹脂、矽系樹脂、苯並環丁烯系樹脂等之樹脂、或該等之混合材料、複合材料等之有機系絕緣材料。半導體晶片10例如亦可為NAND型快閃記憶體之記憶體晶片或搭載任意LSI之半導體晶片。半導體晶片10可為彼此具有相同構成之半導體晶片，亦可為彼此具有不同構成之半導體晶片。
複數個半導體晶片10積層，且由接著層20接著。作為接著層20，例如使用苯酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽系樹脂、苯並環丁烯系樹脂等之樹脂、或該等之混合材料、複合材料等之有機系絕緣材料。複數個半導體晶片10分別具有露出於第1面F10a上之電極墊15。積層於半導體晶片10(下階半導體晶片10)上之其他半導體晶片10(上階半導體晶片10)，以未重合於下階半導體晶片10之電極墊15上之方式，相對於設置有下階半導體晶片10之電極墊15之邊，於大致垂直方向(X方向)上偏移而積層。
電極墊15與設置於半導體晶片10之半導體元件之任一者電性連接。電極墊15例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al、Ti、Ta、TiN、TaN、CrN等之單體、該等中2種以上之複合膜、或該等中2種以上之合金等之低電阻金屬。
柱狀電極30連接於半導體晶片10之電極墊15，且沿複數個半導體晶片10之積層方向(Z方向)延伸。接著層20以露出電極墊15之一部分之方式被部分地去除，且柱狀電極30可連接於電極墊15。或，接著層20設置為貼附於上階半導體晶片10之第2面F10b，且未與下階半導體晶片10之電極墊15重合。柱狀電極30之下端例如藉由引線接合法連接於電極墊15。 柱狀電極30之上端到達樹脂層90之上表面，且於該上表面露出。柱狀電極30之上端連接於再配線層100之電極墊110。
此外，積層體S1之半導體晶片10以露出電極墊15之方式向積層體S2偏移而積層。柱狀電極30於第1面F10a中與配置於積層體S2之相反側之電極墊15連接。
積層體S2具有半導體晶片50、及接著層60。積層體S2為複數個半導體晶片50向垂直於積層方向之方向偏移而積層之積層體。積層體S2包含複數個半導體晶片中最下層之半導體晶片即第2最下層晶片50B、及最上層之半導體晶片即第2最上層晶片50U。積層體S1包含複數個半導體晶片中最下層之半導體晶片即第1最下層晶片10B、及最上層之半導體晶片即第1最上層晶片10U。另外，關於積層體S1與積層體S2之關係之細節，參照圖2A及圖2B於下文說明。
複數個半導體晶片50分別具有第1面F50a、及第1面F50a之相反側之第2面F50b。記憶胞陣列、電晶體或電容器等之半導體元件(未圖示)形成於各半導體晶片50之第1面F50a上。半導體晶片50之第1面F50a上之半導體元件由未圖示之絕緣膜被覆且保護。該絕緣膜例如使用氧化矽膜或氮化矽膜等之無機系絕緣材料。此外，該絕緣膜亦可使用將有機系絕緣材料形成於無機系絕緣材料上之材料。作為有機系絕緣材料，例如使用苯酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽系樹脂、苯並環丁烯系樹脂等之樹脂、或該等之混合材料、複合材料等之有機系絕緣材料。半導體晶片50例如亦可為NAND型快閃記憶體之記憶體晶片或搭載任意LSI之半導體晶片。半導體晶片50亦可為彼此具有相同構成之半導體晶片，亦可為彼此具有不同構成之半導體晶片。再者，半導體晶片50亦可為具有與半導體晶片10相同構成之半導體晶片，亦可為具有與半導體晶片10不同構成之半導體晶片。
複數個半導體晶片50積層，且由接著層60接著。複數個半導體晶片50分別具有露出於第1面F50a上之電極墊55。積層於其他半導體晶片50上之半導體晶片50，以未重合於其他半導體晶片50之電極墊55上之方式，相對於設置有電極墊55之邊，於大致垂直方向(X方向)上偏移而積層。
電極墊55與設置於半導體晶片50之半導體元件之任一者電性連接。電極墊55例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al、Ti、Ta、TiN、TaN、CrN等之單體、該等中2種以上之複合膜、或該等中2種以上之合金等之低電阻金屬。
柱狀電極70連接於半導體晶片50之電極墊55，且沿複數個半導體晶片50之積層方向(Z方向)延伸。接著層60以露出電極墊55之一部分之方式被部分地去除，且柱狀電極70可連接於電極墊55。或，接著層60設置為貼附於上階半導體晶片50之第2面F50b，且未與下階半導體晶片50之電極墊55重合。柱狀電極70之下端例如藉由引線接合法連接於電極墊55。 柱狀電極70之上端到達樹脂層90之上表面，且於該上表面露出。柱狀電極70之上端連接於再配線層100之電極墊110。
此外，積層體S2之半導體晶片50以露出電極墊55之方式向積層體S1偏移而積層。柱狀電極70於第1面F50a中與配置於積層體S1之相反側之電極墊55連接。
半導體晶片200具有第1面F200a、及第1面之相反側之第2面F200b。電晶體或電容器等之半導體元件(未圖示)形成於各半導體晶片200之第1面F200a上。半導體晶片200之第1面F200a上之半導體元件由未圖示之絕緣膜被覆且保護。該絕緣膜例如使用氧化矽膜或氮化矽膜等之無機系絕緣材料。此外，該絕緣膜亦可使用將有機系絕緣材料形成於無機系絕緣材料上之材料。作為有機系絕緣材料，例如使用苯酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽系樹脂、苯並環丁烯系樹脂等之樹脂、或該等之混合材料、複合材料等之有機系絕緣材料。半導體晶片200例如亦可為控制記憶體晶片(半導體晶片10、50)之控制晶片或搭載任意LSI之半導體晶片。
半導體晶片200積層於半導體晶片50上，且由接著層接著於半導體晶片50。半導體晶片200分別具有露出於第1面F200a上之電極墊205。
連接柱(連接凸塊)210連接於半導體晶片200之電極墊205，且沿Z方向延伸。連接柱210之下端連接於半導體晶片200之電極墊205。連接柱210之上端到達樹脂層90之上表面，且於該上表面露出。連接柱210之上端連接於再配線層100之電極墊110。連接柱210之材料可使用例如Cu等之導電性金屬。柱狀電極30及柱狀電極70可由引線接合等形成，連接柱210可由鍍覆法等形成，因此，柱狀電極30及柱狀電極70與連接柱210之粗細、材質亦可不同。
樹脂層90被覆(密封)積層體S1、S2、半導體晶片200、柱狀電極30、70及連接柱210，且於上表面中露出柱狀電極30、70及連接柱210之前端。
樹脂層90例如使用苯酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽系樹脂、苯並環丁烯系樹脂等之樹脂、或該等之混合材料、複合材料等之有機系絕緣材料。
再配線層(RDL(Re Distribution Layer：重新分佈層))100設置於樹脂層90上，且電性連接於柱狀電極30、70及連接柱210。再配線層100係使複數個配線層與複數個絕緣層積層之多層配線層，將柱狀電極30、70及連接柱210分別電性連接於金屬凸塊150。另，圖1模式性顯示再配線層100內之配線層。
金屬凸塊150設置於再配線層100上，且電性連接於再配線層100之配線層。金屬凸塊150用於與外部裝置(未圖示)連接。金屬凸塊150例如使用Sn、Ag、Cu、Au、Pd、Bi、Zn、Ni、Sb、In、Ge之單體、該等中2種以上之複合膜、或合金。
接著，就積層體S1與積層體S2之關係進行說明。
圖2A係顯示第1實施形態之半導體裝置1之構成之一例之剖視圖。圖2B係顯示第1實施形態之半導體裝置1之構成之一例之俯視圖。圖2B亦可為自Z方向觀察圖2A之積層體S1、S2及半導體晶片200之圖。
另，圖2A及圖2B所示之積層體S1、S2與圖1所示之積層體S1、S2之積層數不同。然而，圖2A及圖1於積層體S2高於積層體S1之點上共通。此外，於圖2A及圖2B中，省略接著層20、60及電極墊15、55、205等。
積層體S1具有積層之7階半導體晶片10。積層體S2具有積層之9階半導體晶片50。因此，積層體S2之積層數大於積層體S1之積層數。於圖2A所示之例中，半導體晶片10之厚度與半導體晶片50之厚度大致相同。因此，積層體S2高於積層體S1。另外，於圖2A及圖2B所示之例中，積層體S1、S2設置於支持基板2上。
如圖2A所示，積層體S1之半導體晶片10向積層體S2(沿X方向)偏移而積層。積層體S2之半導體晶片50向積層體S1(沿-X方向)偏移而積層。如圖2B所示，積層體S2配置為自積層方向(Z方向)觀察，與積層體S1之至少一部分重疊。藉此，可將積層體S1與積層體S2交疊配置，且可將積層體S1與積層體S2彼此更接近配置。其結果，可使XY平面之封裝之面積更小。
接著，就半導體裝置1之製造方法進行說明。
圖3A～圖3E係顯示第1實施形態之半導體裝置1之製造方法之一例之剖視圖。
首先，如圖3A所示，藉由使複數個半導體晶片10積層於支持基板2上而形成積層體S1。此時，半導體晶片10以接著層20接著於其他半導體晶片10上。支持基板2亦可為矽、玻璃、陶瓷、樹脂板、引線框架等之金屬板等。
接著，藉由使複數個半導體晶片50積層於支持基板2上而形成積層體S2。此時，半導體晶片50以接著層60接著於其他半導體晶片50上。
另，可先形成積層體S1、S2之任一者。然而，若先形成較積層體S1高之積層體S2，則有時難以使半導體晶片10積層。因此，更佳為先形成積層體S1。
接著，將半導體晶片200積層於最上階之半導體晶片50上。連接柱210例如於將半導體晶片200設置於最上階之半導體晶片50上之前，形成於半導體晶片200之電極墊205。連接柱210例如藉由鍍覆法形成。連接柱210之材料例如使用Cu等之導電性金屬。
接著，如圖3B所示，於半導體晶片10、50之各者形成柱狀電極30、70。於半導體晶片10、50之電極墊15、55上以引線接合法接合金屬引線(導電性引線)，且將該金屬引線沿相對於第1面F10a、F50a大致垂直方向引出而形成柱狀電極30、70。此外，柱狀電極30、70於上端被切斷，藉由柱狀電極30、70自身之剛性而維持直立狀態。
柱狀電極30、70例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al、Ti、Ta之單體、該等中2種以上之複合材料、或該等中2種以上之合金等。較佳使用Au、Ag、Cu、Pd之單體、該等中2種以上之複合材料、或該等中2種以上之合金等，作為柱狀電極30、70之材料。進而較佳為，使用該等中硬度較高之材料，例如Cu、CuPd合金、將Pd被覆於Cu上之材料作為柱狀電極30、70之材料。藉此，柱狀電極30、70不易於由樹脂層90被覆時彎曲、倒塌。
接著，如圖3C所示，以樹脂層90被覆包含積層體S1、S2、半導體晶片200、柱狀電極30、70及連接柱210之構造體。樹脂層90使用例如環氧系、苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽系、苯並環丁烯系等之樹脂、該等之混合材料、複合材料。作為環氧樹脂之例，並無特別限定，例如列舉雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、苯酚酚醛型、甲酚酚醛型等酚醛型環氧樹脂、間苯二酚型環氧樹脂、三苯酚甲烷三環氧丙醚等芳香族環氧樹脂、萘型環氧樹脂、芴型環氧樹脂、雙環戊二烯型環氧樹脂、聚醚改質環氧樹脂、二苯甲酮型環氧樹脂、苯胺型環氧樹脂、NBR(Nitrile Butadiene Rubber：丁腈橡膠)改質環氧樹脂、CTBN(Carboxyl Terminated Butadiene Acrylonitrile Rubber：端羧基液態丁腈橡膠)改質環氧樹脂、及該等之氫化物等。該等中，因與矽之密接性較好，故較佳為萘型環氧樹脂、雙環戊二烯型環氧樹脂。此外，因容易獲得快速硬化性，故二苯甲酮型環氧樹脂亦較佳。該等環氧樹脂可單獨使用，亦可並用2種以上。此外，可於樹脂層90中包含矽石等之填充物。
形成樹脂層90後，以乾燥器等加熱樹脂層90，或對樹脂層90照射UV(Ultraviolet：紫外線)光，藉此使樹脂層90硬化。
接著，如圖3D所示，以自樹脂層90露出柱狀電極30、70及連接柱210之方式，研削樹脂層90之上表面。例如，使用CMP(Chemical Mechanical Polishing：化學機械研磨)法或機械研磨法等，研磨樹脂層90直至露出柱狀電極30、70及連接柱210。
接著，如圖3E所示，於樹脂層90上形成再配線層100。再配線層100之絕緣層例如使用環氧系、苯酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽系、苯並環丁烯系等樹脂、該等之混合材料、複合材料。再配線層100之配線層例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al、Ti、Ta、TiN、TaN、CrN等單體、該等中2種以上之複合材料、或該等中2種以上之合金等。
接著，使用熱、雷射等光將支持基板2剝離。或者，亦可研磨去除支持基板2。另，亦去除設置於最下階之半導體晶片10、50之第2面F10b、F50b之接著層20、60。
圖3E之步驟後，於再配線層100上形成金屬凸塊150。金屬凸塊150例如可使用球搭載、鍍覆法、印刷法來形成。金屬凸塊150例如使用Sn、Ag、Cu、Au、Pd、Bi、Zn、Ni、Sb、In、Ge之單體、該等中2種以上之複合膜、或合金。
之後，將圖3E之步驟所獲得之構造體及樹脂層90，藉由切割於每一封裝單片化。藉此，獲得圖1所示之半導體裝置1。
另外，於圖3A及圖3B之步驟中，積層體S1之形成、柱狀電極30之形成、積層體S2之形成及柱狀電極70之形成亦可按該順序進行。
此外，封裝之厚度有餘裕時，於圖3E之步驟中，亦可不去除支持基板2而保持殘留。此時，半導體裝置1之封裝與支持基板2一同被切割。藉由支持基板2，可保護最下階之半導體晶片10之第2面F10b、及最下階之半導體晶片50之第2面F50b。支持基板2為金屬等之情形時，提高電磁波屏蔽性。又，亦可將支持基板2設為接地電位。此時，於支持基板2與第1積層體S1及第2積層體S2之間介存接著層。
於上述實施形態中，柱狀電極30、70作為一例以引線接合法形成，但亦可以鍍覆法形成。例如，將到達電極墊15、55之孔形成於樹脂層90後，以鍍覆法將金屬材料嵌入孔。藉此，可藉由鍍覆法形成柱狀電極30、70。柱狀電極30、70亦可使用此種鍍覆法與引線接合法之兩者而形成。
本實施形態之柱狀電極30、70亦可與將以通常之引線接合法形成之半導體晶片之電極墊間直接連接之引線混雜。再者，亦可使將半導體晶片間直接連接之引線、以引線接合法形成之柱狀電極、及以鍍覆法形成之柱狀電極混雜。
如上所述，根據第1實施形態，高度不同之2個積層體S1、S2以交疊之方式配置。藉此，可使2個積層體S1、S2更接近地配置。其結果，可使封裝更小。
圖4係顯示第1比較例之半導體裝置1a之構成之一例之剖視圖。
於圖4所示之例中，設置具有積層之16階之半導體晶片10a之積層體S1a。於第1比較例中，設置1個積層體S1a。然而，此時，積層數越增加，積層體S1a變得越高。因此，致使封裝於Z方向上變高。
與此相對，於第1實施形態中，如圖2A所示，分為2個積層體S1、S2，分別積層半導體晶片10、50。封裝之高度由2個積層體S1、S2中較高之積層體之高度決定。於圖2A所示之例中，封裝之高度由具有9階之半導體晶片50之積層體S2之高度決定。因此，藉由分為2個積層體S1、S2，可將封裝之高度設得更小。
圖5係顯示第2比較例之半導體裝置1b之構成之一例之剖視圖。
於圖5所示之例中，設置2個積層體S1b、S2b。2個積層體S1b、S2b自積層方向(Z方向)觀察，彼此未重疊。此時，作為封裝之面積，至少需要積層體S1b、S2b各者之面積。
與此相對，於第1實施形態中，積層體S1、S2之高度彼此不同，且積層體S1、S2以彼此交疊之方式配置。藉此，可將自積層方向觀察之2個積層體S1、S2之面積設得較積層體S1之面積與積層體S2之面積之和更小。其結果，可使封裝之面積更小。
此外，於第1實施形態中，半導體晶片200配置於較積層體S1高之積層體S2上。若於圖2A中，半導體晶片200配置於較積層體S2低之積層體S1上之情形時，為研磨樹脂層90且使連接柱210露出，必須使連接柱210形成得較長。與此相對，於第1實施形態中，因半導體晶片200配置於積層體S2上，故可將形成之連接柱210設得更短。
此外，於第1實施形態中，柱狀電極30至少於每一半導體晶片10設置，柱狀電極70至少於每一半導體晶片50設置。於通常之引線接合法中，例如以引線連接4個記憶體晶片，4個中之1個記憶體晶片經由引線與基板連接。然而，使半導體裝置1高速動作時，更佳為將複數個半導體晶片分別與基板連接。使用柱狀電極之情形時，與通常之引線接合法比較，使複數個記憶體晶片之各者不經由其他記憶體晶片而易與基板連接。於第1實施形態中，半導體晶片10不經由其他半導體晶片10而與再配線層100連接，且半導體晶片50不經由其他半導體晶片50而與再配線層100連接。
此外，於第1實施形態中，使用再配線層100作為基板。再配線層100與柱狀電極30、70及連接柱210電性連接。如上所述，於將複數個記憶體晶片未經由其他記憶體晶片而連接之情形時，必須將更多配線設置於基板內。此外，於柱狀電極30、70及連接柱210之各者中，相鄰之柱狀電極之間隔越窄，越需要將更多配線設置於柱狀電極周邊之基板內。因此，基板內之配線層之數量增加，致使基板變厚。此會導致封裝之厚度增大。此處，於使用再配線層100之情形時，與覆晶連接於配線基板之情形比較，可獲得更細之配線。因此，可提高配線密度，且可減少配線層之積層數。其結果，可將基板及封裝設得更薄。
此外，於半導體晶片200之電極墊205，連接有連接柱210。亦考慮取代連接柱210，於電極墊205連接柱狀電極。然而，電極墊205之墊間距越小，形成柱狀電極越困難。因此，亦可使用柱狀電極，但更佳為使用連接柱210。
另，上述積層體S1、S2之積層數為一例。
(第1實施形態之變化例) 圖6A係顯示第1實施形態之第1變化例之半導體裝置1之構成之一例之剖視圖。圖6B係顯示第1實施形態之第1變化例之半導體裝置1之構成之一例之俯視圖。第1實施形態之第1變化例與第1實施形態比較，半導體晶片200之配置不同。
於圖6A所示之例中，半導體晶片200配置於較積層體S2低之積層體S1上。圖6A所示之半導體晶片200較圖2A所示之半導體晶片200厚。半導體晶片200例如較半導體晶片10、50厚。藉此，於半導體晶片200配置於積層體S1上時，亦可將形成之連接柱210設得較短。通常，半導體晶片200為半導體元件之相反側即第2面F200b之半導體基板被研磨，薄化為理想之厚度。於圖6A所示之例中，與圖2A比較，半導體晶片200半導體基板之研磨量較少。
如圖6B所示，積層體S2與第1實施形態之圖2B同樣，配置為自積層方向(Z方向)觀察，與積層體S1之至少一部分重疊。
圖7A係顯示第1實施形態之第2變化例之半導體裝置1之構成之一例之剖視圖。第1實施形態之第2變化例與第1實施形態比較，半導體晶片10、50之積層數不同。
於圖7A所示之例中，積層體S1具有積層之6階半導體晶片10。積層體S2具有積層之10階半導體晶片50。積層體S2配置為，根據積層體S1之高度與積層體S2之高度之差，自積層方向觀察，與積層體S1之至少一部分重疊。
第2變化例之積層體S2因較第1實施形態之積層體S2高，故致使封裝變高。然而，第2變化例之積層體S1較第1實施形態之積層體S1低。藉此，於第2變化例中，與第1實施形態比較，可將積層體S1、S2以進一步交疊之方式配置。即，可將積層體S1、S2彼此接近配置，且可將封裝之面積設得更小。因此，於預先決定封裝內之半導體晶片10、50之合計片數之情形時，可藉由變更積層體S1、S2之高度之配設，而變更封裝之高度與面積之比例。其結果，可提高封裝尺寸之設計自由度。
圖7B係顯示第1實施形態之第3變化例之半導體裝置1之構成之一例之剖視圖。第1實施形態之第3變化例於半導體晶片200配置於積層體S1上之點上，與第2變化例不同。因此，第3變化例為第1變化例與第2變化例之組合。
圖8A係顯示第1實施形態之第4變化例之半導體裝置1之構成之一例之剖視圖。第1實施形態之第4變化例與第1實施形態比較，半導體晶片10、50之積層數不同。
於圖8A所示之例中，積層體S1具有積層之5階之半導體晶片10。積層體S2具有積層之11階半導體晶片50。因此，於第4變化例中，與第2變化例之圖7A比較，可將積層體S1、S2以進一步交疊之方式配置。其結果，可使封裝之面積更小。
圖8B係顯示第1實施形態之第5變化例之半導體裝置1之構成之一例之剖視圖。第1實施形態之第5變化例於半導體晶片200配置於積層體S1上之點上，與第4變化例不同。因此，第5變化例為第1變化例與第4變化例之組合。
圖9A係顯示第1實施形態之第6變化例之半導體裝置1之構成之一例之剖視圖。第1實施形態之第6變化例與第1實施形態比較，半導體晶片10、50之積層數不同。
於圖9A所示之例中，積層體S1具有積層之4階之半導體晶片10。積層體S2具有積層之12階半導體晶片50。因此，於第6變化例中，與第4變化例之圖8A比較，可將積層體S1、S2以進一步交疊之方式配置。其結果，可使封裝之面積更小。
圖9B係顯示第1實施形態之半導體裝置1之構成之第7變化例之剖視圖。 第1實施形態之第7變化例於半導體晶片200配置於積層體S1上之點上，與第6變化例不同。因此，第7變化例為第1變化例與第6變化例之組合。
(第2實施形態) 圖10係顯示第2實施形態之半導體裝置1之構成之一例之剖視圖。第2實施形態於設置厚度不同之半導體晶片50之點上，與第1實施形態不同。
至少1個半導體晶片50較其他半導體晶片50厚。至少1個半導體晶片50與至少1個半導體晶片10於積層方向(Z方向)之位置相同。於圖10所示之例中，最下階之半導體晶片50較其他半導體晶片50厚。以下，將最下階之半導體晶片50與其他半導體晶片50區別稱為半導體晶片51。積層體S2配置為，根據半導體晶片51之厚度，自積層方向觀察，與積層體S1之至少一部分重疊。若半導體晶片51變厚，則積層體S1更容易進入積層體S2。即，積層體S1可更接近半導體晶片51。藉此，可使積層體S1、S2進一步交疊。其結果，可使封裝之面積更小。
第2實施形態之半導體裝置1之其他構成因與第1實施形態之半導體裝置1之對應之構成同樣，故省略其詳細說明。第2實施形態之半導體裝置1可獲得與第1實施形態同樣之效果。此外，亦可使第1實施形態之第1變化例～第7變化例與第2實施形態之半導體裝置1組合。
(第2實施形態之變化例) 圖11係顯示第2實施形態之變化例之半導體裝置1之構成之一例之剖視圖。第2實施形態於取代較厚之半導體晶片51而設置間隔件52之點上，與第1實施形態不同。
積層體S2具有間隔件52。間隔件52與半導體晶片50積層，且較半導體晶片厚。此時，因未設置較厚之半導體晶片51，故可將積層體S2中半導體晶片之厚度全部設為相同之厚度。間隔件52之材料使用例如矽。
(第3實施形態) 圖12係顯示第3實施形態之半導體裝置1之構成之一例之剖視圖。第3實施形態於取代再配線層100而使用對配線基板300之覆晶連接之點上，與第1實施形態不同。
半導體裝置1不具備再配線層100，進而具備金屬凸塊155、配線基板300、樹脂層310、及樹脂層320。
金屬凸塊(連接凸塊)155設置於柱狀電極30、70及連接柱210之上端部。金屬凸塊155之材料亦可與金屬凸塊150之材料同樣。 即，金屬凸塊155使用Sn、Ag、Cu、Au、Pd、Bi、Zn、Ni、Sb、In、Ge之單體、該等中2種以上之複合膜、或合金等之導電性金屬。
配線基板300為包含配線層與絕緣層之多層基板。絕緣層為例如預浸料。絕緣層為例如玻璃布等之纖維狀補強材料與環氧樹脂等之熱硬化性樹脂之複合材料。
此外，配線基板300經由金屬凸塊155，與柱狀電極30、70電性連接。例如，相鄰之柱狀電極間之間隔較廣之情形時，不需要再配線層100。藉此，不需要搭載再配線層100之步驟。此外，因不需要再配線層100，故減少半導體裝置1之成本。另，圖11模式性顯示配線基板300內之配線層。
樹脂層310將樹脂層90與配線基板300之間密封。此外，樹脂層310亦可用於樹脂層90與配線基板300之接著。
樹脂層320覆蓋樹脂層90之整體。另，剝離支持基板2之情形時，樹脂層320被覆且保護自樹脂層90露出之半導體晶片10、50之第2面F10b、F50b。
接著，就半導體裝置1之製造方法進行說明。
圖13A～圖13D係顯示第3實施形態之半導體裝置1之製造方法之一例之剖視圖。另，圖13A～圖13D顯示第1實施形態之圖3D中樹脂層90之研磨後之步驟。
圖3D之步驟後，如圖13A所示，於柱狀電極30、70之上端部形成金屬凸塊155。
接著，將圖13A之步驟所獲得之構造體及樹脂層90，藉由切割於每一封裝單片化。
接著，如圖13B所示，於配線基板300上塗布樹脂層310之材料310a。
接著，如圖13C所示，將樹脂層90搭載於配線基板300。即，使樹脂層90接著於配線基板300且經由金屬凸塊155將柱狀電極30、70及連接柱210、與配線基板300電性連接。
接著，如圖13D所示，以樹脂層320被覆支持基板2及樹脂層90、310。
之後，藉由於配線基板300上形成金屬凸塊150，而完成圖12所示之半導體裝置1。
第3實施形態之半導體裝置1之其他構成因與第1實施形態之半導體裝置1之對應之構成同樣，故省略其詳細說明。第3實施形態之半導體裝置1可獲得與第1實施形態同樣之效果。此外，亦可使第1實施形態之第1變化例～第7變化例與第3實施形態之半導體裝置1組合。此外，亦可使第2實施形態及第2實施形態之變化例與第3實施形態之半導體裝置1組合。
(第4實施形態) 圖14係顯示第4實施形態之半導體裝置1之構成之一例之剖視圖。第4實施形態於半導體晶片折回並積層之點上，與第1實施形態不同。另，於圖14中，省略樹脂層90及再配線層100等。
於第4實施形態中，積層體S1、S2之配置與第1實施形態不同。此外，半導體裝置1進而具備間隔件400。
積層體S1例如具有積層之4階之半導體晶片10。積層體S1之半導體晶片10向間隔件400(-X方向)偏移而積層。
柱狀電極30與半導體晶片10之電極墊15(未圖示)連接，且沿半導體晶片10之積層方向(Z方向)延伸。
此外，積層體S1之半導體晶片10以露出電極墊15之方式，向間隔件400偏移而積層。柱狀電極30於第1面F10a中與配置於間隔件400之相反側之電極墊15連接。
間隔件400與積層體S1同樣，設置於支持基板2上。因此，間隔件400與最下階之半導體晶片10之第2面F10b配置於相同面。間隔件400向垂直於積層方向之方向與積層體S1並列配置。間隔件400之高度為積層體S1之高度以上。間隔件400作為支持積層體S2之台座發揮功能。間隔件400之材料使用例如矽。
積層體S2配置於積層體S1及間隔件400之上方。積層體S2例如具有積層之4階之半導體晶片50。積層體S2之半導體晶片50向積層體S1之偏移方向之相反方向(X方向)偏移而積層。另，積層體S以未與柱狀電極30接觸之方式，離開配置。因此，更佳為積層體S2配置於間隔件400側而非積層體S1側。第2最下層晶片50B設置於第1最上層晶片10U上。第2最下層晶片50B設置於間隔件400上。此時，因積層體S2與間隔件400之至少一部分相接之面積變大，故間隔件400可更穩定地支持積層體S2。
最上階之半導體晶片10與最下階之半導體晶片50例如介隔接著層60相接。藉由以接著層60補償間隔件400之厚度與積層體S1之高度之差，可將最下階之半導體晶片50設置為大致水平。例如，更佳為貼附於最下階之半導體晶片50之接著層60，較貼附於其他半導體晶片50之接著層60厚。最下階之半導體晶片50之接著層60之厚度例如為約10 μm～約20 μm。其他半導體晶片50之接著層60之厚度例如為約5 μm。
柱狀電極70係與半導體晶片50之電極墊55(未圖示)連接，且沿半導體晶片50之積層方向(Z方向)延伸。
此外，積層體S2之半導體晶片50係以露出電極墊55之方式向柱狀電極30偏移而積層。柱狀電極70於第1面F50a中與配置於柱狀電極30之相反側之電極墊55連接。
半導體晶片200配置於積層體S2上。半導體晶片200配置於柱狀電極30與柱狀電極70之間。半導體晶片200自積層方向觀察，配置於積層體S1及積層體S2之區域之大致中心部。藉此，可將半導體晶片200配置於封裝之大致中央。半導體晶片200自積層方向觀察，與第1最下層晶片10B、第1最上層晶片10U、第2最下層晶片50B、第2最上層晶片50U至少一部分重疊。與積層體S1及積層體S2之全部半導體晶片，自積層方向觀察，至少一部分重疊。
連接柱210係與半導體晶片200之電極墊205(未圖示)連接且沿積層方向延伸。
接著，就半導體裝置1之製造方法進行說明。
於圖14所示之例中，更佳為於形成積層體S2之前，形成柱狀電極30。假設，於形成積層體S2後才形成柱狀電極30之情形，因有毛細管干涉積層體S2之可能性，故必須擴大積層體S2與柱狀電極30之間距。此會導致封裝面積增大。
於第1比較例之圖4中，半導體晶片200a配置於向一方向偏移而積層之積層體S1a上。因此，半導體晶片200a容易配置於封裝之端部，而難以配置於封裝之大致中央。此外，柱狀電極30a集中配置於半導體晶片200a之單側。因此，各半導體晶片10a至半導體晶片200a之配線長度之不均會變大。此會導致各半導體晶片10a之電性特性之不均增大。另，柱狀電極之長度較再配線層100a內之配線之長度短，對配線長度之影響較小。例如，越下階之半導體晶片10a，至半導體晶片200a之配線長度越長。此外，供安裝半導體裝置1a之外部裝置之端子與半導體晶片200a之間之配線長度亦同樣，不均會變大且變長。此導致半導體裝置1a之高速化受阻。此外，半導體晶片200越自封裝之中央離開，越容易使配線之鋪設集中，因而容易增大再配線層100之配線層之數量。另，有連接於半導體晶片200a之連接柱210a，較柱狀電極30a配置得高密度之情形，容易對配線之鋪設造成較大影響。
與此相對，於第4實施形態中，因於以自積層體S1折回之方式偏移而積層之積層體S2上設置半導體晶片200，故可容易將半導體晶片200配置於封裝之大致中央。此外，柱狀電極30、70以自兩側夾著連接柱210之方式配置。藉此，可抑制自半導體晶片200至半導體晶片10之配線長度、與自半導體晶片200至半導體晶片50之配線長度之間之不均。此外，可將自半導體晶片200至半導體晶片10、50之配線長度設得更短。因此，可抑制各半導體晶片10、50之電性特性之不均。外部裝置與半導體晶片200之間之配線長度亦同樣，可抑制不均且可設得更短。此外，可使配線之鋪設分散，且可抑制再配線層100之配線層之數量增大。因此，可將配線之長度及鋪設設得更適當。
此外，藉由間隔件400，可抑制積層體S1之高度之累積公差之影響。通常，半導體晶片之積層數越大，考慮半導體晶片之累積公差，必須使柱狀電極形成得越長。然而，因柱狀電極於樹脂層之研磨時會被磨損，故期望不形成得過長。與此相對，於第4實施形態中，形成與設置於間隔件400上之積層體S2之高度之累積公差相應之長度之柱狀電極30、70及連接柱210。即，不必考慮較間隔件400低之積層體S1之高度之累積公差。藉此，可將形成之柱狀電極30、70及連接柱210設得更短。
此外，藉由間隔件400，可抑制最下階之半導體晶片50之厚度增大。於未設置間隔件400之情形時，若因通常之引線接合使引線碰撞折回之半導體晶片，則有折回之半導體晶片破損之情形。其原因在於，電極墊之位置之半導體晶片與支持基板之間中空，故半導體晶片之強度變弱。若為確保半導體晶片之強度而將折回之半導體晶片(最下階之半導體晶片50)加厚，則致使封裝變厚。此外，若為防止半導體晶片50之破損，而使積層體S2靠近柱狀電極30側，則有致使積層體S2干涉柱狀電極30之可能性。與此相對，於第4實施形態中，因間隔件400支持最下階之半導體晶片50，故不必將最下階之半導體晶片50加厚。
另，積層體S1亦可為1階之半導體晶片10，又，積層體S2亦可為1階之半導體晶片50。
(第4實施形態之變化例) 圖15係顯示第4實施形態之第1變化例之半導體裝置1之構成之一例之剖視圖。第4實施形態之第1變化例於半導體晶片沿一方向偏移而積層之點上，與第4實施形態不同。
於圖15所示之例中，積層體S1具有積層之7階半導體晶片10。積層體S2具有1階之半導體晶片50。此時，不必考慮積層體S1之高度之累積公差。如此，積層體S1、S2之積層階數亦可變更。
圖16係顯示第4實施形態之第2變化例之半導體裝置1之構成之一例之剖視圖。第4實施形態之第2變化例於設置複數個間隔件之點上，與第4實施形態之第1變化例不同。
於圖16所示之例中，積層體S1具有積層體S11、及積層體S12。積層體S11具有積層之下側之4階半導體晶片10。積層體S12具有積層之上側之3階半導體晶片10。
半導體裝置1進而具備間隔件410。間隔件410設置於積層體S1之積層中途。間隔件410向垂直於積層方向之方向與積層體S11並列配置，且支持積層體S12。如此，間隔件之數量亦可變更。
圖17係顯示第4實施形態之第3變化例之半導體裝置1之構成之一例之剖視圖。第4實施形態之第3變化例與第4實施形態同樣，使積層體S1與積層體S2彼此向反方向偏移而積層。又，第4實施形態之第3變化例於設置複數個間隔件之點上，與第4實施形態不同。
於圖17所示之例中，積層體S2配置於積層體S1之上方，但最下階之半導體晶片50未與積層體S1之半導體晶片10相接。
積層體S2具有積層體S21、及積層體S22。積層體S21具有積層之下側之6階半導體晶片50。積層體S22具有上側之1階半導體晶片50。
半導體裝置1進而具備間隔件420。間隔件420設置於積層體S2之積層中途。間隔件420向垂直於積層方向之方向與積層體S21並列配置，且支持積層體S22。如此，間隔件之數量亦可變更。間隔件420設置於積層體1之最上層晶片10U上。
(第5實施形態) 圖18係第5實施形態之半導體裝置1之構成之一例之剖視圖。第5實施形態於設置連接柱狀電極之虛設晶片之點上，與第1實施形態不同。此外，以通常之引線接合法形成之直接連接半導體晶片之電極墊間之引線與柱狀電極混雜。
半導體裝置1具備引線17、57、間隔件400、虛設晶片500、接著層510、及柱狀電極520。
積層體S1具有積層之2階半導體晶片10。積層體S1之半導體晶片10向垂直於積層方向之方向偏移而積層。另外，柱狀電極未連接於半導體晶片10。
引線17將2個半導體晶片10分別具有之電極墊15間連接。此外，引線17將半導體晶片10之電極墊15、與虛設晶片500之電極墊505之間連接。引線17藉由通常之引線接合法形成。引線17之材料例如使用Au等之導電性金屬。
積層體S2具有積層之2階半導體晶片50。積層體S2之半導體晶片50向垂直於積層方向之方向偏移而積層。積層體S2配置於積層體S1之上方。另，柱狀電極未連接於半導體晶片50。
引線57將2個半導體晶片50分別具有之電極墊55間連接。此外，引線57將半導體晶片50之電極墊55、與虛設晶片500之電極墊505之間連接。引線57藉由通常之引線接合法形成。引線57之材料例如使用Au等之導電性金屬。
間隔件400以向垂直於積層方向之方向與積層體S1並列配置，且支持虛設晶片500之方式配置。間隔件400具有積層體S1以上之高度。間隔件400與第4實施形態說明之間隔件400大致同樣。因此，不必考慮積層體S1之高度公差，可將形成之柱狀電極520設得更短。另外，亦可不設置間隔件400。
虛設晶片(連接部)500積層於積層體S1與積層體S2之間。虛設晶片500藉由接著層510與間隔件400及積層體S1接著。虛設晶片500係例如與半導體晶片10、50比較，未設置半導體元件之晶片。虛設晶片500具有用以與半導體晶片10及半導體晶片50連接之電極墊505。
柱狀電極520與虛設晶片500之電極墊505連接，且沿積層方向延伸。柱狀電極520將虛設晶片500與再配線層100電性連接。
半導體晶片200設置於積層體S2上。半導體晶片之電極墊205經由連接柱210與再配線層100電性連接。
圖19係顯示第5實施形態之積層體S1、S2及虛設晶片500之構成之一例之立體圖。
虛設晶片500具有之複數個電極墊505之間隔較半導體晶片10具有之複數個電極墊15之間隔、及半導體晶片50具有之複數個電極墊55之間隔更廣。即，藉由虛設晶片500，可擴大與柱狀電極520連接之電極墊505之墊間距。其結果，可緩解(消除)形成柱狀電極520時之毛細管與柱狀電極520之干涉，且可形成更長之柱狀電極520。
此外，虛設晶片500配置於至積層體S1之距離與至積層體S2之距離大致相等之位置。此外，積層體S1之半導體晶片10之積層數、與積層體S2之半導體晶片10之積層數大致相同。藉此，可以自半導體晶片10至虛設晶片500之配線長度、與自半導體晶片50至虛設晶片500之配線長度大致相等之方式配置虛設晶片500。其結果，可抑制配線長度之不均，且更容易成為等長配線。因此，可將配線之長度設得更適當。
另，積層體S1亦可為1階之半導體晶片10，此外，積層體S2亦可為1階之半導體晶片50。
雖已說明本發明之若干實施形態，但該等實施形態係作為實例而提出，並非意圖限定發明之範圍。該等實施形態可以其他多種形態實施，可於不脫離發明主旨之範圍內，進行多種省略、置換及變更。該等實施形態或其變化與包含於發明之範圍或主旨同樣，包含於申請專利範圍所記述之發明與其均等之範圍內。
[相關申請案之引用] 本申請案基於2021年03月05日申請之先前之日本專利申請案第2021-035733號之優先權之利益，且謀求該利益，將其內容整體以引用之方式包含於本文中。
1:半導體裝置 1a:半導體裝置 1b:半導體裝置 2:支持基板 10:半導體晶片 10a:半導體晶片 10B:第1最下層晶片 10U:第1最上層晶片 15:電極墊 17:引線 20:接著層 30:柱狀電極 30a:柱狀電極 50:半導體晶片 50B:第2最下層晶片 50U:第2最上層晶片 51:半導體晶片 52:間隔件 55:電極墊 57:引線 60:接著層 70:柱狀電極 90:樹脂層 100:再配線層 100a:再配線層 110:電極墊 150:金屬凸塊 155:金屬凸塊 200:半導體晶片 200a:半導體晶片 205:電極墊 210:連接支柱 210a:連接支柱 300:配線基板 310:樹脂層 310a:材料 320:樹脂層 400:間隔件 410:間隔件 420:間隔件 500:虛設晶片 505:電極墊 510:接著層 520:柱狀電極 F10a:第1面 F10b:第2面 F50a:第1面 F50b:第2面 F200a:第1面 F200b:第2面 S1:積層體 S1a:積層體 S1b:積層體 S2:積層體 S2b:積層體 S11:積層體 S12:積層體 S21:積層體 S22:積層體
圖1係顯示第1實施形態之半導體裝置之構成之一例之剖視圖。 圖2A係顯示第1實施形態之半導體裝置之構成之一例之剖視圖。 圖2B係顯示第1實施形態之半導體裝置之構成之一例之俯視圖。 圖3A係顯示第1實施形態之半導體裝置之製造方法之一例之剖視圖。 圖3B係顯示繼圖3A後之半導體裝置之製造方法之一例之剖視圖。 圖3C係顯示繼圖3B後之半導體裝置之製造方法之一例之剖視圖。 圖3D係顯示繼圖3C後之半導體裝置之製造方法之一例之剖視圖。 圖3E係顯示繼圖3D後之半導體裝置之製造方法之一例之剖視圖。 圖4係顯示第1比較例之半導體裝置之構成之一例之剖視圖。 圖5係顯示第2比較例之半導體裝置之構成之一例之剖視圖。 圖6A係顯示第1實施形態之第1變化例之半導體裝置之構成之一例之剖視圖。 圖6B係顯示第1實施形態之第1變化例之半導體裝置之構成之一例之俯視圖。 圖7A係顯示第1實施形態之第2變化例之半導體裝置之構成之一例之剖視圖。 圖7B係顯示第1實施形態之第3變化例之半導體裝置之構成之一例之剖視圖。 圖8A係顯示第1實施形態之第4變化例之半導體裝置之構成之一例之剖視圖。 圖8B係顯示第1實施形態之第5變化例之半導體裝置之構成之一例之剖視圖。 圖9A係顯示第1實施形態之第6變化例之半導體裝置之構成之一例之剖視圖。 圖9B係顯示第1實施形態之第7變化例之半導體裝置之構成之一例之剖視圖。 圖10係顯示第2實施形態之半導體裝置之構成之一例之剖視圖。 圖11係顯示第2實施形態之變化例之半導體裝置之構成之一例之剖視圖。 圖12係顯示第3實施形態之半導體裝置之構成之一例之剖視圖。 圖13A係顯示第3實施形態之半導體裝置之製造方法之一例之剖視圖。 圖13B係顯示繼圖13A後之半導體裝置之製造方法之一例之剖視圖。 圖13C係顯示繼圖13B後之半導體裝置之製造方法之一例之剖視圖。 圖13D係顯示繼圖13C後之半導體裝置之製造方法之一例之剖視圖。 圖14係顯示第4實施形態之半導體裝置之構成之一例之剖視圖。 圖15係顯示第4實施形態之第1變化例之半導體裝置之構成之一例之剖視圖。 圖16係顯示第4實施形態之第2變化例之半導體裝置之構成之一例之剖視圖。 圖17係顯示第4實施形態之第3變化例之半導體裝置之構成之一例之剖視圖。 圖18係顯示第5實施形態之半導體裝置之構成之一例之剖視圖。 圖19係顯示第5實施形態之積層體及虛設晶片之構成之一例之立體圖。
1:半導體裝置 10:半導體晶片 10B:第1最下層晶片 10U:第1最上層晶片 15:電極墊 20:接著層 30:柱狀電極 50:半導體晶片 50B:第2最下層晶片 50U:第2最上層晶片 55:電極墊 60:接著層 70:柱狀電極 90:樹脂層 100:再配線層 110:電極墊 150:金屬凸塊 200:半導體晶片 205:電極墊 210:連接支柱 F10a:第1面 F10b:第2面 F50a:第1面 F50b:第2面 F200a:第1面 F200b:第2面 S1:積層體 S2:積層體

Claims (9)

  1. 一種半導體裝置，其包含：第1積層體，其由複數個第1半導體晶片向垂直於積層方向之方向即第1方向偏移而積層；第1柱狀電極，其與上述第1半導體晶片之電極墊連接，且沿上述第1半導體晶片之積層方向延伸；第2積層體，其由複數個第2半導體晶片向垂直於積層方向之方向即第2方向偏移而積層，且積層為較上述第1積層體高，且，配置為自上述積層方向觀察，與上述第1積層體之至少一部分重疊；第2柱狀電極，其與上述第2半導體晶片之電極墊連接，且沿上述第2半導體晶片之積層方向延伸；第3半導體晶片，其設置於上述第2積層體；第3柱狀電極，其與上述第3半導體晶片之第3電極墊連接，且沿上述第3半導體晶片之積層方向延伸；樹脂，其密封上述第1積層體、上述第2積層體、及上述第3半導體晶片；及配線層，其包含與自上述樹脂露出之上述第1柱狀電極之端部、上述第2柱狀電極及上述第3柱狀電極之端部電性連接之配線，且設置於上述樹脂。
  2. 如請求項1之半導體裝置，其中上述第1方向與上述第2方向為不同之方向； 上述第2積層體之最下層之晶片即第2最下層晶片，設置於上述第1積層體之最上層之晶片即第1最上層晶片之上。
  3. 如請求項2之半導體裝置，其中上述第3半導體晶片自積層方向觀察，與上述第2最下層晶片及上述第1最上層晶片之至少一部分重疊。
  4. 如請求項1之半導體裝置，其中至少1個上述第2半導體晶片較其他上述第2半導體晶片厚，或上述第2積層體具有較上述第2半導體晶片厚之間隔件。
  5. 如請求項1之半導體裝置，其中於上述第1積層體之最上層之晶片即第1最上層晶片之上，設置間隔件；且於上述間隔件上，設置第2積層體之至少一個晶片。
  6. 如請求項1至5中任一項之半導體裝置，其中上述第1柱狀電極至少於每一上述第1半導體晶片設置；且上述第2柱狀電極至少於每一上述第2半導體晶片設置。
  7. 一種半導體裝置之製造方法，其包含如下步驟：於支持基板上，形成第1積層體與第2積層體，該第1積層體係由複數個第1半導體晶片向垂直於積層方向之方向偏移而積層，該第2積層體係由複數個第2半導體晶片向垂直於積層方向之方向偏移而積層，且積層為較上述第1積層體高，且，配置為自上述積層方向觀察，與上述第1積層體之 至少一部分重疊；及形成第1柱狀電極及第2柱狀電極，該第1柱狀電極係與上述第1半導體晶片之電極墊連接且沿上述第1半導體晶片之積層方向延伸，該第2柱狀電極係與上述第2半導體晶片之電極墊連接且沿上述第2半導體晶片之積層方向延伸。
  8. 如請求項7之半導體裝置之製造方法，其進而包含如下步驟：以樹脂層被覆上述第1積層體、上述第2積層體、上述第1柱狀電極及上述第2柱狀電極；研磨上述樹脂層，且使上述第1柱狀電極及上述第2柱狀電極之上端露出；及於上述樹脂層上形成與上述第1柱狀電極及上述第2柱狀電極電性連接之再配線層。
  9. 如請求項7之半導體裝置之製造方法，其進而包含如下步驟：以樹脂層被覆上述第1積層體、上述第2積層體、上述第1柱狀電極及上述第2柱狀電極；研磨上述樹脂層，且使上述第1柱狀電極及上述第2柱狀電極之上端露出；於上述第1柱狀電極及上述第2柱狀電極之上端形成第1連接凸塊；及經由上述第1連接凸塊，使上述第1柱狀電極及上述第2柱狀電極，與配線基板電性連接。
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