TWI835227B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TWI835227B
TWI835227B TW111128373A TW111128373A TWI835227B TW I835227 B TWI835227 B TW I835227B TW 111128373 A TW111128373 A TW 111128373A TW 111128373 A TW111128373 A TW 111128373A TW I835227 B TWI835227 B TW I835227B
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Taiwan
Prior art keywords
metal layer
semiconductor device
columnar electrode
electrode
insulating member
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TW111128373A
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TW202339274A (zh
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正村将利
右田達夫
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日商鎧俠股份有限公司
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Publication of TW202339274A publication Critical patent/TW202339274A/zh
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Abstract

本發明提供一種能提高可靠性之半導體裝置及半導體裝置之製造方法。  本實施方式之半導體裝置具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊之方式配置；及電極，其以被覆上述構件之方式設置於上述第1面上，且與上述柱狀電極電性連接。

Description

半導體裝置及半導體裝置之製造方法
本實施方式係關於一種半導體裝置及半導體裝置之製造方法。
於半導體封裝中，有時會設置電極墊用於電性連接。對於電極墊，期望連接可靠性高。
本發明提供一種能提高可靠性之半導體裝置及半導體裝置之製造方法。
本實施方式之半導體裝置具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊的方式配置；及電極，其以被覆上述構件之方式設置於上述第1面上，且與上述柱狀電極電性連接。
1:半導體裝置
10:半導體晶片
15:電極墊
20:接著層
30:柱狀電極
31:柱狀電極構件
32:金屬層
33:凹部
34:上端部
90:樹脂層
91:樹脂層
92:樹脂層
100:配線基板
150:金屬凸塊
160:金屬凸塊
170:電極墊
171:金屬層
172:金屬層
180:構件
200:半導體晶片
210:金屬凸塊
220:底部填充膠
230:接著劑
311:端部
C:觸媒
F10a:第1面
F10b:第2面
F91:面
F200a:第1面
F200b:第2面
S1:積層體
圖1係表示第1實施方式之半導體裝置之構成之一例的剖視圖。
圖2係表示第1實施方式之電極墊及柱狀電極之構成之一例的圖。
圖3A係表示第1實施方式之半導體裝置之製造方法之一例的圖。
圖3B係表示繼圖3A之後的半導體裝置之製造方法之一例之圖。
圖3C係表示繼圖3B之後的半導體裝置之製造方法之一例之圖。
圖3D係表示繼圖3C之後的半導體裝置之製造方法之一例之圖。
圖3E係表示繼圖3D之後的半導體裝置之製造方法之一例之圖。
圖4係表示第2實施方式之半導體裝置之構成之一例的圖。
以下，參照圖式對本發明之實施方式進行說明。本實施方式並不限定本發明。圖式係模式性或概念性圖，各部分之比率等未必與實物相同。於說明書及圖式中，對與上文中關於已示出之圖式所敍述之要素相同的要素標註相同之符號，並適當省略詳細之說明。
(第1實施方式)
圖1係表示第1實施方式之半導體裝置1之構成之一例的剖視圖。半導體裝置1具備積層體S1、柱狀電極30、金屬凸塊160、電極墊170、樹脂層90、半導體晶片200、金屬凸塊210、底部填充膠220、接著劑230、配線基板100及金屬凸塊150。半導體裝置1例如可為NAND(Not-And，反及)型快閃記憶體、LSI(Large Scale Integration，大規模積體電路)等半導體封裝。
積層體S1設置於配線基板100之上方。積層體S1具有半導體晶片10及接著層20。接著層20例如為DAF(Die Attachment Film，晶粒接著膜)。積層體S1係複數個半導體晶片10向與積層方向垂直之方向錯開 地積層而成之積層體。
複數個半導體晶片10分別具有第1面F10a、及與第1面F10a為相反側之第2面F10b。記憶胞陣列、電晶體或電容器等半導體元件(未圖示)形成於各半導體晶片10之第1面F10a上。半導體晶片10之第1面F10a上之半導體元件由未圖示之絕緣膜被覆而加以保護。該絕緣膜例如使用氧化矽膜或氮化矽膜等無機系絕緣材料。又，該絕緣膜亦可使用於無機系絕緣材料上形成有機系絕緣材料而成之材料。作為有機系絕緣材料，例如使用酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole，聚對伸苯基苯雙
Figure 111128373-A0305-02-0005-1
唑)系樹脂、矽酮系樹脂、苯并環丁烯系樹脂等樹脂、或該等之混合材料、複合材料等有機系絕緣材料。半導體晶片10例如可為NAND型快閃記憶體之記憶體晶片或搭載有任意LSI之半導體晶片。半導體晶片10可為彼此具有相同構成之半導體晶片，亦可為彼此具有不同構成之半導體晶片。
複數個半導體晶片10積層，藉由接著層20而接著。作為接著層20，例如使用酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽酮系樹脂、苯并環丁烯系樹脂等樹脂、或該等之混合材料、複合材料等有機系絕緣材料。複數個半導體晶片10分別具有於第1面F10a上露出之電極墊15。於半導體晶片10(上層半導體晶片10)之下積層之其他半導體晶片10(下層半導體晶片10)係以不重疊於上層半導體晶片10之電極墊15上之方式，相對於上層半導體晶片10之設置有電極墊15之邊沿大致垂直方向(X方向)錯開而積層。
電極墊15與設置於半導體晶片10之任一半導體元件電性連 接。電極墊15例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al、Ti、Ta、TiN、TaN、CrN等單一成分、其等中之2種以上之複合膜、或其等中之2種以上之合金等低電阻金屬。
柱狀電極30連接於半導體晶片10之電極墊15，於複數個半導體晶片10之積層方向(Z方向)上延伸。接著層20被局部去除以使電極墊15之一部分露出，從而使柱狀電極30能夠連接於電極墊15。或者，接著層20貼附於下層半導體晶片10之第2面F10b，且以不與上層半導體晶片10之電極墊15重疊之方式設置。柱狀電極30之上端例如藉由打線接合法而與電極墊15連接。柱狀電極30之下端到達樹脂層91之下表面，並於該下表面露出。柱狀電極30之下端與配線基板100之電極墊(未圖示)連接。柱狀電極30之材料例如使用Au、Cu、Ag、Pd、Pt等導電性金屬、或至少包含其中一種之合金。
金屬凸塊160設置於配線基板100之電極墊(未圖示)上。金屬凸塊160例如使用Sn、Ag、Cu、Au、Pd、Bi、Zn、Ni、Sb、In、Ge之單質、其等中之2種以上之複合膜、或合金。
電極墊170設置於樹脂層91之下表面。電極墊170係與柱狀電極30電性連接。電極墊170將柱狀電極30與金屬凸塊160電性連接。再者，關於電極墊170與柱狀電極30之連接之細節，將參照圖2於下文中進行說明。
樹脂層90被覆(密封)積層體S1、柱狀電極30及金屬凸塊160等。
樹脂層90例如使用酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole) 系樹脂、矽酮系樹脂、苯并環丁烯系樹脂等樹脂、或該等之混合材料、複合材料等有機系絕緣材料。
樹脂層90具有樹脂層91、92。
樹脂層91具有與配線基板100對向之面F91。樹脂層91被覆積層體S1及柱狀電極30。於樹脂層91之下表面即面F91設置有與柱狀電極30之下端連接之電極墊170。
樹脂層92以填充樹脂層91與配線基板100之間之方式設置，且以被覆樹脂層91之方式設置。
樹脂層91與樹脂層92之間材料或特性可相同。又，樹脂層91與樹脂層92之間材料或特性亦可不同。樹脂層91與樹脂層92之間，例如硬化收縮率、彈性模量、線膨脹係數、及玻璃轉移溫度(Tg)中之至少1個不同。樹脂層91、樹脂層92可使用所謂之塑模樹脂。塑模樹脂係於樹脂層中混合有無機絕緣物之填料。樹脂層91與樹脂層92中，填料與樹脂之混合率、填料之材質、填料之形狀、填料之直徑等可不同。
半導體晶片200具有第1面F200a、及與第1面F200a為相反側之第2面F200b。電晶體或電容器等半導體元件(未圖示)形成於各半導體晶片200之第1面F200a上。半導體晶片200之第1面F200a上之半導體元件由未圖示之絕緣膜被覆而加以保護。該絕緣膜例如使用氧化矽膜或氮化矽膜等無機系絕緣材料。又，該絕緣膜亦可使用於無機系絕緣材料上形成有機系絕緣材料而成之材料。作為有機系絕緣材料，例如使用酚系樹脂、聚醯亞胺系樹脂、聚醯胺系樹脂、丙烯酸系樹脂、環氧系樹脂、PBO(p-phenylenebenzobisoxazole)系樹脂、矽酮系樹脂、苯并環丁烯系樹脂等樹脂、或該等之混合材料、複合材料等有機系絕緣材料。半導體晶片200例 如可為控制記憶體晶片(半導體晶片10)之控制器晶片或搭載有任意LSI之半導體晶片。
半導體晶片200設置於配線基板100上。半導體晶片200於第1面F200a上具有金屬凸塊210。
金屬凸塊210與半導體晶片200之電極墊(未圖示)連接。金屬凸塊210與配線基板100之電極墊(未圖示)連接。
底部填充膠220係以填充半導體晶片200與配線基板100之間之方式設置，被覆金屬凸塊210之周圍而加以保護。
接著劑230設置於樹脂層91與半導體晶片200之間。
配線基板100係包含配線層與絕緣層之多層基板。絕緣層例如為預浸體。絕緣層例如為玻璃布等纖維狀補強材與環氧樹脂等熱固性樹脂之複合材料。
金屬凸塊150設置於配線基板100之下，電性連接於配線基板100之配線層。金屬凸塊150用於與外部裝置(未圖示)之連接。金屬凸塊150例如使用Sn、Ag、Cu、Au、Pd、Bi、Zn、Ni、Sb、In、Ge之單質、其等中之2種以上之複合膜、或合金。
其次，對電極墊170與柱狀電極30之連接之細節進行說明。又，以下，將-Z方向設為上方向。
圖2係表示第1實施方式之電極墊170及柱狀電極30之構成之一例的圖。圖2之左側係將圖1所示之虛線框D內之電極墊170及其周邊放大所得之剖視圖。再者，圖2之剖視圖係由圖1上下反轉來表示。圖2之右側係表示從-Z方向觀察時之電極墊170之周邊之俯視圖。再者，於圖2之俯視圖中，省略了電極墊170及金屬層171、172。又，圖2之剖視圖係 對應於圖2之俯視圖之沿A-A線之剖面的剖視圖。
柱狀電極(導線)30於面F91之周邊，沿著與面F91大致垂直之方向(Z方向)貫通樹脂層91。從與面F91大致垂直之方向觀察時，柱狀電極30之外周部從面F91露出。又，柱狀電極30於上端部具有凹部33。即，柱狀電極30於從大致垂直於面F91之方向觀察時之柱狀電極30之中心部，具有從面F91凹陷之凹部33。凹部33之深度例如為約5μm。再者，柱狀電極30之外周部對應於下文進行說明之金屬層32。又，柱狀電極30之中心部對應於下文進行說明之柱狀電極構件31。
柱狀電極30具有柱狀電極構件31及金屬層32。柱狀電極30之凹部33具有作為金屬層32之側面部、及作為柱狀電極構件31之底部。
柱狀電極構件(導線構件)31於樹脂層91之內部具有端部311。即，柱狀電極構件31於樹脂層91之內部終止。柱狀電極構件31之材料例如使用Au、Cu、Ag、Pd、Pt、Ni等導電性金屬、或至少包含其中一種之合金。以下，對使用Cu作為柱狀電極構件31之材料之情形進行說明。
電極墊170以與柱狀電極構件31電性連接之方式於凹部33之內部延伸。因此，柱狀電極構件31與電極墊170之交界位於樹脂層91之內部。電極墊170之材料例如使用Ni、Cu等。以下，對使用Ni作為電極墊170之材料之情形進行說明。
金屬層(第1金屬層)32被覆柱狀電極構件31之外周。再者，柱狀電極構件31之外周係從柱狀電極構件31之延伸方向(Z方向)觀察時之外周。金屬層32沿-Z方向延伸，直至從面F91露出。金屬層32保護柱狀電極構件31使其不被氧化等。藉此，能夠容易地處理柱狀電極構件 31。金屬層32之材料例如使用Pd、Au、Ag、Pt等貴金屬。以下，對使用Pd作為金屬層32之材料之情形進行說明。
此處，如上所述，電極墊170延伸至藉由柱狀電極構件31凹陷而設置之凹部33之內部。藉此，能夠利用投錨效應提高電極墊170之強度。結果能夠提高電極墊170之連接可靠性。又，如下文所說明，藉由形成凹部33來去除柱狀電極構件31之研削條痕及加工影響區域，亦能提高電極墊170之強度。
但是，若設置凹部33，則金屬層32變得不穩定，金屬層32有可能發生剝離而倒向凹部33內。
因此，半導體裝置1進而具備構件180。構件180係為了固定金屬層32而設置。
構件180設置於面F91上。構件180以從大致垂直於面F91之方向觀察時，與柱狀電極30之外周部之至少一部分重疊的方式配置。更詳細而言，構件180以從大致垂直於面F91之方向觀察時，與從面F91露出之金屬層32之至少一部分重疊的方式配置。於圖2之俯視圖所示之例中，構件180例如呈大致環狀配置。
又，構件180以從大致垂直於面F91之方向觀察時，不與柱狀電極30之至少一部分重疊之方式配置。即，構件180以不完全蓋住柱狀電極30之方式配置。
構件180之材料例如使用Ni、Co、Au、Ag、Pd、Rh、Pt、In、Sn等金屬、或其等中之2種以上之合金。構件180之材料較佳為與柱狀電極構件31之材料不同，以使其於參照圖3C在下文進行說明之步驟中，不會因對柱狀電極構件31進行之蝕刻而被去除。以下，對將Ni用作 構件180之材料之情形進行說明。
又，構件180之材料例如亦可使用PI(Polyimide，聚醯亞胺)等有機物。例如，可使用感光性PI，藉由光微影法而形成構件180。
電極墊170以被覆構件180之方式設置於面F91上。
半導體裝置1進而具備被覆電極墊170之至少1層金屬層。更詳細而言，半導體裝置1進而具備金屬層171、172。
金屬層171、172之材料例如使用Au、Pd等貴金屬。藉此，能夠保護電極墊170。以下，對使用Pd作為金屬層171之材料，且使用Au作為金屬層172之材料之情形進行說明。
再者，金屬層171、172之材料例如亦可使用In、Sn等低熔點金屬。藉此，能夠容易地將電極墊170與金屬凸塊160連接。
其次，對電極墊170及構件180之形成方法進行說明。
圖3A~3E係表示第1實施方式之半導體裝置1之製造方法之一例的圖。圖3A~圖3E之左側與圖2之左側同樣地表示剖視圖。圖3A~圖3D之右側與圖2之右側同樣地表示俯視圖。
首先，如圖3A所示，形成具有柱狀電極構件31及金屬層32之柱狀電極30，形成被覆柱狀電極30之樹脂層91，對樹脂層91進行研磨以使柱狀電極30之上端部34從面F91露出。對樹脂層91之研磨例如藉由機械研磨來進行，但亦可藉由CMP(Chemical Mechanical Polishing，化學機械拋光)等來進行。
其次，如圖3B所示，於面F91上形成構件180。構件180以從大致垂直於面F91之方向觀察時，與從面F91露出之金屬層32之至少一部分重疊的方式形成。構件180例如藉由無電解電鍍法而形成。
構件180中之Ni例如藉由以金屬層32中之Pd為觸媒之無電解電鍍而析出。其後，以析出之Ni為自體觸媒而使Ni析出。藉此，從與面F91大致垂直之方向觀察時，構件180形成於整個金屬層32之位置。於圖3B之俯視圖所示之例中，構件180例如形成為大致環狀。
其次，如圖3C所示，去除柱狀電極構件31之一部分，而形成凹部33。更詳細而言，藉由從面F91側去除柱狀電極構件31之一部分，而於柱狀電極30之上端部34形成具有作為金屬層32之側面、及作為柱狀電極構件31之底部的凹部33。凹部33例如藉由蝕刻而形成。凹部33之底部為柱狀電極構件31之端部311。
其次，如圖3D所示，於凹部33之底部、即柱狀電極構件31之端部311上添加觸媒C。觸媒C吸附於端部311之上表面。觸媒C例如為Pd觸媒。
其次，如圖3E所示，於凹部33之內部、及構件180上形成與柱狀電極30電性連接之電極墊170。又，形成被覆電極墊170之金屬層171，並形成被覆金屬層171之金屬層172。電極墊170及金屬層171、172例如藉由無電解電鍍而形成。電極墊170中之Ni係以構件180中之Ni為自體觸媒而析出，且以金屬層32及觸媒C中之Pd為觸媒而析出。
其次，對藉由形成凹部33來提高電極墊170之強度之情況進行說明。
於圖3A所示之步驟中，於柱狀電極30之上端部34之表面形成研削條痕所致之凹凸。用以形成電極墊170之觸媒C容易吸附於研削條痕之凸部。該情形時，於形成電極墊170時，可能會於研削條痕之凹部(柱狀電極構件31與電極墊170之界面)產生大量之較小之孔隙。孔隙會導致電 極墊170之連接可靠性降低。藉由於圖3C所示之步驟中形成凹部33，而去除研削條痕所致之凹凸，從而露出凹凸相對較少之端部311之表面。藉此，能夠改善柱狀電極構件31與電極墊170之界面之狀態，從而能夠提高電極墊170之連接可靠性。
又，於圖3A所示之步驟中，於柱狀電極30之上端部34例如會形成厚度為數μm左右之加工影響區域。加工影響區域係結晶變小、或結晶產生應變之區域。結晶之應變等會使蝕刻速率增大。因此，於加工影響區域中，圖3C所示之對柱狀電極構件31之蝕刻無法均勻地進行，容易於柱狀電極構件31之表面產生凹凸。於此情形時，有可能會於柱狀電極構件31與電極墊170之界面產生大量之較小之孔隙。孔隙會導致電極墊170之連接可靠性降低。因此，藉由使蝕刻進行至結晶應變較少之區域而形成凹部33，從而將加工影響區域全部去除，露出凹凸相對較少之端部311之表面。藉此，能夠改善柱狀電極構件31與電極墊170之界面之狀態，從而能夠提高電極墊170之連接可靠性。
藉由形成凹部33，除了獲得投錨效應以外，還去除了研削條痕及加工影響區域，從而能夠提高電極墊170之強度。藉此，能夠提高電極墊170之連接可靠性。
如上所述，根據第1實施方式，構件180設置於面F91上，且以從大致垂直於面F91之方向觀察時，與從面F91露出之金屬層32之至少一部分重疊之方式配置。能夠利用構件180來固定金屬層32，能夠抑制金屬層32於凹部33之內部剝離。藉此，能夠提高電極墊170之連接可靠性。
又，於第1實施方式中，電極墊170以與柱狀電極構件31電 性連接之方式延伸至凹部33之內部。藉由投錨效應、以及柱狀電極構件31之研削條痕及加工影響區域之去除，能夠提高電極墊170之強度。藉此，能夠提高電極墊170之連接可靠性。
又，於圖2所示之例中，示出了1層金屬層32。金屬層32設置至少1層即可。因此，亦可設置2層以上之金屬層32。
如上所述，樹脂層91例如為包含填料之有機物。樹脂層91之有機物例如為塑模樹脂、環氧樹脂、或PI等。但是，作為絕緣構件之樹脂層91例如亦可為SiO2等無機物。又，樹脂層(絕緣構件)91亦可具有材料或特性不同之複數個樹脂層(複數個絕緣構件)。藉此，能夠抑制半導體裝置1之封裝翹曲。複數個絕緣構件例如硬化收縮率、彈性模量、線膨脹係數、及玻璃轉移溫度(Tg)中之至少1個不同。又，樹脂層91可使用所謂之塑模樹脂。塑模樹脂係於樹脂層中混合有無機絕緣物之填料。關於樹脂層91所具有之複數個樹脂層，填料與樹脂之混合率、填料之材質、填料之形狀、填料之直徑等可不同。
(第2實施方式)
圖4係表示第2實施方式之半導體裝置1之製造方法之一例的圖。第2實施方式與第1實施方式相比，構件180之形成方法不同。
於使柱狀電極30之上端部34露出後(參照圖3A)，如圖4所示，於面F91上形成構件180。構件180例如藉由噴墨法而形成。於此情形時，構件180可逐個位置地形成，亦可一次形成於複數個位置。再者，構件180並不限定於第1實施方式中之無電解電鍍法、或第2實施方式中之噴墨法，例如亦可藉由印刷法等其他方法來形成。
其後，進行與圖3C~圖3E所示之步驟相同之步驟。
再者，構件180可不必以與整個金屬層32(大致環狀)重疊之方式配置。為了能夠抑制金屬層32之剝離，構件180亦可以從大致垂直於面F91之方向觀察時，與從面F91露出之金屬層32之一部分重疊的方式配置。
亦可如第2實施方式般，變更構件180之形成方法。第2實施方式之半導體裝置1能夠獲得與第1實施方式相同之效果。
雖然對本發明之若干實施方式進行了說明，但該等實施方式係作為示例而提出者，並不意圖限定發明之範圍。該等實施方式能夠以其他各種方式實施，能夠於不脫離發明之主旨之範圍內，進行各種省略、替換、變更。該等實施方式及其變化包含於發明之範圍或主旨內，亦同樣地包含於申請專利範圍中記載之發明及其均等之範圍內。
[相關申請]
本申請享有以日本專利申請2022-041598號(申請日:2022年3月16日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
30:柱狀電極
31:柱狀電極構件
32:金屬層
33:凹部
91:樹脂層
170:電極墊
171:金屬層
172:金屬層
180:構件
311:端部
F91:面

Claims (15)

  1. 一種半導體裝置，其具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊之方式配置；及電極墊，其以被覆上述構件之方式設置於上述第1面上，與上述柱狀電極電性連接；其中從上述第1方向觀察時，上述構件為環狀。
  2. 一種半導體裝置，其具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊之方式配置；及電極墊，其以被覆上述構件之方式設置於上述第1面上，與上述柱狀 電極電性連接；其中上述構件之材料與上述柱狀電極之材料不同。
  3. 一種半導體裝置，其具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊之方式配置；及電極墊，其以被覆上述構件之方式設置於上述第1面上，與上述柱狀電極電性連接；其中進而具備被覆上述電極墊之至少1層第3金屬層。
  4. 一種半導體裝置，其具備：絕緣構件，其具有第1面；柱狀電極，其具有至少1層第1金屬層、及第2金屬層，上述至少1層第1金屬層沿與上述第1面大致垂直之方向延伸至上述絕緣構件中，且至少一部分從上述絕緣構件由上述第1面露出，上述第2金屬層之至少一部分從上述絕緣構件露出，且設置於上述第1金屬層之內側；構件，其設置於上述第1面上，且以從大致垂直於上述第1面之第1方向觀察時，與上述第1金屬層之至少一部分重疊之方式配置；及 電極墊，其以被覆上述構件之方式設置於上述第1面上，與上述柱狀電極電性連接；其中上述電極墊係藉由鍍覆而形成。
  5. 如請求項1至4中任一項之半導體裝置，其中上述第1金屬層之上端部較上述第2金屬層之上端部更靠近上述第1面，上述電極墊與上述第2金屬層電性連接。
  6. 如請求項1至4中任一項之半導體裝置，其中從上述第1方向觀察時，上述第1金屬層為環狀。
  7. 如請求項1至4中任一項之半導體裝置，其中上述構件以從上述第1方向觀察時，不與上述柱狀電極之至少一部分重疊之方式配置。
  8. 如請求項1至4中任一項之半導體裝置，其中上述構件之材料使用金屬或有機物。
  9. 如請求項1之半導體裝置，其中作為上述構件之材料之金屬包括Ni、Co、Au、Ag、Pd、Rh、Pt、In、Sn，作為上述構件之材料之有機物包括PI。
  10. 如請求項1至4中任一項之半導體裝置，其中上述絕緣構件使用包含填料之有機物、或無機物。
  11. 如請求項1至4中任一項之半導體裝置，其中上述第1金屬層之材料使用貴金屬。
  12. 如請求項11之半導體裝置，其中上述貴金屬為Pd。
  13. 一種半導體裝置之製造方法，其包括如下步驟：形成具有第1金屬層、及形成於上述第1金屬層內部之第2金屬層之柱狀電極；形成被覆上述柱狀電極之絕緣構件，削除上述絕緣構件，以使上述柱狀電極之上端部從上述絕緣構件之第1面露出；以從大致垂直於上述第1面之第1方向觀察時，與從上述第1面露出之上述第1金屬層之至少一部分重疊之方式，於上述第1面上形成構件；從上述第1面側去除上述第2金屬層之一部分，以使上述第1金屬層之上端部較上述第2金屬層之上端部更靠近上述第1面；及於上述柱狀電極之上部側形成電極墊。
  14. 如請求項13之半導體裝置之製造方法，其進而包括如下步驟：藉由無電解電鍍法、印刷法、或噴墨法而於上述第1面上形成上述構件。
  15. 如請求項13之半導體裝置之製造方法，其中上述電極墊係藉由鍍覆而形成。
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TW202203393A (zh) * 2020-07-07 2022-01-16 日商鎧俠股份有限公司 半導體裝置及半導體裝置之製造方法

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