TW201349428A - 提供具互連堆疊器件晶圓之積體電路系統之方法及裝置 - Google Patents

提供具互連堆疊器件晶圓之積體電路系統之方法及裝置 Download PDF

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TW201349428A
TW201349428A TW102112222A TW102112222A TW201349428A TW 201349428 A TW201349428 A TW 201349428A TW 102112222 A TW102112222 A TW 102112222A TW 102112222 A TW102112222 A TW 102112222A TW 201349428 A TW201349428 A TW 201349428A
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Taiwan
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conductor
metal layer
device wafer
cavity
oxide
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TW102112222A
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Yin Qian
Hsin-Chih Tai
Duli Mao
Tie-Jun Dai
Howard E Rhodes
Hong-Li Yang
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Omnivision Tech Inc
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Publication of TW201349428A publication Critical patent/TW201349428A/zh

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Abstract

本發明係關於一種積體電路系統，其包含一第一器件晶圓，其具有一第一半導體層，該第一半導體層接近安置於一第一金屬層氧化物內之包含一第一導體之一第一金屬層。亦包含一第二器件晶圓，其具有一第二半導體層，該第二半導體層接近安置於一第二金屬層氧化物內之包含一第二導體之一第二金屬層。該第一金屬層氧化物之一前側在該第一金屬層氧化物與該第二金屬層氧化物之間之氧化物接合介面處接合至該第二金屬層氧化物之一前側。一導電路徑藉由形成於一腔內之導電材料將該第一導體耦合至該第二導體，該腔係蝕刻在該第一導體與該第二導體之間，且自該第二器件晶圓之一背側蝕刻穿過該氧化物接合介面及穿過該第二半導體層。

Description

提供具互連堆疊器件晶圓之積體電路系統之方法及裝置
本發明大體上係關於半導體處理。更明確而言，本發明之實施例係關於堆疊積體電路系統之半導體處理。
隨著積體電路技術的持續發展，吾人持續努力來增加性能及密度、改良外形因數及降低成本。堆疊三維積體電路之實施方案已經成為設計者有時用於實現此等益處之一個途徑。其中三維積體電路係一適當考慮之一些實例包含：在影像感測器或處理器晶片之頂部上堆疊記憶體、在處理器晶片之頂部上堆疊記憶體、在影像感測器之頂部上堆疊處理器晶片、堆疊用不同製程製造的晶片、堆疊兩個小積體電路晶片(其單獨的產量可高於一大積體電路晶片的產量)、或堆疊晶片以減少積體電路系統佔據面積。
實施堆疊三維積體電路之一關鍵挑戰是如何以高產量及穩定性實現積體電路晶片之間之許多小面積互連。舉例而言，堆疊積體電路晶片之間之典型銅至銅接合經常遭受晶圓扭曲以及彎曲。此外，當嘗試提供積體電路晶片之間之連接時，銅表面粗糙性及不平坦性成為額外挑戰。用於製造堆疊積體電路晶片之間之許多小面積互連的其他已知技術亦係較昂貴、不可靠且大型的。
101‧‧‧積體電路系統
103‧‧‧第一器件晶圓
105‧‧‧第一半導體層
107‧‧‧第一金屬層氧化物
109‧‧‧第一導體
111‧‧‧第一器件晶圓之前側/第一金屬層氧化物之前側
113‧‧‧第一器件晶圓之背側
203‧‧‧第二器件晶圓
205‧‧‧第二半導體層
207‧‧‧第二金屬層氧化物
209‧‧‧第二導體
211‧‧‧第二器件晶圓之前側/第二金屬層氧化物之前側
213‧‧‧第二器件晶圓之背側/第二半導體層之背側
315‧‧‧接合介面
417‧‧‧鈍化層
519‧‧‧開口
521‧‧‧氧化物沈積
623‧‧‧溝槽
725‧‧‧腔
827‧‧‧腔
829‧‧‧環形孔
931‧‧‧障壁金屬沈積
1033‧‧‧導電材料
1035‧‧‧導電路徑
1137‧‧‧線接合腔
1139‧‧‧線接合
參考以下圖描述本發明之非限制及非詳盡實施例，其中相同參考數字在各視圖中始終指代相同部件，除非另有指定。
圖1係繪示根據本發明之教示之可包含在一實例積體電路系統中之第一及第二器件晶圓之一個實例之一橫截面圖。
圖2係繪示根據本發明之教示之在一實例積體電路系統中經堆疊及接合在一起之第一及第二器件晶圓之一個實例之一橫截面圖。
圖3係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中該等晶圓之一者具有一經薄化及鈍化之半導體層。
圖4係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中氧化物沈積在穿過半導體層之一者之一蝕刻開口上。
圖5A係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中用一第一遮罩在一開口中穿過半導體層之一者蝕刻抵達一導體之一溝槽。
圖5B係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中在溝槽中用一第二遮罩在第一與第二導體之間蝕刻一腔且使該腔自該等器件晶圓之一者之一背側蝕刻穿過一接合介面及穿過半導體層之一者。
圖6A係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之另一實例之一橫截面圖，其中用一第一遮罩在第一與第二導體之間蝕刻一腔且使該腔自該等器件晶圓之一者之一背側蝕刻穿過一接合介面及穿過半導體層之一者。
圖6B係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之另一實例之一橫截面圖，其中用一第二遮罩在一開口中穿過半導體層之一者在腔之上方蝕刻抵達一導體之一溝槽。
圖7係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之又一實例之一橫截面圖，其中用一單一遮罩在第一與第二導體之間蝕刻一腔且使該腔自該等器件晶圓之一者之一背側蝕刻穿過該等導體之一者中之一環形孔、穿過一接合介面及穿過半導體層之一者。
圖8係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中一障壁金屬沈積在背側上且自該等器件晶圓之一者之一背側在第一與第二導體之間蝕刻一腔。
圖9係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中自該等器件晶圓之一者之一背側在第一與第二導體之間蝕刻的一腔係用導電材料填充以在第一與第二導體之間提供一導電路徑。
圖10係繪示根據本發明之教示之在一實例積體電路系統中之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖，其中在第一與第二導體之間提供導電路徑之導電材料被蝕刻及拋光。
圖11係繪示根據本發明之教示之在一實例積體電路系統中之具有一線接合腔及線接合之經堆疊及接合之第一及第二器件晶圓之一個實例之一橫截面圖。
如將展示，本發明揭示提供具有堆疊積體電路器件晶圓之一積體電路系統之一方法及裝置的實例，該等堆疊積體電路器件晶圓使用 在各自金屬層氧化物中之導體之間穿過一接合介面之一個或多個導電路徑。在下文描述中，陳述許多特定細節以提供對本發明之徹底理解。然而，一般技術者顯將理解不需要利用該特定細節來實踐本發明。在其他案例中，未詳細描述眾所周知的材料或方法以避免使本發明難理解。
貫穿本說明書，對「一個實施例」、「一實施例」、「一個實例」或「一實例」之參考意指結合該實施例或實例來描述之一特定特徵、結構或特性被包含在本發明之至少一個實施例中。因此，在貫穿本說明書之各種地方出現片語「在一個實施例中」、「在一實施例中」、「一個實例」或「一實例」並不一定都指同一實施例或實例。此外，特定特徵、結構或特性可以任何適當的組合及/或次組合而組合在一個或多個實施例或實例中。特定特徵、結構或特性可被包含在一積體電路、一電子電路、一組合邏輯電路或其他提供所描述之功能性的適當組件中。另外，應瞭解，一併提供之圖係出於向一般技術者解釋之目的，且圖式不必按比例繪製。
為了繪示說明，圖1係繪示根據本發明之教示之包含在一積體電路系統101之一個實例中之一第一器件晶圓103及一第二器件晶圓203之一個實例之一橫截面圖。在一個實例中，第一器件晶圓103及第二器件晶圓203之一者可為一成像器晶片、一特定應用積體電路或類似物，且第一器件晶圓103及第二器件晶圓203之另一者可為一處理晶片、一特定應用積體電路或類似物。
如該實例中所示，第一器件晶圓103包含一第一半導體層105，第一半導體層105接近安置於一第一金屬層氧化物107內之包含一第一導體109之一第一金屬層。在所描繪的實例中，第一金屬層氧化物107接近第一器件晶圓103之一前側111且第一半導體層105接近第一器件晶圓103之一背側113。在一個實例中，第一半導體層105包含矽。
繼續圖1中所描繪之實例，第二器件晶圓203包含一第二半導體層205，第二半導體層205接近安置於一第二金屬層氧化物207內之包含一第二導體209之一第二金屬層。在所描繪的實例中，第二金屬層氧化物207接近第二器件晶圓203之一前側211且第二半導體層205接近第二器件晶圓203之一背側213。在一個實例中，第二半導體層205包含矽。
在一個實例中，第一金屬層氧化物107之前側111與第二金屬層氧化物207之前側211之至少一者係藉由一化學機械拋光而平整化。
圖2係繪示第一器件晶圓103接合至第二器件晶圓203之積體電路系統101之一橫截面圖。如所描繪之實例中所示，根據本發明之教示，第一器件晶圓103之第一金屬層氧化物107之前側111係在第一金屬層氧化物107與第二金屬層氧化物207之間之一接合介面315處接合至第二器件晶圓203之第二金屬層氧化物207之前側211。
在圖2中繪示之實例中，應注意，包含在第一金屬層氧化物107內之第一金屬層之第一導體109之所有導體被繪示為在第一器件晶圓103之前側111表面的下方。類似地，應注意，包含在第二金屬層氧化物207內之第二金屬層之第二導體209之所有導體被繪示為在第二器件晶圓203之前側211表面的下方。因此，在所描繪的實例中，接合介面315包含在第一金屬層氧化物107與第二金屬層氧化物207之間之氧化物至氧化物接合。在另一個實例中，應瞭解，若金屬層之一者包含與前側111或前側211之表面齊平之導體，則接合介面315可為氧化物至導體介面。然而，在任一實例中，根據本發明之教示，在接合介面315處之表面之至少一者包含第一金屬層氧化物107及/或第二金屬層氧化物207之氧化物。因此，在一個實例中，根據本發明之教示，接合介面315係氧化物接合介面。
圖3係繪示積體電路系統101之一實例之一橫截面圖，其具有如 上討論之經堆疊及接合之第一器件晶圓103及第二器件晶圓203，且第二器件晶圓203具有一經薄化第二半導體層205。在一個實例中，根據本發明之教示，在如所繪示自背側213將第二半導體層205薄化之後，接著如所示般鈍化第二半導體層205以在經薄化之第二半導體層205上形成一鈍化層417。
圖4係繪示具有經堆疊及接合之第一器件晶圓103及第二器件晶圓203且第二半導體層205如上討論般經薄化及鈍化之積體電路系統101之一實例之一橫截面圖。另外，圖4中所描繪的實例展示自第二器件晶圓203之背側213蝕刻穿過第二半導體層205之一開口519。在一個實例中，如所示，開口519係自背側213蝕刻穿過第二半導體層205抵達第二金屬層氧化物207。
繼續所繪示之實例，圖4亦展示在開口519經蝕刻穿過第二半導體層205抵達第二金屬層氧化物207之後，如所示，在背側213上及在第二器件晶圓203之開口519上方沈積氧化物沈積521。
圖5A係繪示如上面在圖1至圖4中討論之積體電路系統101之一實例之一個實例之一橫截面圖，其中穿過第二半導體層205之蝕刻開口519用氧化物沈積521覆蓋。另外，圖5A繪示一實例，其中如所示，然後自背側213在開口519中蝕刻一溝槽623使其穿過氧化物沈積521並穿過第二金屬層氧化物207而抵達第二導體209。在一個實例中，溝槽623係使用一第一遮罩自背側213如描述般而蝕刻。
圖5B自上文在圖5A中所描繪的實例繼續，其中自背側213在開口519中蝕刻溝槽623使其穿過氧化物沈積521並穿過第二金屬層氧化物207而抵達第二導體209。在圖5B中所描繪的實例中，根據本發明之教示，如所示，然後自第二半導體層205之背側213蝕刻一腔725使其穿過溝槽623並穿過接合介面315而抵達第一金屬層氧化物107內之第一導體109。在一個實例中，腔725係使用一第二遮罩自背側213如描 述般而蝕刻。
圖6A係繪示如上面在圖1至圖4中討論之積體電路系統101之一實例之另一實例之一橫截面圖，其中穿過第二半導體層205之蝕刻開口519用氧化物沈積521覆蓋。另外，圖6A繪示一實例，其中如所示，自背側213在開口519中蝕刻腔725使其穿過氧化物沈積521、穿過第二金屬層氧化物207並穿過接合介面315而抵達第一金屬層氧化物107內之第一導體109。在一個實例中，腔725係使用一第一遮罩自背側213如描述般而蝕刻。
圖6B自上文在圖6A中所描繪的實例繼續，其中自背側213在開口519中蝕刻腔725使其穿過氧化物沈積521並穿過第二金屬層氧化物207而抵達第一金屬層氧化物107內之第一導體109。在圖6B中所描繪的實例中，根據本發明之教示，如所示，然後在腔725上方自背側213蝕刻溝槽623使其穿過氧化物沈積521並穿過第二金屬層氧化物207而抵達第二導體209。在一個實例中，溝槽623係使用一第二遮罩自背側213如描述般而蝕刻。
圖7係繪示如上面在圖1至圖4中討論之積體電路系統101之一實例之又一實例之一橫截面圖，其中穿過第二半導體層205之蝕刻開口519用氧化物沈積521覆蓋。另外，圖7繪示一實例，其中第二導體209包含一環形孔829或可穿過其蝕刻一腔之其他適當開口。舉例而言，在圖7所描繪的實例中，如所示，自背側213在開口519中蝕刻一腔827使其穿過氧化物沈積521、穿過第二金屬層氧化物207、穿過第二導體209之環形孔829並穿過接合介面315而抵達第一金屬層氧化物107內之第一導體109。在一個實例中，腔827係使用一單一遮罩自背側213如描述般而蝕刻。
圖8係繪示如在上面的實例中所描述的積體電路系統101之一實例之一橫截面圖，其中自背側213在第一導體109與第二導體209之間 蝕刻一腔使其穿過氧化物沈積521、穿過第二金屬層氧化物207並穿過接合介面315。另外，圖8繪示根據本發明之教示之一障壁金屬沈積931，其自背側213沈積在氧化物沈積521上方及在溝槽623之壁及腔725之壁上方，覆蓋第一導體109、第二導體209、第一金屬層氧化物107及第二金屬層氧化物207之暴露部分。
圖9係繼續如上面所描述的實例積體電路系統101之一橫截面圖，其中障壁金屬沈積931係自背側213沈積在氧化物沈積521上方及在溝槽623之壁及腔725之壁上方。另外，圖9繪示用一導電材料1033自背側213填充腔725、溝槽623及開口519。因此，根據本發明之教示，耦合第一導體109及第二導體209之一導電路徑1035現在具備形成於腔725中之導電材料1033。因此，第一導體109係透過導電路徑1035及透過障壁金屬沈積931而耦合至第二導體209。
圖10係繼續如上面所描述之實例積體電路系統101之一橫截面圖，其中腔725、溝槽623及開口519係用導電材料1033自背側213填充以在第一導體109與第二導體209之間提供導電路徑1035。另外，圖10展示在如所示蝕刻及/或拋光至氧化物沈積521之後第二器件晶圓203之背側213之一實例，根據本發明之教示，此蝕刻及/或拋光操作自背側213移除過多的導電材料1033。
圖11係繼續如上面所描述之實例積體電路系統101之一橫截面圖，其中第二器件晶圓203之背側213被蝕刻及/或拋光至氧化物沈積521，從而自背側213移除過多的導電材料1033。另外，圖11繪示根據本發明之教示之一實例積體電路系統101中之一實例，其中形成一線接合腔1137及一線接合1139，以提供至第二金屬層氧化物207中之一導體之一封裝連接。
所繪示之本發明之實例之以上描述(包含摘要中描述之內容)並不意欲為詳盡的或限制於所揭示之精確形式。雖然為了繪示目的而在本 文中描述本發明之特定實施例及實例，但是在不脫離本發明之較寬廣精神及範圍的情況下，各種等效修改是可能的。當然，應瞭解特定實例電壓、電流、頻率、功率範圍值、時間等等係提供用於解釋目的，且根據本發明之教示在其他實施例及實例中亦可使用其他值。
可根據上面的詳細描述對本發明的實例做出此等修改。在隨附申請專利範圍中使用之術語不應解釋為將本發明限制於說明書及申請專利範圍中所揭示之特定實施例。而是，範圍應完全由隨附申請專利範圍來決定，申請專利範圍應根據既定請求項解釋條款來解讀。本說明書及附圖因此應視為說明性而不是限制性的。
101‧‧‧積體電路系統
103‧‧‧第一器件晶圓
105‧‧‧第一半導體層
107‧‧‧第一金屬層氧化物
109‧‧‧第一導體
111‧‧‧第一器件晶圓之前側/第一金屬層氧化物之前側
113‧‧‧第一器件晶圓之背側
203‧‧‧第二器件晶圓
205‧‧‧第二半導體層
207‧‧‧第二金屬層氧化物
209‧‧‧第二導體
211‧‧‧第二器件晶圓之前側/第二金屬層氧化物之前側
213‧‧‧第二器件晶圓之背側/第二半導體層之背側
315‧‧‧接合介面
417‧‧‧鈍化層
519‧‧‧開口
521‧‧‧氧化物沈積
623‧‧‧溝槽
725‧‧‧腔
931‧‧‧障壁金屬沈積
1033‧‧‧導電材料
1035‧‧‧導電路徑
1137‧‧‧線接合腔
1139‧‧‧線接合

Claims (20)

  1. 一種積體電路系統，其包括：一第一器件晶圓，其具有一第一半導體層，該第一半導體層接近安置於一第一金屬層氧化物內之包含一第一導體之一第一金屬層；一第二器件晶圓，其具有一第二半導體層，該第二半導體層接近安置於一第二金屬層氧化物內之包含一第二導體之一第二金屬層，其中該第一器件晶圓之該第一金屬層氧化物之一前側在該第一金屬層氧化物與該第二金屬層氧化物之間之一接合介面處接合至該第二器件晶圓之該第二金屬層氧化物之一前側；及一導電路徑，其將該第一導體耦合至該第二導體，其中該導電路徑具備形成於一腔內之導電材料，該腔係蝕刻在該第一導體與該第二導體之間，且自該第二器件晶圓之一背側蝕刻穿過該接合介面及穿過該第二半導體層。
  2. 如請求項1之積體電路系統，進一步包括沈積在該導電路徑與該第一導體及該第二導體之間之該腔內之一障壁金屬沈積，其中該第一導體係透過該障壁金屬沈積及該導電路徑而耦合至該第二導體。
  3. 如請求項1之積體電路系統，進一步包括安置在該導電材料與該第二半導體層間之氧化物沈積。
  4. 如請求項3之積體電路系統，進一步包括安置在該第二半導體層之該背側與該氧化物沈積之間之一鈍化層。
  5. 如請求項1之積體電路系統，其中該第一金屬層氧化物之該前側及該第二金屬層氧化物之該前側之至少一者係藉由一化學機械拋光而平整化。
  6. 如請求項1之積體電路系統，其中穿過其蝕刻該腔之該第二半導體層係在蝕刻該腔之前經薄化。
  7. 如請求項1之積體電路系統，其中該腔經進一步蝕刻穿過該第二導體中之一環形孔。
  8. 如請求項1之積體電路系統，其中該腔經進一步蝕刻穿過自該第二半導體層之該背側蝕刻抵達該第一導體之一溝槽。
  9. 如請求項8之積體電路系統，其中該腔係在自該第二半導體層之該背側蝕刻抵達該第一導體之該溝槽之前經蝕刻。
  10. 如請求項1之積體電路系統，其中該第一器件晶圓及該第二器件晶圓之一者包括一成像器晶片，且該第一器件晶圓及該第二器件晶圓之另一者包括一處理晶片。
  11. 一種製造一積體電路系統之方法，其包括在安置於一第一金屬層氧化物內之接近一第一器件晶圓之一第一半導體層之一第一金屬層中，形成一第一導體；在安置於一第二金屬層氧化物內之接近一第二器件晶圓之一第二半導體層之一第二金屬層中，形成一第二導體；在該第一金屬層氧化物與該第二金屬層氧化物之間之一接合介面處，將該第一器件晶圓之該第一金屬層氧化物之一前側接合至該第二器件晶圓之該第二金屬層氧化物之一前側；自該第二器件晶圓之一背側，在該第一導體與該第二導體之間且穿過該接合介面及穿過該第二半導體層蝕刻一腔；及用導電材料填充該腔以提供將該第一導體耦合至該第二導體之一導電路徑。
  12. 如請求項11之方法，進一步包括在用該導電材料填充該腔以提供將該第一導體耦合至該第二導體之該導電路徑之前，在該腔中沈積一障壁金屬沈積。
  13. 如請求項11之方法，進一步包括在蝕刻該第一導體與該第二導體之間之該腔之前，鈍化該第二器件晶圓之該背側。
  14. 如請求項11之方法，進一步包括在蝕刻該第一導體與該第二導體之間之該腔之前，在該第二器件晶圓之該背側上沈積氧化物沈積。
  15. 如請求項11之方法，進一步包括在將該第一器件晶圓之該第一金屬層氧化物之該前側接合至該第二器件晶圓之該第二金屬層氧化物之該前側之前，藉由化學機械拋光來平整化該第一金屬層氧化物之該前側及該第二金屬層氧化物之該前側之至少一者。
  16. 如請求項11之方法，進一步包括在蝕刻該第一導體與該第二導體之間之該腔之前，薄化該第二器件晶圓之該第二半導體層。
  17. 如請求項11之方法，其中自該第二器件晶圓之該背側，在該第一導體與該第二導體之間且穿過該接合介面及穿過該第二半導體層蝕刻該腔包括：穿過該第二導體中之一環形孔而蝕刻該腔。
  18. 如請求項11之方法，進一步包括在蝕刻該第一導體與該第二導體之間之該腔之前，自該第二半導體層之該背側蝕刻一溝槽使其抵達該第二導體。
  19. 如請求項11之方法，進一步包括在蝕刻該第一導體與該第二導體之間之該腔之前，自該第二半導體層之該背側蝕刻一溝槽使其抵達該第二導體。
  20. 如請求項11之方法，其中該第一器件晶圓及該第二器件晶圓之一者包括一成像器晶片，且該第一器件晶圓及該第二器件晶圓之另一者包括一處理器晶片。
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