WO2021208078A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2021208078A1
WO2021208078A1 PCT/CN2020/085375 CN2020085375W WO2021208078A1 WO 2021208078 A1 WO2021208078 A1 WO 2021208078A1 CN 2020085375 W CN2020085375 W CN 2020085375W WO 2021208078 A1 WO2021208078 A1 WO 2021208078A1
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Prior art keywords
side wall
wafer
opening
connection
connecting plate
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PCT/CN2020/085375
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English (en)
French (fr)
Inventor
赫然
何志宏
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20931045.7A priority Critical patent/EP4131374A4/en
Priority to PCT/CN2020/085375 priority patent/WO2021208078A1/zh
Priority to CN202080093552.5A priority patent/CN114981962A/zh
Priority to KR1020227039876A priority patent/KR20230002752A/ko
Priority to JP2022562869A priority patent/JP2023521483A/ja
Publication of WO2021208078A1 publication Critical patent/WO2021208078A1/zh
Priority to US17/966,034 priority patent/US20230031151A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof.
  • Three-dimensional stacking technology is the current mainstream breakthrough solution.
  • Three-dimensional stacking technology can be used to form multilayer or 3D structures.
  • 3D structure such as three-dimensional integrated circuit (3D-IC), micro-electro-mechanical system (MEMS), complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) image sensor (CMOS image sensor) , CIS) and so on.
  • 3D-IC three-dimensional integrated circuit
  • MEMS micro-electro-mechanical system
  • CMOS complementary metal oxide semiconductor
  • CMOS image sensor complementary metal oxide semiconductor
  • CIS complementary metal oxide semiconductor
  • bonding is the core process, and it has gone through the technical iterative process from micro-bump bonding, copper pillar bonding to wafer bonding technology.
  • three-dimensional The stacking technology is dominated by wafer bonding technology, and wafer bonding technology has developed into the key of various manufacturers in the competition of three-dimensional stacking technology.
  • Wafer bonding is a technology for bonding and forming a mechanical and electrical connection between the wafer and the surface of the wafer.
  • Dielectric layer bonding is a way to realize wafer bonding.
  • the wafer bonding technology that forms a covalent bond bond, at this time the two wafers bonded to each other are not electrically connected.
  • through silicon via (TSV) technology can be used.
  • TSV technology forms through holes from the back of the wafer and fills them with conductive materials to achieve inter-wafer interconnection.
  • connection lines respectively connected to the two that is, different Connection between wafers.
  • the two wafers are connected by using contact plugs and connecting wires, and the wiring between the two is longer, so there is a longer signal delay, which cannot meet actual needs in some scenarios.
  • the use of multiple contact plugs to achieve three-dimensional interconnection occupies more plane space, which is not conducive to improving the integration density of the device.
  • the first aspect of the present application provides a semiconductor structure and a manufacturing method thereof, which reduces the signal delay between wafers.
  • the first aspect of the embodiments of the present application provides a semiconductor device.
  • the semiconductor device may include: a first wafer, a second wafer, and a contact plug.
  • the first wafer may include a first dielectric layer, and the first dielectric layer may have a first connection pad.
  • the first connection pad may be used to extract signals from the first wafer.
  • the second wafer and the first wafer For bonding, the second wafer may include a second dielectric layer, and the second dielectric layer may have a second connection pad.
  • the second connection pad may be used for the signal extraction of the second wafer.
  • the contact plug may be filled in the vertical
  • the conductive material in the through hole is used to electrically connect the first land and the second land, wherein the vertical through hole is formed by etching through the first wafer and partially through the second wafer to the upper part of the second land
  • the first land is located in the vertical through hole and the first dielectric layer under the first land is not etched, so that the contact plug in the vertical through hole can pass through and
  • the upper surface of the first land and the upper surface and/or side wall of the second land are in contact to realize the electrical connection between the first land and the second land, thereby realizing the verticality of the first wafer and the second wafer interconnection.
  • the contact plug serves as the signal transmission channel between the first connection pad and the second connection pad, and its path is short, which reduces the signal delay.
  • the vertical through hole is formed by an etching process, which penetrates from the sidewall of the first connection pad to The second connecting plate, in which the contact plug can contact the second connecting plate from the periphery of the first connecting plate, so that the reliable connection between the contact plug and the second connecting plate can be realized by a simple process.
  • there is only one metal plug in the embodiment of the present application and there is no need to consider the distance between the two metal plugs. Therefore, the lateral size can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.
  • the second connecting plate and the first connecting plate are arranged longitudinally opposite to each other, and at least one side wall of the second connecting plate extends laterally beyond the side of the first connecting plate.
  • the vertical through hole exposes the upper surface of the second connecting plate adjacent to the at least one side wall, or the second connecting plate and the at least one side wall and adjacent Upper surface.
  • the side wall of at least one side of the second connecting plate extends laterally beyond the side wall of the first connecting plate.
  • the adjacent upper surface of the side wall of the connecting pad is used to realize the contact between the contact plug and the second connecting pad.
  • the vertical through hole can also expose the side wall of the second connecting pad and the side wall beyond the first connecting pad, so as to be able to The contact reliability of the contact plug and the second connection pad is improved to a certain extent, thereby increasing the reliability of the electrical connection between the first connection pad and the second connection pad.
  • the vertical through hole exposes the side wall of the first connection pad; or in the vertical through hole, the first dielectric layer remains on the side wall of the first connection pad.
  • the vertical through hole can expose the sidewall of the first land, and the contact reliability between the contact plug formed in the vertical through hole and the first land can be improved.
  • the vertical through hole may not The sidewalls of the first connection pad are exposed, but the first dielectric layer on the sidewalls of the first connection pad is retained during the etching process. In this way, the first dielectric layer can protect the sidewalls of the first connection pad, thereby improving the The structural integrity of a connecting plate further improves the functional integrity of the first connecting plate.
  • the second connecting disk and the first connecting disk are arranged longitudinally and directly opposite to each other, and at least one side wall of the second connecting disk is flush with the side wall of the first connecting disk ,
  • the vertical through hole exposes at least one side wall of the second connection plate and the side wall of the first connection plate that is flush with the second connection plate.
  • the side wall of at least one side of the second connection plate is flush with the side wall of the first connection plate.
  • the vertical through holes can be used to expose the sides of the first connection plate and the second connection plate.
  • the second connection plate and the first connection plate are longitudinally staggered, and the size of the top opening of the vertical through hole is greater than or equal to that of the second connection plate and the first connection plate.
  • the lateral distance of the connecting plate is greater than or equal to that of the second connection plate and the first connection plate.
  • the second connecting plate and the first connecting plate can be longitudinally staggered.
  • the first connecting plate and the second connecting plate have no overlapping area in the longitudinal direction, and there is a horizontal distance in the horizontal direction, the vertical
  • the size of the through hole at the top opening can be greater than or equal to the lateral distance between the second connecting pad and the first connecting pad, so as to smoothly expose the first connecting pad and the second connecting pad to realize the electrical connection between the two and improve the electrical connection. reliability.
  • the semiconductor device further includes: a third wafer
  • the third wafer has a third connection pad; the third wafer and the first wafer are bonded to realize the electrical connection between the third connection pad and the contact plug.
  • the semiconductor device may further include a third wafer, and the third connection pad in the third wafer may be electrically connected to the first wafer and the second wafer by being electrically connected to the contact plug.
  • the third wafer can be bonded with the first wafer, thereby further improving the integration of the device.
  • the vertical through hole penetrates through the multi-side sidewall direction of the first connecting plate.
  • the vertical through hole may penetrate through the direction of the side wall of the first connection plate, so that the contact plug formed in the vertical through hole can surround the first connection plate on multiple sides, thereby improving the contact plug and the first connection plate.
  • the contact reliability of the connecting pad can also increase the contact area between the contact plug and the second connecting pad to a certain extent, so as to improve the contact reliability of the contact plug and the second connecting pad.
  • a second aspect of the embodiments of the present application provides a method for manufacturing a semiconductor device, including:
  • the first wafer includes a first dielectric layer, the first dielectric layer has a first connection pad;
  • the second wafer includes a first dielectric layer Two dielectric layers, the second dielectric layer has a second connection pad;
  • the first wafer is etched from top to bottom to form a vertical through hole, and the vertical through hole penetrates the first wafer to the first connection pad.
  • the upper surface and penetrate the second wafer to the second land along the side wall of the first land, and expose the upper surface and/or side wall of the second land;
  • the vertical through hole is filled with conductive material to form a contact plug, and the contact plug is used to realize electrical connection between the first connection pad and the second connection pad.
  • the second connection pad and the first connection pad are arranged longitudinally and directly opposite to each other, and then the first connection pad is used as a barrier layer to prevent the first wafer from above.
  • Etching to form vertical through holes includes:
  • the first opening and the second opening are deepened together, so that the deepened first opening exposes the upper surface of the first connecting plate, so that the deepened
  • the second opening exposes the upper surface and/or the side wall of the second connecting plate.
  • the side wall of the first opening laterally extends beyond the side wall of the first connecting plate, and at least one side wall of the second connecting plate extends laterally beyond all sides.
  • the deepened second opening exposes the adjacent upper surface of the second connection plate that extends laterally beyond the side wall of the first connection plate, or the second connection The side wall of the disc and its adjacent upper surface beyond the side wall of the first connecting disc in the lateral direction;
  • At least one side wall of the second connection plate is connected to the side of the first connection plate. If the wall is flush, the deepened second opening exposes the side wall of the second connecting disk that is flush with the first connecting disk.
  • the side wall of the second connection plate extends laterally beyond the side wall of the first connection plate, and the side wall of the first connection plate in the deepened second opening The wall retains the first dielectric layer.
  • the second connection plate and the first connection plate are arranged longitudinally and directly opposite to each other, and the first dielectric layer has a third opening; then, the first connection plate is used as a barrier.
  • a first opening is obtained by etching from the upper surface of the first wafer; the first opening is located above the first connection plate, and at least one side wall of the first opening extends laterally beyond the first opening A side wall of the connecting plate;
  • the first connection pad as a barrier layer, the first dielectric layer and the second dielectric layer at the bottom of the first opening are etched so that the deepened first opening and the third opening are connected, and the etching
  • the third opening is deepened during the etching process; the deepened first opening exposes the upper surface of the first connecting plate, and the deepened third opening exposes the upper surface of the second connecting plate and/or Side wall.
  • the side wall of the first opening laterally extends beyond the side wall of the first connecting plate, and at least one side wall of the second connecting plate extends laterally beyond all sides.
  • the deepened third opening exposes the adjacent upper surface of the second connection plate that extends laterally beyond the side wall of the first connection plate, or the second connection The side wall of the disc and its adjacent upper surface beyond the side wall of the first connecting disc in the lateral direction;
  • At least one side wall of the second connection plate is connected to the side of the first connection plate. If the wall is flush, the deepened third opening exposes the side wall of the second connecting plate that is flush with the first connecting plate.
  • the side wall of the second connecting plate extends laterally beyond the side wall of the first connecting plate, and the third opening is on the side of the first connecting plate.
  • the wall retains the first dielectric layer.
  • the second connection pad and the first connection pad are arranged longitudinally and directly opposite to each other, and then the first connection pad is used as a barrier layer to prevent the first wafer from above.
  • Etching to form vertical through holes includes:
  • first connection disk as a barrier layer, deepen the first opening so that the deepened first opening exposes the upper surface of the first connection disk, and the upper surface of the second connection disk and /Or side wall.
  • the side wall of the first opening laterally extends beyond the side wall of the first connecting plate, and at least one side wall of the second connecting plate extends laterally beyond all sides.
  • the deepened first opening exposes the adjacent upper surface of the second connection plate that extends laterally beyond the side wall of the first connection plate, or the second connection The side wall of the disc and its adjacent upper surface beyond the side wall of the first connecting disc in the lateral direction;
  • the second connection pad and the first connection pad are arranged longitudinally and directly opposite to each other, and then the first connection pad is used as a barrier layer to prevent the first wafer from above.
  • Etching to form vertical through holes includes:
  • a fourth opening is obtained by etching from the upper surface of the first wafer; at least one side wall of the fourth opening extends laterally beyond the side wall of the first connection pad;
  • first connecting pad as a barrier layer
  • etching is performed above the first connecting pad and the bottom of the fourth opening to expose the upper surface of the first connecting pad, and the deepened fourth The opening exposes the upper surface and/or the side wall of the second connection plate.
  • the side wall of the fourth opening laterally extends beyond the side wall of the first connecting plate, and at least one side wall of the second connecting plate extends laterally beyond all sides.
  • the deepened fourth opening exposes the adjacent upper surface of the second connection plate that extends laterally beyond the side wall of the first connection plate, or the second connection The side wall of the disc and its adjacent upper surface beyond the side wall of the first connecting disc in the lateral direction;
  • At least one side wall of the second connection plate is connected to the side of the first connection plate. If the wall is flush, the deepened fourth opening exposes the side wall of the second connecting disk that is flush with the first connecting disk.
  • the filling a conductive material in the vertical through hole to form a contact plug includes:
  • a planarization process is used to remove the conductive material on the upper surface of the first wafer to form a contact plug in the vertical through hole.
  • the semiconductor device may include a first wafer, a second wafer, and contact plugs.
  • the first wafer may include a first dielectric layer, and a first wafer.
  • the dielectric layer has a first connection pad
  • the second wafer is bonded to the first wafer
  • the second wafer includes a second dielectric layer
  • the second dielectric layer has a second connection pad
  • the contact plug is filled in the vertical through hole
  • the conductive material in is used to electrically connect the first connection pad and the second connection pad, wherein the vertical through hole is formed by etching and penetrates the first wafer and partially penetrates the second wafer to the upper surface of the second connection pad and /Or the through hole of the side wall, the first connecting pad is located in the vertical through hole and the first dielectric layer under the first connecting pad is not etched.
  • the vertical through hole can expose the upper surface of the first wafer, as well as the upper surface and/or sidewall of the second land, so that the contact plug in the vertical through hole can be connected to the first land and the second at the same time
  • the contact plug is used as the signal transmission channel between the first connection plate and the second connection plate to realize the electrical connection between the first connection plate and the second connection plate.
  • the through hole is formed by an etching process and penetrates from the sidewall of the first land to the second land, and the contact plugs therein can contact the second land from the periphery of the first land, so that the contact plug can be realized by a simple process Reliable connection with the second connecting plate.
  • the lateral size can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.
  • Figure 1 is a schematic diagram of a bonding structure in the prior art
  • Figure 2 is a top view of a three-dimensional interconnect structure in the prior art
  • FIG. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a shape of the first connecting plate and the second connecting plate in the embodiment of the application;
  • FIG. 5 is a schematic structural diagram of a semiconductor device provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a three-dimensional interconnection structure provided by an embodiment of the application.
  • FIG. 9 is a top view of a three-dimensional interconnection structure provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of still another semiconductor device provided by an embodiment of the application.
  • FIG. 11 is a schematic diagram of another shape of the first connecting plate and the second connecting plate in the embodiment of the application;
  • FIG. 12 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of another semiconductor device provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of another semiconductor device provided by an embodiment of the application.
  • 15 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the application.
  • 16-20 are schematic diagrams of the semiconductor device in the manufacturing process of the semiconductor device in the embodiment of the application.
  • the present application provides a semiconductor device and a manufacturing method thereof to reduce signal delay and occupied area, and improve the integration density of the device.
  • the three-dimensional stacking technology can bond different wafers together, reduce the plane space of the three-dimensional device, and increase the integration density.
  • a first device 130 may be formed in the first wafer 100, the first device 130 may be, for example, a CIS, and the second wafer 200 A second device 230 may be formed.
  • the second device 230 may be, for example, an image system processor (ISP), and then the first wafer 100 and the second wafer 200 are bonded together to form an image sensor system.
  • the first device is formed in the dielectric layer 120 on the substrate 110, the second device is formed in the dielectric layer 220 on the substrate 210, and the bonding between the first wafer 100 and the second wafer 200 after bonding is formed ⁇ 1001.
  • the first wafer 100 and the second wafer 200 can be bonded at the dielectric layer, and the through silicon via technology can be used to etch from the substrate 110 of the first wafer 100 to form a through silicon through to the CIS.
  • the through silicon via technology can be used to etch from the substrate 110 of the first wafer 100 to form a through silicon through to the CIS.
  • two metal plugs 140 and 240 connected to the CIS and the ISP are obtained.
  • the metal plugs 140 and 240 can realize the signal in the bonding structure.
  • a horizontal redistribution layer (RDL) 150 is formed on the back of the substrate 110 of the first wafer 100 to realize the electrical connection of the two metal plugs 140 and 240, so that the CIS and the ISP pass.
  • the two metal plugs 140, 240 and the rewiring layer 150 are electrically connected, that is, three-dimensional interconnections between wafers of different layers are realized.
  • the signal of the ISP in the second wafer 200 needs to be transmitted upwards through the metal plug 240 connected to the ISP, and then transmitted through the horizontal redistribution layer 150 to be connected to the ISP. After passing down the metal plug 140, it can reach the CIS in the first wafer 100.
  • Resistance and capacitance are related, leading to a long delay time for signal transmission, which cannot meet actual needs in some scenarios.
  • two metal plugs are needed to realize the connection between the CIS and the ISP. Refer to FIG.
  • the semiconductor device may include a first wafer, a second wafer, and a contact plug.
  • the first wafer may include a first dielectric layer, and a first wafer.
  • a dielectric layer has a first connection pad
  • the second wafer is bonded to the first wafer
  • the second wafer includes a second dielectric layer
  • the second dielectric layer has a second connection pad
  • the contact plug is filled in the vertical communication
  • the conductive material in the hole is used to electrically connect the first land and the second land, wherein the vertical through hole is formed by etching and penetrates the first wafer and partially penetrates the second wafer to the upper surface of the second land And/or the through hole of the side wall, the first connection pad is located in the vertical through hole and the first dielectric layer under the first connection pad is not etched.
  • the vertical through hole can expose the upper surface of the first wafer, as well as the upper surface and/or sidewall of the second land, so that the contact plug in the vertical through hole can be connected to the first land and the second at the same time
  • the contact plug is used as the signal transmission channel between the first connection plate and the second connection plate to realize the electrical connection between the first connection plate and the second connection plate.
  • the through hole is formed by an etching process and penetrates from the sidewall of the first land to the second land, and the contact plugs therein can contact the second land from the periphery of the first land, so that the contact plug can be realized by a simple process Reliable connection with the second connecting plate.
  • the lateral size can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.
  • the semiconductor device may include a first wafer 300, a second wafer 400, and a first wafer 300 and a second wafer. Circle 400 of vertically interconnected contact plugs 360.
  • the first wafer 300 may include a first substrate 310, a first dielectric layer 320 on the first substrate 310, and a first land 330 in the first dielectric layer 320
  • the second wafer 400 may include a second substrate 410, a second dielectric layer 420 on the second substrate 410, and a second land 430 in the second dielectric layer 420.
  • the first substrate 310 and the second substrate 410 may be semiconductor substrates, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium on Insulator). , Germanium On Insulator) and so on.
  • the first substrate 310 and the second substrate 410 may also be substrates including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., and may also have a stacked structure, such as Si/SiGe. It can also be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator).
  • the first substrate 310 and the second substrate 410 may be the same material or different materials. In this embodiment, the first substrate 310 and the second substrate 410 may both be silicon substrates.
  • the device structure is covered by an interlayer dielectric layer.
  • the interlayer dielectric layer can be silicon oxide.
  • the interconnection structure is formed in the dielectric material.
  • the device structure can be a MOS device, a storage device and/or other passive devices.
  • the interconnection structure can be multiple Layer structure, the interconnection structure may include contact plugs, vias or connection layers, the connection layer may be located on the top layer of the interconnection structure, as a lead structure of the interconnection structure, the connection layer may include a plurality of connection pads.
  • the interconnection structure may be a metal material, such as tungsten, aluminum, copper, or the like.
  • tungsten such as tungsten, aluminum, copper, or the like.
  • top connection layer is shown. This is just to simplify the drawings. It should be understood that this is only an example. In different designs and applications, it can be used as required. Form the interconnect structure of the required number of layers.
  • the first substrate 310 and the second substrate 410 may be formed with the same device structure or different device structures.
  • the devices on the first substrate 310 and the second substrate 410 may be both DRAM devices, or all logic devices, can also be two devices in DRAM and logic devices, respectively, two devices in SRAM and logic devices, or two devices in CIS and ISP, etc. .
  • the same interconnection structure may be formed on the first substrate 310 and the second substrate 410, or different interconnection structures may be formed.
  • the connection between the interconnection structure on the first substrate 310 and the second substrate 410 The discs can have the same structure or different structures.
  • the embodiment of the present application takes the first land 330 in the interconnect structure on the first substrate 310 and the second land 430 in the interconnect structure on the second substrate 410 as examples to illustrate different crystals. Interconnect structure between circles.
  • the first land 330 is the land in the interconnection structure of the first wafer 300 before bonding, and may be the top metal in the first wafer 300, and the material of the first land 330 may be metal copper.
  • the first land 330 may be covered by the first dielectric layer 320 to achieve isolation between different first land 330.
  • the first dielectric layer 320 may be a silicon oxide layer or a laminated structure, for example, it may include nitride The silicon layer and the silicon oxide layer on it.
  • the second land 430 is the land in the interconnection structure of the second wafer 400 before bonding, and may be the top metal layer in the second wafer 400, and the material of the second land 430 may be copper metal .
  • the second land 430 may be covered by the second dielectric layer 420, so as to realize the isolation between different second land 430.
  • the second dielectric layer 420 may be silicon oxide or a laminated structure, for example, it may include silicon nitride. Layer and the silicon oxide layer on it.
  • the surface of the first substrate 310 on which the device structure is formed is the front surface of the first wafer 300, and the surface opposite to the surface of the first substrate 310 on which the device is formed is the back surface of the first wafer 300.
  • the surface of the substrate 410 on which the device structure is formed is the front surface of the second wafer 400, and the surface opposite to the surface of the second substrate 410 on which the device is formed is the back surface of the second wafer 400.
  • the first wafer 300 and the second wafer 400 may be bonded together.
  • the first wafer 300 and the second wafer 400 may be two of multiple bonded wafers.
  • the front side of the first wafer 300 can be bonded to the front side of the second wafer 400
  • the front side of the first wafer 300 can also be bonded to the back side of the second wafer 400
  • the back side of the first wafer 300 It can also be relatively bonded to the front surface of the second wafer 400
  • the back surface of the first wafer 300 can also be relatively bonded to the back surface of the second wafer 400.
  • the bonding surfaces of the first wafer 300 and the second wafer 400 are bonding surfaces.
  • the bonding surfaces may be formed with a material layer for bonding, and the bonding material layer may be an adhesive layer of dielectric material, such as an oxide layer. Silicon and silicon nitride bond the two wafers through the molecular force between the adhesive layers.
  • first and second wafer are relative, and are related to the bonding method of the first wafer 300 and the second wafer.
  • the first wafer 300 can be used as the upper wafer
  • the second wafer 400 can be used as the lower wafer
  • the front side of the first wafer 300 is used as the bonding surface
  • the first wafer 300 is turned over, the original "Up” becomes “Down”
  • the back of the first wafer 300 is used as the bonding surface, the first wafer 300 has not been turned over, and the original "Up” is still “Up”.
  • the first wafer 300 and the second wafer 400 are bonded, since the two are bonded through the dielectric layer, the first land 330 in the first wafer 300 and the second land 430 in the second wafer 400 The electrical connection has not been realized yet, so the connection between the first wafer 300 and the second wafer 400 needs to be realized through the vertical through holes 359.
  • the first wafer 300 may be used as the upper wafer in the bonding structure, so that the upper surface of the first wafer 300 is etched to form the vertical through holes 359.
  • the etching can be performed from the front surface of the first wafer 300, and when the front surface of the first wafer 300 is used as the bonding surface 1001, the etching can be performed from The backside of the first wafer 300 is etched.
  • TSV technology can be used to etch from the upper surface of the first wafer to form two through silicon vias penetrating the first and second lands respectively, and then fill the through silicon holes with metal materials as contact plugs , And then rewire the upper surface of the first wafer to establish the connection between the two contact plugs.
  • the channel between the first and second connection pads is longer, and the size of each contact plug is limited by the etching process and cannot be reduced indefinitely.
  • the distance between the contact plugs is also Due to the limitation, the two three-dimensional interconnection structures in this process occupies a larger plane area.
  • the first land and the second land The size of the land is also limited by the etching process and matches the size of the contact plug. Therefore, the size of the first land and the second land is larger. At the same time, the distance between the first land and the second land Corresponding to the lateral distance of the contact plug, the minimum distance is limited, so the wiring design is also limited.
  • the etching can be started from the upper surface of the first wafer 300, and the first land 330 is used as the barrier layer to form a vertical through hole 359, and in this vertical through hole 359 Inside, the upper surface of the first land 330 and the upper surface and/or sidewalls of the second land 430 are exposed.
  • the first land 330 can protect the first dielectric layer and the second dielectric layer below it from being etched In this way, after the vertical through hole 359 is filled with metal, the formed contact plug 360 is in contact with the upper surface of the first land 330 and at the same time is in contact with the upper surface and/or sidewall of the second land 430, that is, the formed contact plug 360 is in contact with the first connecting pad 330 and the second connecting pad 430 at the same time, forming a connection between the first connecting pad 330 and the second connecting pad 430.
  • the contact plug 360 can surround the first connection pad 330 on at least one side, and the planar size of the first connection pad 330 is not very demanding, so the planar area of the device can be further reduced.
  • the vertical through hole 359 may be a through hole with uneven upper and lower dimensions. Specifically, it may penetrate the first wafer to the upper surface of the first land 330, thereby exposing the upper surface of the first land 330.
  • the vertical through hole 359 also The first wafer and the second wafer can be penetrated to the second land 430 along the sidewalls of the first land 330, thereby exposing the upper surface and/or sidewalls of the second land 430.
  • the first connecting pad 330 may have a larger through hole size
  • the first connecting pad 330 and the second connecting pad 430 may have a smaller through hole size.
  • the vertical through holes 359 may expose the entire upper surface of the first land 330 or part of the upper surface of the first land 330; the vertical through holes 359 may expose one or more sides of the first land 330 The wall may not expose the side wall of the first connection pad 330.
  • the side wall of the first connection pad 330 is partially covered by the first dielectric layer, thereby protecting the first connection pad 330; the vertical through hole 359 may be exposed
  • the entire upper surface of the second connecting pad 430 may also expose part of the upper surface of the second connecting pad 430; the vertical through holes 359 may expose one or more side walls of the second connecting pad 430, or may not expose the second connecting pad
  • the side wall of the disk 430, at this time, the side wall of the second connecting disk 430 is covered by the second dielectric layer.
  • the first connecting plate 330 may be polygonal or circular
  • the second connecting plate 430 may be polygonal or circular.
  • the shape of the first connection plate 330 and the second connection plate 430 can be the same or different.
  • the first connection plate 330 and the second connection plate 430 have a relatively short lateral distance and can have overlapping projections in the longitudinal direction. There can be no overlapping projections in the longitudinal direction.
  • the polygon may be a bar, for example, the circle may be a perfect circle or an ellipse.
  • the first connecting disk 330 is a bar
  • the second connecting disk 430 is also a bar
  • the size of the two connecting plates 430 may be the same or different.
  • the second land 430 and the first land 330 may be arranged in a vertical direction, that is, In other words, the first connecting pad 330 and the first connecting pad 330 have an overlapping area in the direction perpendicular to the bonding surface 1001, and the side wall of the second connecting pad 430 is flush with at least one side of the side wall of the first connecting pad 330 In this way, the side walls of the second land 430 and the first land 330 can be exposed in the vertical through hole 359, and the side walls of the second land 430 and the first land 330 exposed are flush, so that the vertical through hole 359
  • the contact plugs 360 filled in the middle are respectively connected to the side walls of the second connection pad 430 and the side walls of the first connection pad 330, so that the first connection pad 330 and the second connection pad 430 can be electrically connected.
  • the second connection plate 430 may be aligned with the first connection plate 330 on one side, and the first connection plate 330 has a side wall that extends laterally beyond the side wall of the second connection plate 430, and the contact plug 360 can contact the first connection plate 430.
  • the second land 430 and the first land 330 may be arranged directly opposite to each other in the longitudinal direction. And at least one side wall of the second connecting plate 430 extends laterally from the side wall of the first connecting plate 330, and the vertical through hole 359 is formed to expose at least the second connecting plate 430 beyond the first connecting plate 330 in the lateral direction. Part of the surface of the side, that is, the upper surface of the second connecting plate 430 adjacent to the side wall of the first connecting plate 330 in the lateral direction may be exposed, or the upper surface of the second connecting plate 430 may be exposed beyond the first connecting plate 330 in the lateral direction.
  • the contact plug 360 filled in the vertical through hole 359 is at least in contact with the upper surface of the second connection pad 430.
  • the upper surface of the first connection pad 330 may be exposed in the vertical through hole 359, so that the contact plug 360 can connect the first connection pad 330 and the second connection pad 430.
  • the second connecting plate 430 may have a side wall extending laterally beyond the first connecting plate 330.
  • the second connecting plate 430 may have one side wall aligned with the first connecting plate 330, and the other side wall may extend laterally beyond the side wall of the first connecting plate 330, and the contact plug 360 may contact
  • the upper surface and multi-side side walls of the first connecting plate 330, and the side wall and the other upper surface of the second connecting plate 430 are shown with reference to FIG. 6(a); with reference to FIG.
  • the second connection plate 430 may have one side wall extending laterally beyond the first connection plate 330, and the other side wall is recessed relative to the first connection plate 330, and the contact plug 360 may contact the upper surface of the first connection plate 330 and a The side wall, and the upper surface of the second connecting plate 430 laterally beyond the side of the first connecting plate 330, refer to FIG. 6(b).
  • the second land 430 may have multiple sidewalls that extend laterally beyond the first land 330.
  • FIG. 7 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
  • the contact plug 360 can contact the upper surface and one side wall of the first connecting pad 330, and the upper surface of the second connecting pad 430 laterally beyond the side of the first connecting pad 330, as shown in FIG. 7(a)
  • the contact plug 360 can contact the upper surface and the side walls of the first connection plate 330, and the upper surface of the second connection plate 430, as shown in FIG. 7(b) and FIG. 3; the contact plug 360 can contact the first
  • FIG. 7(c) The upper surface and multi-side side walls of the connecting plate 330, and the upper surface and the multi-side side walls of the second connecting plate 430 are shown in FIG. 7(c).
  • a part of the first dielectric layer may also remain between the contact plug 360 and the first connection pad 330, so as to protect the first connection pad 330 during the etching process.
  • the contact plug 360 can connect the first connection plate 330 and the second connection plate 430 from multiple sides of the first connection plate 330, which improves the contact plug 360 and the second connection plate 430 to a certain extent.
  • the contact area improves the contact reliability between the contact plug 360 and the second connection pad 430.
  • the contact plug 360 constitutes an arch structure to realize the The first connection plate 330 and the second connection plate 430 are connected, wherein the contact plug 360 is formed on the left and right sides of the first connection plate 330, the left and right width of the first connection plate 330 can be smaller, and at the same time, the first connection The pad 330 and the second connection pad 430 may have an overlapping area without having to set a larger distance, so that the wiring area can be reduced to a certain extent.
  • FIG. 10 is a schematic structural diagram of another semiconductor device provided by an embodiment of this application
  • the second land 430 and the first land 330 are staggered in the longitudinal direction, that is, the first land
  • the second connecting pad 430 and the first connecting pad 330 have no overlapping area in the direction perpendicular to the bonding surface 1001. Therefore, the size of the top opening of the vertical through hole 359 is greater than or equal to the second connecting pad 430 and the first connecting pad 330 horizontal distance.
  • the vertical through hole 359 can expose the opposite of the first land 330 and the second land 430.
  • the side wall of the first connecting pad 330 that faces the second connecting pad 430 is exposed, and the side wall of the second connecting pad 430 facing the first connecting pad 330 is exposed, and the vertical through holes 359 are at different depths.
  • the lateral size is uniform, so that the metal plug 360 in the vertical through hole 359 can connect the exposed sidewalls of the first land 330 and the second land 430 to realize the electrical connection between the two; an opening at the top of the vertical through hole 359
  • the size of the position can be larger than the lateral size of the second connecting pad 430 and the first connecting pad 330, so in addition to exposing the opposite sidewalls of the first connecting pad 330 and the second connecting pad 430, the vertical through hole 359 may also expose the first connecting pad.
  • FIG. 10(a) Part of the upper surface of the disk 330 and/or the second land 430 is shown in FIG. 10(a) to improve the reliability of contact.
  • the vertical through hole 359 exposes the foundation of the upper surface of the first land 330
  • a part of the first dielectric layer can be reserved on the sidewall of the first connection pad 330, so as to protect the first connection pad 330, as shown in FIG. 10(b).
  • the shape of the first connecting plate 330 may also be a slit type or a comb tooth type.
  • the second The shape of the connecting plate 430 can be polygonal, circular, slit or comb-like; of course, when the shape of the first connecting plate 330 is polygonal or circular, the shape of the second connecting plate 430 can be a slit or comb. Tooth type and slit type can be single slit type or multiple slit type.
  • the slit type can include a single slit type, refer to Figure 11(a), and a multi-slit type, refer to Figures 11(b) and 11(c), the comb tooth type refers to Figure 11(d), the comb tooth type
  • the number of middle comb teeth can be determined according to the actual situation.
  • the slit type or comb tooth type can be regarded as a combination of multiple lines, and the connection mode of each line can be referred to
  • the connection between the above lines, that is, the vertical through holes 359 formed can expose the sidewalls of the slit-type or comb-tooth-shaped connection plate, or may not expose the sidewalls, as long as the first connection plate 330 and the first connection plate 330 can be exposed at the same time.
  • Part of the upper surface of the second connecting pad 430 is sufficient to realize the contact between the contact plug 360 and the first connecting pad 330 and the second connecting pad 430 respectively.
  • FIG. 12 there is a schematic structural diagram of another semiconductor device provided by an embodiment of this application.
  • the contact plug 360 can be connected to the upper surface of the first land 330 and The side wall and the upper surface of the second connecting plate 430 are connected, as shown in FIG. 12(a); the contact plug 360 can be connected to the upper surface and the side wall of the first connecting plate 330, and the upper surface of the second connecting plate 430 and Side wall connection, refer to Figure 12(b).
  • the contact plug 360 can be connected to the upper surface and sidewalls of the first connecting pad 330 and the sidewalls of the second connecting pad 430, as shown in FIG. 12(c).
  • the vertical through hole 359 may be a through hole that penetrates from the upper surface of the first wafer 300 to the upper surface of the first land 330, and penetrates from the periphery of the first land 330 to the upper surface of the second land 430.
  • the upper surface of the first connection pad 330 and the upper surface and/or the side wall of the second connection pad 430 are exposed in the through hole, thereby forming a vertical through hole 359 with a larger upper portion and a smaller lower size.
  • the vertical through holes 359 feet above and below an interface may have different diameters.
  • FIG. 13 is a schematic structural diagram of another semiconductor device provided by this embodiment of the present application. .
  • the vertical through holes 359 feet in the first substrate 310 and the first dielectric layer 320 may have different diameters, as shown in FIG. 3; the vertical through holes 359 feet above and below the upper surface of the first land 330 may have different diameters.
  • the semiconductor device provided by the embodiment of the present application may further include a third wafer.
  • a schematic structural diagram of another semiconductor device provided by this embodiment of the present application the first wafer 300, the second wafer The circle 400 and the third wafer 500 constitute a three-layer stack.
  • the third wafer 500 may include a third substrate 510, a third dielectric layer 520 may be formed on the third substrate 510, a third land 530 may be provided in the third dielectric layer 520, and the third wafer 500 may be disposed on the third substrate 510.
  • the third connection pad 530 and the contact plug 360 in the third wafer 500 are electrically connected by the bonding of the first wafer 300 and the third wafer 500, and the third connection pad 530 and the contact plug 360 360, after the dielectric layer of the first wafer 300 and the third wafer 500 are bonded, other contact plugs can be formed by a manufacturing process similar to that of the contact plug 360 for connection (not shown), the first wafer 300
  • the bonding surface 5001 with the third wafer 500 can be referred to as shown in FIG. 14.
  • the embodiment of the present application provides a semiconductor device, including a first wafer, a second wafer, and contact plugs.
  • the first wafer may include a first dielectric layer, the first dielectric layer has a first connection pad, and the second The wafer is bonded to the first wafer.
  • the second wafer includes a second dielectric layer.
  • the second dielectric layer has a second connection pad.
  • the contact plug is a conductive material filled in the vertical through hole for electrical connection.
  • the first land and the second land, wherein the vertical through holes are through holes formed by etching that penetrate the first wafer and partially penetrate the second wafer to the upper surface and/or sidewall of the second land.
  • a land is located in the vertical through hole and the first dielectric layer under the first land is not etched, so that the contact plug in the vertical through hole can pass through the upper surface of the first land and the second
  • the upper surface and/or the side wall of the connection pad are in contact with each other to realize the electrical connection between the first connection pad and the second connection pad, thereby realizing the vertical interconnection of the first wafer and the second wafer.
  • the contact plug serves as a signal transmission channel between the first connection pad and the second connection pad, and its path is short, which reduces the signal delay.
  • the vertical through hole is formed by an etching process, which penetrates from the sidewall of the first connection pad to The second connecting plate, in which the contact plug can contact the second connecting plate from the periphery of the first connecting plate, so that the reliable connection between the contact plug and the second connecting plate can be realized by a simple process.
  • there is only one metal plug in the embodiment of the present application and there is no need to consider the distance between the two metal plugs. Therefore, the lateral size can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.
  • an embodiment of the present application also provides a method for manufacturing a semiconductor device.
  • FIG. 15, is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
  • -FIG. 20 is a schematic diagram of the semiconductor device in the manufacturing process of the semiconductor device in the embodiment of the application. The method may include the following steps:
  • the first wafer 300 may include a first substrate 310, a first dielectric layer 320 on the first substrate 310, a first land 330 in the first dielectric layer 320, and a second wafer 400 It may include a second substrate 410, a second dielectric layer 420 on the second substrate 410, and a second land 430 in the second dielectric layer 420.
  • the first substrate 310 and the second substrate 410 may be formed with the same device structure or different device structures.
  • the devices on the first substrate 310 and the second substrate 410 may be both DRAM devices, or all logic devices, can also be two devices in DRAM and logic devices, respectively, two devices in SRAM and logic devices, or two devices in CIS and ISP, etc. .
  • the first land 330 is the land in the interconnection structure of the first wafer 300 before bonding, and may be the top metal in the first wafer 300, and the material of the first land 330 may be metal copper.
  • the first land 330 may be covered by the first dielectric layer 320 to achieve isolation between different first land 330.
  • the first dielectric layer 320 may be a silicon oxide layer or a laminated structure, for example, it may include nitride The silicon layer and the silicon oxide layer on it.
  • the second land 430 is the land in the interconnection structure of the second wafer 400 before bonding, and may be the top metal layer in the second wafer 400, and the material of the second land 430 may be copper metal .
  • the second land 430 may be covered by the second dielectric layer 420, so as to realize the isolation between different second land 430.
  • the second dielectric layer 420 may be silicon oxide or a laminated structure, for example, it may include silicon nitride. Layer and the silicon oxide layer on it.
  • the surface of the first substrate 310 on which the device structure is formed is the front surface of the first wafer 300, and the surface opposite to the surface of the first substrate 310 on which the device is formed is the back surface of the first wafer 300.
  • the surface of the substrate 410 on which the device structure is formed is the front surface of the second wafer 400, and the surface opposite to the surface of the second substrate 410 on which the device is formed is the back surface of the second wafer 400.
  • the first wafer 300 and the second wafer 400 may be bonded together.
  • the first wafer 300 and the second wafer 400 may be two of a plurality of bonded wafers. Round, the front side of the first wafer 300 can be bonded to the front side of the second wafer 400, the front side of the first wafer 300 can also be bonded to the back side of the second wafer 400, and the back side of the first wafer 300 It can also be relatively bonded to the front surface of the second wafer 400, and the back surface of the first wafer 300 can also be relatively bonded to the back surface of the second wafer 400.
  • the surfaces of the first wafer 300 and the second wafer 400 for bonding may be formed with a material layer for bonding.
  • the bonding material layer may be an adhesive layer of dielectric material, such as silicon oxide and silicon nitride. The molecular force between the bonding layers realizes the bonding of the two wafers.
  • the first wafer 300 is etched from top to bottom by using the first land 330 as a barrier layer to form a vertical through hole 359.
  • the vertical through hole 359 penetrates the upper surface of the first land 330 of the first wafer, and The first wafer and the second wafer are penetrated along the sidewalls of the first land 330 to the second land 430, and the upper surface and/or sidewalls of the second land 430 are exposed.
  • the first wafer 300 may be used as the upper wafer in the bonding structure, so that the upper surface of the first wafer 300 is etched to form the vertical through holes 359. It is understandable that when the back surface of the first wafer 300 is used as the bonding surface 1001, the etching can be performed from the front surface of the first wafer 300, and when the front surface of the first wafer 300 is used as the bonding surface 1001, the etching can be performed from The backside of the first wafer 300 is etched.
  • the vertical through holes 359 may expose the entire upper surface of the first land 330 or part of the upper surface of the first land 330; the vertical through holes 359 may expose one or more sides of the first land 330 The wall may not expose the side wall of the first connection pad 330.
  • the side wall of the first connection pad 330 is partially covered by the first dielectric layer, thereby protecting the first connection pad 330; the vertical through hole 359 may be exposed
  • the entire upper surface of the second connecting pad 430 may also expose part of the upper surface of the second connecting pad 430; the vertical through holes 359 may expose one or more side walls of the second connecting pad 430, or may not expose the second connecting pad
  • the side wall of the disk 430, at this time, the side wall of the second connecting disk 430 is covered by the second dielectric layer.
  • the following takes the bonding of the front surface of the first wafer 300 and the second wafer 400 as an example for description.
  • the second connection plate 430 and the first connection plate 330 are arranged longitudinally and directly opposite to each other, the second connection plate 430 is located under the first connection plate 330, and the second connection plate 430 may have side walls and the first connection plate 430.
  • the sidewalls of the connection pad 330 are flush, and there may also be sidewalls that extend laterally beyond the sidewalls of the first connection pad 330.
  • the method for forming the vertical through holes 359 can be specifically as follows: first etch the upper surface of the first wafer A first opening is formed, the first opening is located above the first connecting plate 330, and at least one side wall of the first opening can extend laterally beyond the side wall of the first connecting plate 330, so that the first opening can be exposed by deepening
  • the first connection plate 330 etches the position of the bottom of the first opening beyond the side wall of the first connection plate 330 in the lateral direction, and a second connection plate 430 can be formed on the periphery of the first connection plate 330. Open, thereby forming a vertical through hole 359.
  • the first land 330 can protect the first dielectric layer and the second dielectric layer thereunder.
  • the position of the second opening can be determined according to the position of the second connection plate 430 relative to the first connection plate 330, and the side wall of the second connection plate 430 can extend beyond the side wall of the first connection plate 330 in the lateral direction. It is consistent with the direction in which the side wall of the second opening extends laterally beyond the side wall of the first connection plate 330.
  • etching can be performed from the backside of the first wafer 300, that is, etching is performed from the backside of the first substrate 310 to form a first opening 350.
  • the first opening 350 can be Above a connecting pad 330, and the sidewalls of the first opening 350 laterally extend beyond the sidewalls of the first connecting pad 330 on multiple sides, the etching of the first opening 350 can be stopped on the lower surface of the first substrate 310 The position can also be stopped in the first dielectric layer 320 by etching a part of the first dielectric layer 320 (not shown); the insulating layer 361 is deposited to protect the sidewall of the first opening 350; on the side of the first opening 350 The wall is etched beyond the bottom of the first land 330 in the lateral direction (this etching can expose the side wall of the first land 330, or leave a part of the first dielectric layer 320 without exposing the side of the first land 330 Wall), forming a second opening 351 penetrating to the bonding surface 1001, as shown in FIG.
  • the first opening 350 and the second opening 351 are also deepened, thereby The first dielectric layer 320 above the first land 330 and the second dielectric layer 420 above the second land 430 are removed to form a vertical through hole 359.
  • the vertical through hole 359 is formed
  • the upper surface of the first connecting pad 330 is exposed, and the upper surface of the second connecting pad 430 extends laterally beyond the upper surface of the first connecting pad 330 on multiple sides.
  • retaining part of the first dielectric layer 320 on the sidewall of the first connection pad 330 is beneficial to protect the first connection pad 330 and avoid damage or collapse of the first connection pad 330 caused by etching.
  • the second dielectric layer on the sidewall of the second land 430 can be etched and removed together to expose the side of the second land 430 wall.
  • etching is performed from the backside of the first wafer 300, that is, etching is performed from the backside of the first substrate 310 to form a first opening 350.
  • an opening 350 can be stopped at the lower surface of the first substrate 310, or it can be stopped in the first dielectric layer 320 by etching a part of the first dielectric layer 320 (not shown); the insulating layer 361 is deposited To protect the side wall of the first opening 350, refer to FIG. 17(c); the side wall of the first opening 350 extends beyond the bottom of the first connection pad 330 in the lateral direction to be etched to form the bonding surface 1001. Refer to Figure 17(c) for the second opening 351 shown in FIG.
  • the first opening 350 and the second opening 351 are also deepened, so that the deepened second opening 351 stops at the first
  • the lower surface of the second land 430 during the etching process, the first land 330 can protect the first dielectric layer and the second dielectric layer under it, thereby forming a vertical through hole 359, and the vertical through hole 359 exposes the first land 330
  • the upper surface of the second connecting plate 430 laterally exceeds the upper surface and the side walls of the first connecting plate 330 on multiple sides.
  • the dielectric layer on the sidewalls of the first land 330 and the second land 430 can be etched and removed to expose the first land 330 and the second land. Connect the side wall of the disk 430.
  • the second connecting plate 430 and the first connecting plate 330 are arranged longitudinally and directly opposite to each other, the second connecting plate 430 is located below the first connecting plate 330, and the second connecting plate 430 may have side walls and a first connecting plate.
  • the sidewalls of a connecting pad 330 are flush, and there may also be sidewalls that extend laterally beyond the sidewalls of the first connecting pad 330.
  • a third opening may be formed in the first wafer before the wafer bonding. It is formed in the first dielectric layer around the first connection pad 330, so that the etching load after bonding can be reduced.
  • the method of forming the vertical through hole can be specifically as follows: after the wafer is bonded, the upper surface of the first wafer is etched to form a first opening, the first opening is located above the first connection pad 330, and the first opening is At least one side of the side wall may extend laterally from the side wall of the first connection plate 330, so that the first opening can be deepened to expose the first connection plate 330, and at the same time, the first opening and the third opening can be connected, and the third opening can be connected to the third opening.
  • the opening is deepened, and the deepened third opening can expose the second connecting pad 430 to form a vertical through hole 359.
  • the first land 330 can protect the first dielectric layer and the second dielectric layer thereunder.
  • the position of the third opening can be determined according to the position of the second connection plate 430 relative to the first connection plate 330, and the side wall of the second connection plate 430 can extend beyond the side wall of the first connection plate 330 in the lateral direction. It is consistent with the arrangement direction of the third opening in the first dielectric layer.
  • a third opening 352 may be formed in the first wafer 300, and the third opening 352 is formed in In the first dielectric layer 320 around the first connection pad 330, that is, before the bonding of the first wafer 300 and the second wafer 400, the first dielectric layer 320 may be etched so as to be on the first connection pad.
  • a third opening 352 is formed around 330, as shown in FIG. 18(a). In this way, after the wafer is bonded, etching can be performed from the back of the first wafer 300, that is, from the back of the first substrate 310 to form a first opening 350, as shown in FIG.
  • the first opening 350 may be above the first connection plate 330, and the sidewalls of the first opening 350 laterally exceed the sidewalls of the first connection plate 330 on multiple sides.
  • the etching of the first opening 350 It can be stopped at the lower surface of the first substrate 310, or it can be stopped in the first dielectric layer 320 by etching a part of the first dielectric layer 320 (not shown); the insulating layer 361 is deposited to protect the first opening 350
  • Figure 18(c) as shown in Fig.
  • the second dielectric layer on the sidewall of the second land 430 can be etched and removed together to expose the side of the second land 430 Wall, no examples are given here.
  • the dielectric layer on the sidewalls of the first land 330 and the second land 430 can be etched away to expose the first land 330 and the second land 430 side walls.
  • the second connection plate 430 and the first connection plate 330 are arranged longitudinally and directly opposite to each other, the second connection plate 430 is located under the first connection plate 330, and the second connection plate 430 may have side walls and a first connection plate.
  • the sidewalls of a connecting pad 330 are flush, and there may also be sidewalls that extend laterally beyond the sidewalls of the first connecting pad 330.
  • the method of forming the vertical through holes 359 may be specifically as follows: firstly, the upper surface of the first wafer is engraved The first opening is formed by etching, and the first opening is located above the first connecting plate 330, and at least one side of the side wall of the first opening can extend laterally beyond the side wall of the first connecting plate 330, so that the first opening can be deepened Expose the first connection pad 330 and continue to deepen the first opening.
  • the first connection pad 330 can protect the first dielectric layer and the second dielectric layer underneath, and the first opening is etched laterally beyond the first connection pad 330 The first dielectric layer and the second dielectric layer at the position of, so that the deepened first opening penetrates through the second connection pad 430 at the periphery of the first connection pad 330, thereby forming a vertical through hole 359.
  • the sidewalls of the second land 430 extend laterally from the sidewalls of the first land 330 on multiple sides, and the etching is performed from the backside of the first wafer 300, that is, from the first substrate 310
  • the back surface is etched to form a first opening 350.
  • the first opening 350 may be above the first connecting plate 330, and the sidewalls of the first opening 350 laterally exceed the first opening 350 on multiple sides.
  • the etching of the first opening 350 can be stopped at the position of the lower surface of the first substrate 310, or it can be stopped by etching part of the first dielectric layer 320 (not shown).
  • first dielectric layer 320 In the first dielectric layer 320; an insulating layer 361 is deposited to protect the sidewalls of the first opening 350, as shown in FIG. 19(c); the first opening 350 is deepened, and the second land 430 is used as an etch stop layer. During the etching process, the first connecting pad 330 protects the first dielectric layer and the second dielectric layer underneath it until the upper surface of the second connecting pad 430 is exposed. At this time, the upper surface of the first connecting pad 330 is also exposed. In the deepened first opening 350, a vertical through hole 359 is formed, as shown in FIG. 19(d).
  • the second connection plate 430 and the first connection plate 330 are arranged longitudinally and directly opposite to each other, the second connection plate 430 is located below the first connection plate 330, and the second connection plate 430 may have side walls and a first connection plate.
  • the sidewalls of a connecting pad 330 are flush, and there may also be sidewalls that extend laterally beyond the sidewalls of the first connecting pad 330.
  • the method of forming the vertical through holes 359 may specifically be: etching from the upper surface of the first wafer A fourth opening is formed, at least one side of the side wall of the fourth opening extends laterally beyond the side wall of the first connection plate 330, and then the first connection plate 330 may be used as a barrier layer, above the first connection plate 330 and the fourth opening Etch the bottom of the first connection pad 330 to expose the upper surface of the first connection pad 330, while the deepened fourth opening exposes the upper surface and/or sidewalls of the second connection pad 430.
  • the first connection pad 330 can be Protect the first dielectric layer and the second dielectric layer underneath.
  • the sidewalls of the second land 430 extend laterally from the sidewalls of the first land 330 on multiple sides, and the etching is performed from the backside of the first wafer 300, that is, from the first substrate 310
  • the back side is etched, and the etching position is around the first land 330 until the lower or upper surface of the first land 330 is etched to obtain a fourth opening 353, as shown in FIG. 20(b) ;
  • an insulating layer 361 is deposited to protect the sidewall of the fourth opening 353, as shown in FIG.
  • the first dielectric layer 320 and the second dielectric layer 420 at the bottom of 353 are etched to expose the upper surface and sidewalls of the first land 330 and the upper surface of the second land 430, thereby forming vertical through holes 359, reference As shown in Figure 20(d).
  • the first land 330 of the upper wafer is used as a barrier layer when the vertical through hole 359 is etched until the second connection layer 430 of the lower wafer is exposed.
  • the first connection pad 330 is a conductive material, and can be set to a material with a higher etching selection ratio to the first dielectric layer and the second dielectric layer, such as a metal material or a doped semiconductor material.
  • the etching options for the metal and dielectric layers are relatively large. For example, SiO2:Al approaches 20:1, and SiO2:W approaches 80:1, so it will not cause damage to the first connection pad 330 and the second connection layer 430.
  • the second connection layer 430 is etched away, it can be ensured that the first connection pad 330 still exists until the first dielectric layer 320 and the second dielectric layer 420 are completely etched away.
  • the second connection layer 430 stops the etching, and the etching process is relatively simple.
  • the upper surface of the first wafer 300 can be etched to form a vertical through hole 359 as the vertical through hole 359, and in this vertical through hole 359, the first connecting pad 330 is exposed.
  • the upper surface, and the upper surface and/or sidewalls of the second land 430 so that after the vertical through hole 359 is filled with metal, the formed contact plug 360 is in contact with the upper surface of the first land 330 and at the same time with the second land
  • the upper surface and/or the side wall of the 430 are in contact, that is, the formed contact plug 360 is in contact with the first connecting pad 330 and the second connecting pad 430 at the same time, thereby realizing the electrical connection of the first connecting pad 330 and the second connecting pad 430.
  • a contact plug 360 is formed in the vertical through hole 359, and conductive material can be formed in the vertical through hole 359 by electroplating or deposition, and then a planarization process, such as a chemical mechanical polishing process, is used to remove the conductive material outside the vertical through hole 359 , Thereby forming a contact plug 360.
  • the material of the contact plug 360 may be copper or aluminum, other conductive metal materials or non-metallic materials, for example, doped silicon.
  • a first wafer and a second wafer that have been bonded are provided.
  • the first wafer includes a first dielectric layer, and the first dielectric layer includes a first dielectric layer.
  • the connection pad, the second wafer includes a second dielectric layer, the second dielectric layer has a second connection pad, and the first connection pad is used as a barrier layer.
  • Etching from the first wafer from top to bottom can form a vertical connection
  • the vertical through hole penetrates the first wafer to the upper surface of the first land, and penetrates the second wafer to the second land along the sidewall of the first land, and exposes the upper surface of the second land and/ Or sidewalls
  • the vertical vias are filled with conductive material to form contact plugs, that is, the vertical vias can expose the upper surface of the first wafer and the upper surface and/or sidewalls of the second land, so that it is vertical
  • the contact plug in the through hole can be in contact with the first connection plate and the second connection plate at the same time, so as to realize the electrical connection between the first connection plate and the second connection plate.
  • the signal transmission channel has a shorter path, which reduces the signal delay.
  • the vertical through hole is formed by an etching process.
  • the surrounding area of the device is in contact with the second connecting pad, so that a simple process is used to realize the reliable connection between the contact plug and the second connecting pad.
  • there is only one metal plug in the embodiment of the present application and there is no need to consider the distance between the two metal plugs. Therefore, it is possible to reduce the lateral size to a certain extent, reduce the size of the device, and improve the integration of the device.

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Abstract

一种半导体器件及其制造方法，半导体器件可以包括第一晶圆(300)、第二晶圆(400)和接触塞(360)，第一晶圆(300)中可以包括第一介质层(320)，第一介质层(320)中具有第一连接盘(330)，第二晶圆(400)和第一晶圆(300)键合，第二晶圆(400)包括第二介质层(420)，第二介质层(420)中具有第二连接盘(430)，接触塞(360)为填充于垂直通孔中的导电材料，用于电连接第一连接盘(330)和第二连接盘(430)，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆(300)且部分贯穿第二晶圆(400)至第二连接盘(430)的上表面和/或侧壁的通孔，第一连接盘(330)位于垂直通孔中且位于第一连接盘(330)之下的第一介质层(320)未被刻蚀，接触塞(360)可以从第一连接盘(330)的周围与第二连接盘(430)接触，从而利用简单的工艺实现接触塞(360)与第二连接盘(430)的可靠连接。

Description

一种半导体结构及其制造方法 技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构及其制造方法。
背景技术
近年来，半导体器件和集成电路的集成密度和功率密度快速增大，平面空间受限，摩尔定律走到瓶颈，三维堆叠技术为当前主流突破方案，利用三维堆叠技术可以形成多层或3D结构，3D结构例如三维集成电路(three dimensional integrated circuit，3D-IC)、微机电系统(Micro-Electro-Mechanical System，MEMS)、互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)图像传感器(CMOS image sensor，CIS)等。在三维堆叠技术中，键合是核心工艺，经历了从微凸点(micro-bump)键合、铜柱凸点(Cu pillar)键合到晶圆键合技术的技术迭代过程，目前，三维堆叠技术以晶圆键合技术为主，晶圆键合技术已经发展成为各厂商在三维堆叠技术竞争中的关键。
晶圆键合是一种将晶圆和晶圆表面进行贴合并形成机械、电学连接的技术，介质层键合是晶圆键合的一种实现方式，其是通过介质层与介质层之间形成共价键结合的晶圆键合技术，此时相互键合的两个晶圆并未实现电连接。为了实现介质层键合晶圆的互连，可以采用硅通孔(Through Silicon Via，TSV)技术，TSV技术是从晶圆的背面形成贯通的通孔并填充导电材料，以实现晶圆间的垂直互连，例如利用两个通孔分别贯通至不同晶圆中并填充导电材料，得到与这两个晶圆分别连接的接触塞，再设置与二者分别连接的连接线，即实现了不同晶圆之间的连接。然而这种方式中，两个晶圆之间利用接触塞和连接线实现连通，二者之间布线较长，因此具有较长的信号延迟，在一些场景下不能满足实际需要。同时，利用多个接触塞实现三维互连，占用较多的平面空间，不利于提高器件的集成密度。
发明内容
有鉴于此，本申请的第一方面提供了一种半导体结构及其制造方法，减少了晶圆之间的信号延迟。
本申请实施例的第一方面，提供了一种半导体器件，半导体器件可以包括：第一晶圆、第二晶圆和接触塞。其中，第一晶圆可以包括第一介质层，第一介质层中可以具有第一连接盘，第一连接盘可以用于第一晶圆的信号的引出，第二晶圆和第一晶圆键合，第二晶圆中可以包括第二介质层，第二介质层中可以具有第二连接盘，第二连接盘可以用于第二晶圆的信号的引出，接触塞可以为填充在垂直通孔中的导电材料，用于电连接第一连接盘和第二连接盘，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆且部分贯穿第二晶圆至第二连接盘的上表面和/或侧壁的通孔，第一连接盘位于垂直通孔中且位于第一连接盘之下的第一介质层未被刻蚀，这样，在垂直通孔中的接触塞可以通过与第一连接盘的上表面，以及第二连接盘的上表面和/或侧壁接触，实现第一连接盘和第二连接盘的电连接，从而实现第一晶圆和第二晶圆的垂直互连。接触塞作为第一连接盘和第二连接盘之间的信号传输通道，其路径较短，减小了信号延迟，同时垂直通孔利用刻蚀工艺形成，从第一连接盘的侧壁贯 穿至第二连接盘，其中的接触塞可以从第一连接盘的周围与第二连接盘接触，从而利用简单的工艺实现接触塞与第二连接盘的可靠连接。此外，本申请实施例中仅存在一个金属塞，无需考虑两个金属塞之间的距离，因此可以在一定程度上缩小横向尺寸，减小器件尺寸，提高器件的集成度。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，所述第二连接盘至少一侧的侧壁在横向上超出所述第一连接盘的侧壁，则所述垂直通孔暴露所述第二连接盘与所述至少一侧的侧壁相邻的上表面，或所述第二连接盘与所述至少一侧的侧壁及相邻的上表面。
在本申请实施例中，第二连接盘至少一侧的侧壁在横向上超出所述第一连接盘的侧壁，此时，可以令垂直通孔至少暴露第二连接盘的与超出第一连接盘的侧壁相邻的上表面，以实现接触塞和第二连接盘的接触，当然，垂直通孔还可以暴露第二连接盘的与超出第一连接盘的侧壁，从而能够在一定程度上提高接触塞和第二连接盘的接触可靠性，从而调高第一连接盘和第二连接盘的电连接的可靠性。
作为一种可能的实施方式，所述垂直通孔暴露所述第一连接盘的侧壁；或在所述垂直通孔中，所述第一连接盘的侧壁保留有第一介质层。
在本申请实施例中，垂直通孔可以暴露第一连接盘的侧壁，则可以提高垂直通孔中形成的接触塞与第一连接盘的接触可靠性，当然，垂直通孔中也可以不暴露第一连接盘的侧壁，而是在刻蚀过程中保留第一连接盘侧壁的第一介质层，这样，第一介质层可以对第一连接盘的侧壁构成保护，从而提高第一连接盘的结构完整性，进而提高第一连接盘的功能完整性。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，所述第二连接盘至少一侧的侧壁与所述第一连接盘的侧壁齐平，则所述垂直通孔暴露所述第二连接盘的至少一侧侧壁，以及与所述第二连接盘齐平的所述第一连接盘侧壁。
在本申请实施例中，第二连接盘至少一侧的侧壁与所述第一连接盘的侧壁齐平，此时，可以利用垂直通孔暴露第一连接盘和第二连接盘的侧壁，从而利用接触赛连接第一连接盘和第二连接盘的侧壁，以实现第一连接盘和第二连接盘的电连接，减少垂直互连结构的冗余横向面积，从而减小器件面积，提高器件集成度。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向交错设置，所述垂直通孔的顶部开口处的尺寸大于或等于所述第二连接盘与所述第一连接盘的横向距离。
在本申请实施例中，第二连接盘和第一连接盘可以纵向交错设置，此时第一连接盘和第二连接盘在纵向上没有重叠的区域，且在横向上有横向距离，则垂直通孔在顶部开口处的尺寸可以大于或等于第二连接盘和第一连接盘的横向距离，从而顺利暴露第一连接盘和第二连接盘，以实现二者的电连接，提高电连接的可靠性。
作为一种可能的实施方式，半导体器件还包括：第三晶圆；
所述第三晶圆中具有第三连接盘；所述第三晶圆和所述第一晶圆键合，以实现所述第三连接盘与所述接触塞的电连接。
在本申请实施例中，半导体器件还可以包括第三晶圆，第三晶圆中的第三连接盘可以通过与接触塞电连接而与第一晶圆以及第二晶圆连接，具体的，第三晶圆可以和第一晶圆 键合，从而进一步提高器件的集成度。
作为一种可能的实施方式，所述垂直通孔贯穿于所述第一连接盘的多侧侧壁方向。
本申请实施例中，垂直通孔可以贯穿于第一连接盘的多侧侧壁方向，这样在垂直通孔中形成的接触塞可以在多侧包围第一连接盘，从而提高接触塞与第一连接盘的接触可靠性，也能在一定程度上增大接触塞和第二连接盘的接触面积，进行提高接触塞与第二连接盘的接触可靠性。
本申请实施例的第二方面，提供了一种半导体器件的制造方法，包括：
提供完成键合的第一晶圆和第二晶圆；所述第一晶圆中包括第一介质层，所述第一介质层中具有第一连接盘；所述第二晶圆中包括第二介质层，所述第二介质层中具有第二连接盘；
以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，所述垂直通孔贯穿所述第一晶圆至所述第一连接盘的上表面，且沿所述第一连接盘的侧壁贯穿所述第二晶圆至所述第二连接盘，并暴露所述第二连接盘的上表面和/或侧壁；
在所述垂直通孔填充导电材料，以形成接触塞，所述接触塞用于实现所述第一连接盘和所述第二连接盘的电连接。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，则所述以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
从所述第一晶圆的上表面进行刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
在所述第一开口的侧壁在横向上超出所述第一连接盘的位置底部刻蚀形成第二开口；
以所述第一连接盘为阻挡层，一并加深所述第一开口和所述第二开口，以使加深后的所述第一开口暴露所述第一连接盘的上表面，使加深后的所述第二开口暴露所述第二连接盘的上表面和/或侧壁。
作为一种可能的实施方式，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁在横向上超出所述第一连接盘的侧壁，加深后的所述第二开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁与所述第一连接盘的侧壁齐平，则加深后的所述第二开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
作为一种可能的实施方式，所述第二连接盘的侧壁在横向上超出所述第一连接盘的侧壁的方向上，加深后的所述第二开口中所述第一连接盘侧壁保留有第一介质层。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，所述第一介质层中具有第三开口；则所述以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
从所述第一晶圆的上表面刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
以所述第一连接盘为阻挡层，刻蚀所述第一开口底部的第一介质层和第二介质层，以 使加深后的所述第一开口和所述第三开口连通，且刻蚀过程中加深所述第三开口；加深后的所述第一开口暴露所述第一连接盘的上表面，加深后的所述第三开口暴露所述第二连接盘的上表面和/或侧壁。
作为一种可能的实施方式，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁在横向上超出所述第一连接盘的侧壁，加深后的所述第三开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁与所述第一连接盘的侧壁齐平，则加深后的所述第三开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
作为一种可能的实施方式，所述第二连接盘的侧壁在横向上超出所述第一连接盘的侧壁的方向上，加深后的所述第三开口中所述第一连接盘侧壁保留有第一介质层。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，则所述以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
从所述第一晶圆的上表面进行刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
以所述第一连接盘为阻挡层，加深所述第一开口，以使加深后的所述第一开口暴露所述第一连接盘的上表面，以及所述第二连接盘的上表面和/或侧壁。
作为一种可能的实施方式，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁在横向上超出所述第一连接盘的侧壁，加深后的所述第一开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的方向上，所述第二连接盘的至少一侧侧壁与所述第一连接盘的侧壁齐平，则加深后的所述第一开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
作为一种可能的实施方式，所述第二连接盘与所述第一连接盘纵向正对设置，则所述以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
从所述第一晶圆的上表面刻蚀得到第四开口；所述第四开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
以所述第一连接盘为阻挡层，在所述第一连接盘上方和所述第四开口的底部进行刻蚀，以暴露所述第一连接盘的上表面，加深后的所述第四开口暴露所述第二连接盘的上表面和/或侧壁。
作为一种可能的实施方式，所述第四开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁在横向上超出所述第一连接盘的侧壁，加深后的所述第四开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
和/或，所述第四开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的至少一侧侧壁与所述第一连接盘的侧壁齐平，则加深后的所述第四开口暴露所述 第二连接盘的与所述第一连接盘齐平的侧壁。
作为一种可能的实施方式，所述在所述垂直通孔填充导电材料，以形成接触塞，包括：
利用电镀或沉积工艺在所述垂直通孔内，以及所述第一晶圆的上表面形成导电材料；
利用平坦化工艺去除所述第一晶圆的上表面的导电材料，以形成所述垂直通孔内的接触塞。
相较于现有技术，本申请具有以下有益效果：
基于以上技术方案可知，本申请提供了一种半导体器件及其制造方法，半导体器件可以包括第一晶圆、第二晶圆和接触塞，第一晶圆中可以包括第一介质层，第一介质层中具有第一连接盘，第二晶圆和第一晶圆键合，第二晶圆包括第二介质层，第二介质层中具有第二连接盘，接触塞为填充于垂直通孔中的导电材料，用于电连接第一连接盘和第二连接盘，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆且部分贯穿第二晶圆至第二连接盘的上表面和/或侧壁的通孔，第一连接盘位于垂直通孔中且位于第一连接盘之下的第一介质层未被刻蚀。也就是说，垂直通孔可以暴露第一晶圆的上表面，以及第二连接盘的上表面和/或侧壁，这样垂直通孔中的接触塞可以同时与第一连接盘和第二连接盘接触，从而实现第一连接盘和第二连接盘的电连接，接触塞作为第一连接盘和第二连接盘之间的信号传输通道，其路径较短，减小了信号延迟，同时垂直通孔利用刻蚀工艺形成，从第一连接盘的侧壁贯穿至第二连接盘，其中的接触塞可以从第一连接盘的周围与第二连接盘接触，从而利用简单的工艺实现接触塞与第二连接盘的可靠连接。此外，本申请实施例中仅存在一个金属塞，无需考虑两个金属塞之间的距离，因此可以在一定程度上缩小横向尺寸，减小器件尺寸，提高器件的集成度。
附图说明
为了清楚地理解本申请的具体实施方式，下面将描述本申请具体实施方式时用到的附图做一简要说明。显而易见地，这些附图仅是本申请的部分实施例。
图1为现有技术中一种键合结构示意图；
图2为现有技术中三维互连结构的俯视图；
图3为本申请实施例提供的一种半导体器件的结构示意图；
图4为本申请实施例中第一连接盘和第二连接盘的一种形状示意图；
图5为本申请实施例提供的一种半导体器件的结构示意图；
图6为本申请实施例提供的另一种半导体器件的结构示意图；
图7为本申请实施例提供的又一种半导体器件的结构示意图；
图8为本申请实施例提供的三维互连结构的结构示意图；
图9为本申请实施例提供的三维互连结构的俯视图；
图10为本申请实施例提供的再一种半导体器件的结构示意图；
图11为本申请实施例中第一连接盘和第二连接盘的另一种形状示意图；
图12为本申请实施例提供的又一种半导体器件的结构示意图；
图13为本申请实施例提供的又一种半导体器件的结构示意图；
图14为本申请实施例提供的还一种半导体器件的结构示意图；
图15为本申请实施例提供的一种半导体器件的制造方法的流程图；
图16-图20为本申请实施例中在半导体器件的制造过程中的半导体器件的示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
其次，本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
有鉴于此，本申请提供了一种半导体器件及其制造方法，以减小信号延迟以及占用的面积，提高器件的集成密度。
正如背景技术中的描述，三维堆叠技术可以将不同晶圆键合在一起，减小三维器件的平面空间，提高集成密度。
举例来说，参考图1所示，为现有技术中一种键合结构示意图，第一晶圆100中可以形成第一器件130，第一器件130例如可以为CIS，第二晶圆200中可以形成第二器件230，第二器件230例如可以为图像系统处理器(image system processor，ISP)，而后将第一晶圆100和第二晶圆200键合在一起，构成影像传感器系统。第一器件形成于衬底110上的介质层120中，第二器件形成于衬底210上的介质层220中，键合后的第一晶圆100和第二晶圆200之间构成键合面1001。
具体的，可以将第一晶圆100和第二晶圆200进行介质层键合，并采用硅通孔技术，从第一晶圆100的衬底110进行刻蚀，形成贯穿至CIS的硅通孔以及贯穿至ISP的硅通孔，在两个硅通孔中形成金属材料后，得到两个分别与CIS和ISP连接的金属塞140、240，金属塞140、240可以实现键合结构中信号的在竖直方向的传递，而后在第一晶圆100的衬底110背面形成水平再布线层(redistribution layer，RDL)150以实现两个金属塞140、240的电连接，这样CIS和ISP通过两个金属塞140、240和再布线层150实现电连接，即不同层晶圆之间实现三维互连。
然而，利用介质层键合以及硅通孔技术连接的方式中，第二晶圆200中ISP的信号需要先通过连接ISP的金属塞240向上传递，再经过水平再布线层150传递到与ISP连接的金属塞140后向下传递，才能到达第一晶圆100中的CIS中，参考图1中虚线指示方向，也就是说，信号需要经过较长的π型路径，而延迟时间和路径中的电阻和电容相关，导致信号传递的延迟时间较长，在一些场景下不能满足实际需要。同时，需要两个金属塞才能实现CIS和ISP之间的连接，参考图2所示，为现有技术中三维互连结构的俯视图，其中，两个金属塞140、240的尺寸的最小值有一定限制，两个金属塞140、240在形成过程中的最小距离也有一定的限制，这就决定了两个金属塞140、240的设置需要较大的平面空间，相应的，与两个金属塞140、240接触的第一器件130和第二器件140的连线层也不能太靠 近，因此这种连接方式不利于器件的集成密度。
基于以上技术问题，本申请实施例提供了一种半导体器件及其制造方法，半导体器件可以包括第一晶圆、第二晶圆和接触塞，第一晶圆中可以包括第一介质层，第一介质层中具有第一连接盘，第二晶圆和第一晶圆键合，第二晶圆包括第二介质层，第二介质层中具有第二连接盘，接触塞为填充于垂直通孔中的导电材料，用于电连接第一连接盘和第二连接盘，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆且部分贯穿第二晶圆至第二连接盘的上表面和/或侧壁的通孔，第一连接盘位于垂直通孔中且位于第一连接盘之下的第一介质层未被刻蚀。也就是说，垂直通孔可以暴露第一晶圆的上表面，以及第二连接盘的上表面和/或侧壁，这样垂直通孔中的接触塞可以同时与第一连接盘和第二连接盘接触，从而实现第一连接盘和第二连接盘的电连接，接触塞作为第一连接盘和第二连接盘之间的信号传输通道，其路径较短，减小了信号延迟，同时垂直通孔利用刻蚀工艺形成，从第一连接盘的侧壁贯穿至第二连接盘，其中的接触塞可以从第一连接盘的周围与第二连接盘接触，从而利用简单的工艺实现接触塞与第二连接盘的可靠连接。此外，本申请实施例中仅存在一个金属塞，无需考虑两个金属塞之间的距离，因此可以在一定程度上缩小横向尺寸，减小器件尺寸，提高器件的集成度。
为了更清楚地理解本申请的具体实施方式，下面结合附图对本申请提供的半导体器件进行详细描述。
参考图3所示，为本申请实施例提供的一种半导体器件的结构示意图，其中，该半导体器件可以包括第一晶圆300、第二晶圆400以及实现第一晶圆300和第二晶圆400的垂直互连的接触塞360。第一晶圆300可以包括第一衬底310、第一衬底310上的第一介质层320以及第一介质层320中的第一连接盘330，第二晶圆400可以包括第二衬底410、第二衬底410上的第二介质层420以及第二介质层420中的第二连接盘430。
其中，第一衬底310和第二衬底410可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium On Insulator)等。在其他实施例中，第一衬底310和第二衬底410还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其他外延结构，例如SGOI(绝缘体上锗硅)等。第一衬底310和第二衬底410可以是相同的材料，也可以是不同的材料。在本实施例中，第一衬底310和第二衬底410可以均为硅衬底。
第一衬底310和第二衬底410上可以已经完成键合之前的所有工艺，例如第一衬底310和第二衬底410上已经形成有器件结构以及电连接器件结构的互连结构，器件结构由层间介质层覆盖，层间介质层可以为氧化硅，互连结构形成于介质材料中，器件结构可以为MOS器件、存储器件和/或其他无源器件，互连结构可以为多层结构，互连结构可以包括接触塞、过孔或连接层，连接层可以位于互连结构的顶层，作为互连结构的引出结构，连接层可以包括多个连接盘。互连结构可以为金属材料，例如可以为钨、铝、铜等。在本申请实施例的图示中，仅图示出顶层的连接层，此处仅是为了简化附图，可以理解的是，此处仅为示例，在不同的设计和应用中，可以根据需要形成所需层数的互连结构。
第一衬底310和第二衬底410上可以形成有相同的器件结构，也可以形成有不同的器件结构，举例来说，第一衬底310和第二衬底410上的器件可以均为DRAM器件，或者均为逻辑器件，也可以分别为DRAM和逻辑器件中的两种器件，还可以分别为SRAM和逻辑器件中的两种器件，或者分别为CIS与ISP中的两种器件等等。
第一衬底310和第二衬底410上可以形成有相同的互连结构，也可以形成有不同的互连结构，第一衬底310和第二衬底410上的互连结构中的连接盘可以具有相同的结构，也可以具有不同的结构。为了便于区分，本申请实施例以第一衬底310上的互连结构中的第一连接盘330和第二衬底410上的互连结构中的第二连接盘430为例，说明不同晶圆之间的互连结构。
第一连接盘330为第一晶圆300在键合之前互连结构中的连接盘，可以为第一晶圆300中的顶层金属层(top metal)，第一连接盘330的材料可以为金属铜。第一连接盘330可以被第一介质层320覆盖，从而实现不同第一连接盘330之间的隔离，第一介质层320可以为氧化硅层，也可以是叠层结构，例如可以包括氮化硅层及其上的氧化硅层。
类似的，第二连接盘430为第二晶圆400在键合之前互连结构中的连接盘，可以为第二晶圆400中的顶层金属层，第二连接盘430的材料可以为金属铜。第二连接盘430可以被第二介质层420覆盖，从而实现不同第二连接盘430之间的隔离，第二介质层420可以为氧化硅，也可以是叠层结构，例如可以包括氮化硅层及其上的氧化硅层。
为了便于描述，第一衬底310上形成器件结构的表面作为第一晶圆300的正面，与第一衬底310形成器件的表面相对的表面则为第一晶圆300的背面，第二衬底410上形成器件结构的表面作为第二晶圆400的正面，与第二衬底410形成器件的表面相对的表面则为第二晶圆400的背面。
本申请实施例中，第一晶圆300和第二晶圆400可以键合在一起，事实上，第一晶圆300和第二晶圆400可以是多个键合晶圆中的两个晶圆，第一晶圆300的正面可以和第二晶圆400的正面相对键合，第一晶圆300的正面也可以和第二晶圆400的背面相对键合，第一晶圆300的背面也可以和第二晶圆400的正面相对键合，第一晶圆300的背面也可以和第二晶圆400的背面相对键合。第一晶圆300和第二晶圆400用于键合的表面为键合面，键合面可以形成有用于键合的材料层，键合材料层可以为介质材料的粘合层，例如氧化硅、氮化硅，通过粘合层之间的分子力实现两个晶圆的键合。
需要说明的是，本申请实施例中，“上”和“下”是相对的，与第一晶圆300和第二晶圆的键合方式相关。具体的，第一晶圆300可以作为上晶圆，第二晶圆400可以作为下晶圆，而第一晶圆300的正面作为键合面时，第一晶圆300经过了翻转，则原来的“上”变为了“下”，而第一晶圆300的背面作为键合面时，第一晶圆300并未经过翻转，则原来的“上”依然为“上”，同理，第二晶圆400的正面作为键合面时，第二晶圆400并未经过翻转，则原来的“上”依然为“上”，而第二晶圆400的背面作为键合面时，第二晶圆经过了翻转，则原来的“上”变为了“下”。此外，上、下、左、右、前、后、顶、底等描述仅仅是为了方便反映各个部件之间的相对位置和/或方向的，并不暗示任何具体的固定方向。
在第一晶圆300和第二晶圆400键合之后，由于二者通过介质层键合，第一晶圆300中的第一连接盘330和第二晶圆400中的第二连接盘430还未实现电连接，因此需要通过 垂直通孔359实现第一晶圆300和第二晶圆400的连接。本申请实施例中，可以将第一晶圆300作为键合结构中的上晶圆，从而从第一晶圆300的上表面进行刻蚀，以形成垂直通孔359。可以理解的是，在第一晶圆300的背面作为键合面1001时，可以从第一晶圆300的正面进行刻蚀，在第一晶圆300的正面作为键合面1001时，可以从第一晶圆300的背面进行刻蚀。
目前，可以利用TSV技术从第一晶圆的上表面进行刻蚀，分别形成贯穿至第一连接盘和第二连接盘的两个硅通孔，而后在硅通孔中填充金属材料作为接触塞，之后再第一晶圆的上表面再布线，以建立两个接触塞之间的连接。然而，这种连接方式中，第一连接盘和第二连接盘之间的通道较长，且每个接触塞的尺寸受到刻蚀工艺的限制，不能无限减小，接触塞之间的距离也受到限制，因此这种工艺中的两个三维互连结构所占用的平面面积较大，同时，由于接触塞与第一连接盘或第二连接盘进行了接触，则第一连接盘和第二连接盘的尺寸也受到刻蚀工艺的限制，与接触塞的尺寸相匹配，因此第一连接盘和第二连接盘的尺寸较大，同时，第一连接盘和第二连接盘之间的距离与接触塞的横向距离对应，其最小距离受到限制，因此布线设计也受到限制。
为了解决上述问题，本申请实施例中，可以从第一晶圆300的上表面开始刻蚀，以第一连接盘330为阻挡层，形成一个垂直通孔359，而在这一个垂直通孔359内，暴露中第一连接盘330的上表面，以及第二连接盘430的上表面和/侧壁，第一连接盘330可以保护其下的第一介质层和第二介质层不被刻蚀，这样在垂直通孔359内填充金属后，形成的接触塞360与第一连接盘330的上表面接触，同时与第二连接盘430的上表面和/或侧壁接触，即形成的接触塞360同时与第一连接盘330和第二连接盘430接触，构成了第一连接盘330和第二连接盘430的连接。接触塞360可以在至少一侧包围第一连接盘330，对第一连接盘330的平面尺寸要求不高，因此可以进一步减少器件的平面面积。
垂直通孔359可以是上下尺寸不均匀的通孔，具体的，其可以贯穿第一晶圆至第一连接盘330的上表面，从而暴露第一连接盘330的上表面，垂直通孔359还可以沿第一连接盘330的侧壁贯穿第一晶圆和第二晶圆至第二连接盘430，从而暴露第二连接盘430的上表面和/或侧壁。也就是说，第一连接盘330上方可以具有较大的通孔尺寸，而第一连接盘330和第二连接盘430之间可以具有较小的通孔尺寸。
具体的，垂直通孔359可以暴露第一连接盘330的全部上表面，也可以暴露第一连接盘330的部分上表面；垂直通孔359可以暴露第一连接盘330的一侧或者多侧侧壁，也可以不暴露第一连接盘330的侧壁，此时第一连接盘330的侧壁被部分第一介质层覆盖，从而对第一连接盘330构成保护作用；垂直通孔359可以暴露第二连接盘430的全部上表面，也可以暴露第二连接盘430的部分上表面；垂直通孔359可以暴露第二连接盘430的一侧或者多侧侧壁，也可以不暴露第二连接盘430的侧壁，此时第二连接盘430的侧壁被第二介质层覆盖。
参考图4所示，为本申请实施例中第一连接盘和第二连接盘的一种形状示意图，第一连接盘330可以为多边形或圆形，第二连接盘430可以为多边形或圆形，第一连接盘330和第二连接盘430的形状可以相同，也可以不同，当然，第一连接盘330和第二连接盘430的横向距离较近，可以在纵向上有重叠的投影，也可以在纵向上没有重叠的投影。多边形 例如可以为条形，圆形例如可以为正圆形或椭圆形，作为一种示例，第一连接盘330为条形，第二连接盘430也为条形，第一连接盘330和第二连接盘430的尺寸可以相同，也可以不同。
作为一种可能的实施方式，参考图5所示，为本申请实施例提供的一种半导体器件的结构示意图，第二连接盘430与第一连接盘330可以在纵向上正对设置，也就是说，第一连接盘330与第一连接盘330在垂直于键合面1001的方向上有重叠区域，并且第二连接盘430的侧壁与第一连接盘330的侧壁至少有一侧齐平，这样垂直通孔359中可以暴露第二连接盘430和第一连接盘330的侧壁，暴露出的第二连接盘430和第一连接盘330的侧壁齐平，这样在垂直通孔359中填充的接触塞360分别与第二连接盘430的侧壁以及第一连接盘330的侧壁连接，从而可以电连接第一连接盘330和第二连接盘430。具体来说，第二连接盘430与第一连接盘330可以有一侧对齐，第一连接盘330有一侧侧壁在横向上超出第二连接盘430的侧壁，接触塞360可以接触第一连接盘330的上表面和一侧侧壁，以及第二连接盘430的一侧侧壁，参考图5(a)所示；第二连接盘430与第一连接盘330可以有多侧对齐，接触塞360可以接触第一连接盘330的上表面和多侧侧壁，以及第二连接盘430的多侧侧壁，参考图5(b)所示。
作为另一种可能的实施方式，参考图6所示，为本申请实施例提供的另一种半导体器件的结构示意图，第二连接盘430与第一连接盘330可以在纵向上正对设置，并且第二连接盘430的至少一侧侧壁在横向上超出第一连接盘330的侧壁，则形成的垂直通孔359内至少暴露第二连接盘430在横向上超出第一连接盘330一侧的部分表面，即可以暴露第二连接盘430的在横向上超出第一连接盘330的侧壁相邻的上表面，也可以暴露第二连接盘430在横向上超出第一连接盘330的侧壁及其相邻的上表面，这样在垂直通孔359内填充的接触塞360至少与第二连接盘430的上表面接触。同时，垂直通孔359内还可以暴露第一连接盘330的上表面，这样接触塞360可以连接第一连接盘330和第二连接盘430。
具体的，第二连接盘430可以有一侧侧壁在横向上超出第一连接盘330。参考图6(b)所示，第二连接盘430可以有一侧侧壁与第一连接盘330对齐，另一侧侧壁在横向上超出第一连接盘330的侧壁，接触塞360可以接触第一连接盘330的上表面和多侧侧壁，以及第二连接盘430的一侧侧壁和另一侧上表面，参考图6(a)所示；参考图6(b)所示，第二连接盘430可以有一侧侧壁在横向上超出第一连接盘330，另一侧侧壁相对第一连接盘330有所凹陷，接触塞360可以接触第一连接盘330的上表面和一侧侧壁，以及第二连接盘430在横向上超出第一连接盘330的一侧的上表面，参考图6(b)所示。
具体的，第二连接盘430可以有多侧侧壁在横向上超出第一连接盘330，参考图7所示，为本申请实施例提供的另一种半导体器件的结构示意图。其中，接触塞360可以接触第一连接盘330的上表面和一侧侧壁，以及第二连接盘430在横向上超出第一连接盘330的一侧的上表面，参考图7(a)所示；接触塞360可以接触第一连接盘330的上表面和多侧侧壁，以及第二连接盘430的上表面，参考图7(b)和图3所示；接触塞360可以接触第一连接盘330的上表面和多侧侧壁，以及第二连接盘430的上表面和多侧侧壁，参考图7(c)所示。
当然，以上示例中，接触塞360和第一连接盘330之间也可以保留有部分第一介质层， 从而在刻蚀过程中对第一连接盘330构成保护。
综上，本申请实施例中，接触塞360可以从第一连接盘330的多侧连接第一连接盘330和第二连接盘430，在一定程度上提高接触塞360与第二连接盘430的接触面积，提高接触塞360和第二连接盘430的接触可靠性。
参考图8所示，为本申请实施例提供的三维互连结构的结构示意图，参考图9所示，为本申请实施例提供的三维互连结构的俯视图，接触塞360构成拱门结构，实现与第一连接盘330和第二连接盘430的连接，其中，接触塞360形成于第一连接盘330的左右两侧，则第一连接盘330的左右向宽度可以较小，同时，第一连接盘330和第二连接盘430可以有重叠区域，而不必设置较大的间距，从而可以在一定程度上降低布线面积。
作为再一种可能的实施方式，参考图10所示，为本申请实施例提供的再一种半导体器件的结构示意图，第二连接盘430与第一连接盘330在纵向上交错设置，即第二连接盘430和第一连接盘330在垂直于键合面1001的方向上没有重叠区域，因此，垂直通孔359的顶部开口处的尺寸大小大于或等于第二连接盘430和第一连接盘330的横向距离。具体的，在垂直通孔359的顶部开口处的尺寸等于第二连接盘430和第一连接盘330的横向距离时，垂直通孔359可以暴露第一连接盘330和第二连接盘430的相对的侧壁，即暴露第一连接盘330的朝向第二连接盘430的侧壁，暴露第二连接盘430的朝向第一连接盘330的侧壁，则在垂直通孔359的不同深度，其横向尺寸均匀，从而在垂直通孔359中的金属塞360可以连接暴露出的第一连接盘330和第二连接盘430的侧壁，实现二者的电连接；在垂直通孔359的顶部开口处的尺寸可以大于第二连接盘430和第一连接盘330的横向尺寸，则除了暴露第一连接盘330和第二连接盘430的相对的侧壁，垂直通孔359还可以暴露第一连接盘330和/或第二连接盘430的部分上表面，参考图10(a)所示，以提高接触的可靠性，事实上，在垂直通孔359暴露第一连接盘330的上表面的基础上，第一连接盘330的侧壁可以保留部分第一介质层，从而对第一连接盘330构成保护，参考图10(b)所示。
参考图11所示，为本申请实施例中第一连接盘和第二连接盘的另一种形状示意图，第一连接盘330的形状还可以为狭缝型或梳齿型，此时第二连接盘430的形状可以为多边形、圆形、狭缝型或梳齿性；当然，第一连接盘330的形状为多边形或圆形时，第二连接盘430的形状可以为狭缝型或梳齿型，狭缝型可以为单狭缝型、多狭缝型。其中，狭缝型可以包括单狭缝型，参考图11(a)，以及多狭缝型，参考图11(b)和11(c)，梳齿型参考图11(d)，梳齿型中梳齿的数量可以根据实际情况确定。
在第一连接盘330和第二连接盘430的形状为狭缝型或梳齿型时，可以将狭缝型或梳齿型看成多个线条的组合，而每个线条的连接方式可以参考以上线条之间的连接方式，即形成的垂直通孔359可以暴露该狭缝型或梳齿型的连接盘的侧壁，也可以不暴露其侧壁，只要能够同时暴露第一连接盘330和第二连接盘430的部分上表面，从而实现接触塞360分别与第一连接盘330和第二连接盘430之间的接触即可。
参考图12所示，为本申请实施例提供的又一种半导体器件的结构示意图，以第二连接盘430为单狭缝型为例，接触塞360可以与第一连接盘330的上表面和侧壁，以及第二连接盘430的上表面连接，参考图12(a)所示；接触塞360可以与第一连接盘330的上表面和侧壁，以及第二连接盘430的上表面和侧壁连接，参考图12(b)所示。以第二连接盘 430为双狭缝为例，接触塞360可以与第一连接盘330的上表面和侧壁，以及第二连接盘430的侧壁连接，参考图12(c)所示。
也就是说，垂直通孔359可以是从第一晶圆300的上表面贯穿至第一连接盘330的上表面，从第一连接盘330的周围贯穿至第二连接盘430的上表面的通孔，该通孔中暴露第一连接盘330的上表面，以及第二连接盘430的上表面和/或侧壁，从而形成上部尺寸较大而下部尺寸较小的垂直通孔359。
在本申请实施例中，由于受到刻蚀工艺影响，一个界面上方和下方的垂直通孔359尺径可以不同，参考图13所示，为本申请实施例提供的又一种半导体器件的结构示意图。具体的，第一衬底310与第一介质层320中的垂直通孔359尺径可以不同，参考图3所示；第一连接盘330的上表面以上和以下的垂直通孔359尺径可以不同，参考图13(a)和13(c)所示；第一连接盘330的下表面以上和以下的垂直通孔359尺径可以不同，参考图13(b)所示；第二连接盘430的上表面以上和以下的垂直通孔359尺径可以不同，参考图12(b)所示。
可以理解的是，以上附图仅为示例性说明，并不能包括本申请实施例提供的所有情形，为了简要，在此不做一一举例说明，本领域技术人员可以基于以上描述设置其他结构，其应该在本申请的保护范围之内。
在本申请实施例提供的半导体器件中，还可以包括第三晶圆，参考图14所示，为本申请实施例提供的还一种半导体器件的结构示意图，第一晶圆300、第二晶圆400和第三晶圆500构成三层堆叠。第三晶圆500可以包括第三衬底510，第三衬底510上可以形成第三介质层520，第三介质层520中可以具有第三连接盘530，第三晶圆500可以设置于第一晶圆300之上，第三晶圆500中的第三连接盘530和接触塞360通过第一晶圆300和第三晶圆500的键合实现电连接，第三连接盘530和接触塞360，也可以通过第一晶圆300和第三晶圆500的介质层键合后，利用与接触塞360类似的制造工艺形成其他接触塞从而连接(图未示出)，第一晶圆300和第三晶圆500的键合面5001可以参考图14所示。
本申请实施例提供了一种半导体器件，包括第一晶圆、第二晶圆和接触塞，第一晶圆中可以包括第一介质层，第一介质层中具有第一连接盘，第二晶圆和第一晶圆键合，第二晶圆包括第二介质层，第二介质层中具有第二连接盘，接触塞为填充于垂直通孔中的导电材料，用于用于电连接第一连接盘和第二连接盘，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆且部分贯穿第二晶圆至第二连接盘的上表面和/或侧壁的通孔，第一连接盘位于垂直通孔中且位于第一连接盘之下的第一介质层未被刻蚀，这样，在垂直通孔中的接触塞可以通过与第一连接盘的上表面，以及第二连接盘的上表面和/或侧壁接触，实现第一连接盘和第二连接盘的电连接，从而实现第一晶圆和第二晶圆的垂直互连。接触塞作为第一连接盘和第二连接盘之间的信号传输通道，其路径较短，减小了信号延迟，同时垂直通孔利用刻蚀工艺形成，从第一连接盘的侧壁贯穿至第二连接盘，其中的接触塞可以从第一连接盘的周围与第二连接盘接触，从而利用简单的工艺实现接触塞与第二连接盘的可靠连接。此外，本申请实施例中仅存在一个金属塞，无需考虑两个金属塞之间的距离，因此可以在一定程度上缩小横向尺寸，减小器件尺寸，提高器件的集成度。
基于以上实施例提供的半导体器件，本申请实施例还提供了一种半导体器件的制造方法，参考图15所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，图16-图20所示为本申请实施例中在半导体器件的制造过程中的半导体器件的示意图，该方法可以包括以下步骤：
S101，提供完成键合的第一晶圆300和第二晶圆400，参考图16(a)、17(a)18(a)、19(a)和20(a)。
本申请实施例中，第一晶圆300可以包括第一衬底310、第一衬底310上的第一介质层320以及第一介质层320中的第一连接盘330，第二晶圆400可以包括第二衬底410、第二衬底410上的第二介质层420以及第二介质层420中的第二连接盘430。第一衬底310和第二衬底410上可以形成有相同的器件结构，也可以形成有不同的器件结构，举例来说，第一衬底310和第二衬底410上的器件可以均为DRAM器件，或者均为逻辑器件，也可以分别为DRAM和逻辑器件中的两种器件，还可以分别为SRAM和逻辑器件中的两种器件，或者分别为CIS与ISP中的两种器件等等。
第一连接盘330为第一晶圆300在键合之前互连结构中的连接盘，可以为第一晶圆300中的顶层金属层(top metal)，第一连接盘330的材料可以为金属铜。第一连接盘330可以被第一介质层320覆盖，从而实现不同第一连接盘330之间的隔离，第一介质层320可以为氧化硅层，也可以是叠层结构，例如可以包括氮化硅层及其上的氧化硅层。
类似的，第二连接盘430为第二晶圆400在键合之前互连结构中的连接盘，可以为第二晶圆400中的顶层金属层，第二连接盘430的材料可以为金属铜。第二连接盘430可以被第二介质层420覆盖，从而实现不同第二连接盘430之间的隔离，第二介质层420可以为氧化硅，也可以是叠层结构，例如可以包括氮化硅层及其上的氧化硅层。
为了便于描述，第一衬底310上形成器件结构的表面作为第一晶圆300的正面，与第一衬底310形成器件的表面相对的表面则为第一晶圆300的背面，第二衬底410上形成器件结构的表面作为第二晶圆400的正面，与第二衬底410形成器件的表面相对的表面则为第二晶圆400的背面。
本申请实施例中，第一晶圆300和第二晶圆400可以键合在一起，实施上，第一晶圆300和第二晶圆400可以是多个键合晶圆中的两个晶圆，第一晶圆300的正面可以和第二晶圆400的正面相对键合，第一晶圆300的正面也可以和第二晶圆400的背面相对键合，第一晶圆300的背面也可以和第二晶圆400的正面相对键合，第一晶圆300的背面也可以和第二晶圆400的背面相对键合。第一晶圆300和第二晶圆400用于键合的表面可以形成有用于键合的材料层，键合材料层可以为介质材料的粘合层，例如氧化硅、氮化硅，通过粘合层之间的分子力实现两个晶圆的键合。
在第一晶圆300和第二晶圆400键合之后，由于二者通过介质层键合，第一晶圆300中的第一连接盘330和第二晶圆400中的第二连接盘430还未实现垂直互连，因此需要进行二者的连接。
S102，以第一连接盘330为阻挡层，对第一晶圆300从上至下进行刻蚀形成垂直通孔359，垂直通孔359贯穿第一晶圆第一连接盘330的上表面，且沿着第一连接盘330的侧壁贯穿第一晶圆和第二晶圆至第二连接盘430，并暴露第二连接盘430的上表面和/或侧壁。
本申请实施例中，可以将第一晶圆300作为键合结构中的上晶圆，从而从第一晶圆300的上表面进行刻蚀，以形成垂直通孔359。可以理解的是，在第一晶圆300的背面作为键合面1001时，可以从第一晶圆300的正面进行刻蚀，在第一晶圆300的正面作为键合面1001时，可以从第一晶圆300的背面进行刻蚀。
具体的，垂直通孔359可以暴露第一连接盘330的全部上表面，也可以暴露第一连接盘330的部分上表面；垂直通孔359可以暴露第一连接盘330的一侧或者多侧侧壁，也可以不暴露第一连接盘330的侧壁，此时第一连接盘330的侧壁被部分第一介质层覆盖，从而对第一连接盘330构成保护作用；垂直通孔359可以暴露第二连接盘430的全部上表面，也可以暴露第二连接盘430的部分上表面；垂直通孔359可以暴露第二连接盘430的一侧或者多侧侧壁，也可以不暴露第二连接盘430的侧壁，此时第二连接盘430的侧壁被第二介质层覆盖。
下面以第一晶圆300的正面和第二晶圆400的键合为例进行说明，刻蚀形成垂直通孔359的方式有多种，不同的垂直通孔359结构、不同的连接盘可以有不同的刻蚀方式，以下进行示例性说明。
作为一种可能的实施方式，第二连接盘430与第一连接盘330纵向正对设置，第二连接盘430位于第一连接盘330下方，且第二连接盘430可以有侧壁与第一连接盘330的侧壁齐平，也可以有侧壁在横向上超出第一连接盘330的侧壁，形成垂直通孔359的方式可以具体为：先对第一晶圆的上表面进行刻蚀形成第一开口，第一开口位于第一连接盘330的上方，且第一开口的至少一侧侧壁可以在横向上超出第一连接盘330的侧壁，这样对第一开口进行加深可以暴露第一连接盘330，对第一开口的底部在横向上超出第一连接盘330的侧壁的位置进行刻蚀，可以在第一连接盘330的外围形成贯穿至第二连接盘430的第二开口，从而形成垂直通孔359。而在刻蚀形成贯穿至第二连接盘430的开口时，第一连接盘330可以保护其下的第一介质层和第二介质层。通常来说，第二开口的位置可以根据第二连接盘430相对于第一连接盘330的位置确定，第二连接盘430的侧壁在横向上超出第一连接盘330的侧壁的方向可以与第二开口的侧壁在横向上超出第一连接盘330的侧壁的方向一致。
参考图16所示，第二连接盘430的侧壁在多侧在横向上超出第一连接盘330的侧壁。首先，可以从第一晶圆300的背面进行刻蚀，即从第一衬底310的背面进行刻蚀，形成第一开口350，参考图16(b)所示，第一开口350可以在第一连接盘330的上方，且第一开口350的侧壁在多侧在横向上超出第一连接盘330的侧壁，对第一开口350的刻蚀可以停止在第一衬底310的下表面位置，也可以过刻蚀部分第一介质层320(图未示出)而停止在第一介质层320中；沉积绝缘层361以保护第一开口350的侧壁；在第一开口350的侧壁在横向上超出第一连接盘330位置底部进行刻蚀(此次刻蚀可以暴露第一连接盘330的侧壁，也可以保留部分第一介质层320而不暴露第一连接盘330的侧壁)，形成贯穿至键合面1001的第二开口351，参考图16(c)所示；之后以第一连接盘330为阻挡层，一并加深第一开口350和第二开口351，从而去除第一连接盘330上方的第一介质层320，以及第二连接盘430上方的第二介质层420，从而形成垂直通孔359，参考图16(d)所示，形成的垂直通孔359暴露出第一连接盘330的上表面，以及第二连接盘430在横向上超出第一 连接盘330的多侧的部分上表面。其中，保留第一连接盘330侧壁上的部分第一介质层320，有利于对第一连接盘330进行保护，避免第一连接盘330被刻蚀造成的损伤或倒塌。
此外，在第二连接盘430在横向上超出第一连接盘330的尺寸较小时，可以一并刻蚀去除第二连接盘430侧壁的第二介质层，以暴露第二连接盘430的侧壁。参考图17所示，从第一晶圆300的背面进行刻蚀，即从第一衬底310的背面进行刻蚀，形成第一开口350，参考图17(b)所示，当然，对第一开口350的刻蚀可以停止在第一衬底310的下表面位置，也可以过刻蚀部分第一介质层320(图未示出)而停止在第一介质层320中；沉积绝缘层361以保护第一开口350的侧壁，参考图17(c)所示；在第一开口350的侧壁在横向上超出第一连接盘330位置底部进行刻蚀，以形成贯穿至键合面1001的第二开口351，参考图17(c)所示；之后以第一连接盘330为阻挡层，一并加深第一开口350和第二开口351，使加深后的第二开口351停止于第二连接盘430的下表面，刻蚀过程中，第一连接盘330可以保护其下的第一介质层和第二介质层，从而形成垂直通孔359，垂直通孔359暴露第一连接盘330的上表面，以及第二连接盘430在横向上超出第一连接盘330的多侧的部分上表面以及侧壁。
此外，在第二连接盘430与第一连接盘330齐平的方向，可以刻蚀去除第一连接盘330和第二连接盘430侧壁的介质层，以暴露第一连接盘330和第二连接盘430的侧壁。具体的操作步骤，可以参考图16所示的步骤，这里不再赘述。
作为另一种可能的实施方式，第二连接盘430与第一连接盘330纵向正对设置，第二连接盘430位于第一连接盘330下方，且第二连接盘430可以有侧壁与第一连接盘330的侧壁齐平，也可以有侧壁在横向上超出第一连接盘330的侧壁，可以在晶圆键合之前，在第一晶圆中形成第三开口，第三开口形成于第一连接盘330周围的第一介质层中，这样可以减小键合后的刻蚀负载。形成垂直通孔的方式可以具体为：在晶圆键合后，对第一晶圆的上表面进行刻蚀形成第一开口，第一开口位于第一连接盘330的上方，且第一开口的侧壁可以至少一侧在横向上超出第一连接盘330的侧壁，这样对第一开口进行加深可以暴露第一连接盘330，同时可以连通第一开口和第三开口，并且可以对第三开口进行加深，加深后的第三开口可以暴露第二连接盘430，形成垂直通孔359。在刻蚀形成贯穿至第二连接盘430的开口时，第一连接盘330可以保护其下的第一介质层和第二介质层。通常来说，第三开口的位置可以根据第二连接盘430相对于第一连接盘330的位置确定，第二连接盘430的侧壁在横向上超出第一连接盘330的侧壁的方向可以与第三开口在第一介质层中的设置方向一致。
参考图18所示，第二连接盘430的侧壁在多侧在横向上超出第一连接盘330的侧壁，第一晶圆300中可以形成有第三开口352，第三开口352形成于第一连接盘330周围的第一介质层320中，即在进行第一晶圆300和第二晶圆400的键合前，可以对第一介质层320进行刻蚀，以在第一连接盘330周围形成第三开口352，参考图18(a)所示。这样，在进行晶圆的键合后，可以从第一晶圆300的背面进行刻蚀，即从第一衬底310的背面进行刻蚀，形成第一开口350，参考图18(b)所示，第一开口350可以在第一连接盘330的上方，且第一开口350的侧壁在多侧在横向上超出第一连接盘330的侧壁，当然，对第一开口350的刻蚀可以停止在第一衬底310的下表面位置，也可以过刻蚀部分第一介质层320(图未 示出)而停止在第一介质层320中；沉积绝缘层361以保护第一开口350的侧壁，参考图18(c)所示；以第一连接盘330为阻挡层，加深第一开口350以使第一开口350和第三开口352连通，而后继续刻蚀以加深第三开口352，从而使加深后的第一开口350暴露第一连接盘330的上表面，加深后的第三开口352暴露第二连接盘430的上表面，从而形成垂直通孔359，参考图18(d)所示。
此外，在第二连接盘430在横向上超出第一连接盘330的尺寸较小时，可以一并刻蚀去除第二连接盘430侧壁的第二介质层，以暴露第二连接盘430的侧壁，在此不进行举例说明。在第二连接盘430与第一连接盘330齐平的方向，可以刻蚀去除第一连接盘330和第二连接盘430侧壁的介质层，以暴露第一连接盘330和第二连接盘430的侧壁。具体的操作步骤，可以参考图18所示的步骤，这里不再赘述。
作为又一种可能的实施方式，第二连接盘430与第一连接盘330纵向正对设置，第二连接盘430位于第一连接盘330下方，且第二连接盘430可以有侧壁与第一连接盘330的侧壁齐平，也可以有侧壁在横向上超出第一连接盘330的侧壁，形成垂直通孔359的方式可以具体为：先对第一晶圆的上表面进行刻蚀形成第一开口，第一开口位于第一连接盘330的上方，且第一开口的侧壁可以至少一侧在横向上超出第一连接盘330的侧壁，这样对第一开口进行加深可以暴露第一连接盘330，继续加深第一开口，此时第一连接盘330可以保护其下的第一介质层和第二介质层，而刻蚀第一开口在横向上超出第一连接盘330的位置的第一介质层和第二介质层，从而可以在第一连接盘330的外围，加深后的第一开口贯穿至第二连接盘430，从而形成垂直通孔359。
参考图19所示，第二连接盘430的侧壁在多侧在横向上超出第一连接盘330的侧壁，从第一晶圆300的背面进行刻蚀，即从第一衬底310的背面进行刻蚀，形成第一开口350，参考图19(b)所示，第一开口350可以在第一连接盘330的上方，且第一开口350的侧壁在多侧在横向上超出第一连接盘330的侧壁，当然，对第一开口350的刻蚀可以停止在第一衬底310的下表面位置，也可以过刻蚀部分第一介质层320(图未示出)而停止在第一介质层320中；沉积绝缘层361以保护第一开口350的侧壁，参考图19(c)所示；加深第一开口350，以第二连接盘430作为刻蚀停止层，刻蚀过程中，第一连接盘330对其下的第一介质层和第二介质层形成保护作用，直到暴露第二连接盘430的上表面，此时，第一连接盘330的上表面也暴露在加深后的第一开口350中，形成垂直通孔359，参考图19(d)所示。
作为还一种可能的实施方式，第二连接盘430与第一连接盘330纵向正对设置，第二连接盘430位于第一连接盘330下方，且第二连接盘430可以有侧壁与第一连接盘330的侧壁齐平，也可以有侧壁在横向上超出第一连接盘330的侧壁，形成垂直通孔359的方式可以具体为：从第一晶圆的上表面进行刻蚀形成第四开口，第四开口的侧壁至少一侧在横向上超出第一连接盘330的侧壁，之后可以以第一连接盘330为阻挡层，在第一连接盘330上方和第四开口的底部进行刻蚀，以暴露第一连接盘330的上表面，同时加深后的第四开口暴露第二连接盘430的上表面和/或侧壁，刻蚀过程中，第一连接盘330可以保护其下的第一介质层和第二介质层。
参考图20所示，第二连接盘430的侧壁在多侧在横向上超出第一连接盘330的侧壁， 从第一晶圆300的背面进行刻蚀，即从第一衬底310的背面进行刻蚀，刻蚀的位置在第一连接盘330的周围，直到刻蚀到第一连接盘330的下表面位置或上表面位置，得到第四开口353，参考图20(b)所示；之后再沉积绝缘层361以保护第四开口353的侧壁，参考图20(c)所示；对第一连接盘330上部的第一介质层320，以及第一连接盘330周围第四开口353底部的第一介质层320和第二介质层420进行刻蚀，以暴露第一连接盘330的上表面和侧壁，以及第二连接盘430的上表面，从而形成垂直通孔359，参考图20(d)所示。
以上形成垂直通孔359的方法中，垂直通孔359刻蚀的时候利用上层晶圆的第一连接盘330作为阻挡层，直至刻蚀至下层晶圆的第二连接层430裸露出来为止，通常而言，第一连接盘330为导体材料，可以设置为与第一介质层和第二介质层具有较高刻蚀选择比的材料，例如金属材料或掺杂的半导体材料。其中，金属和介质层的刻蚀选择比较大，例如SiO2:Al趋近于20:1，SiO2:W趋近于80:1，因此不会对第一连接盘330和第二连接层430造成较大的损伤，因此第二连接层430刻蚀开之前都可以确保第一连接盘330仍然存在，直到第一介质层320和第二介质层420完全刻蚀开后，藉由下层晶圆的第二连接层430将刻蚀停住，刻蚀工艺较为简单。
S103，在垂直通孔359中填充导电材料，以形成接触塞360，参考图16(e)、17(e)、18(e)、19(e)和20(e)。
本申请实施例中，可以从第一晶圆300的上表面开始刻蚀，形成一个垂直通孔359作为垂直通孔359，而在这一个垂直通孔359内，暴露中第一连接盘330的上表面，以及第二连接盘430的上表面和/侧壁，这样在垂直通孔359内填充金属后，形成的接触塞360与第一连接盘330的上表面接触，同时与第二连接盘430的上表面和/或侧壁接触，即形成的接触塞360同时与第一连接盘330和第二连接盘430接触，实现了第一连接盘330和第二连接盘430的电连接。
在垂直通孔359中形成接触塞360，可以利用电镀或者沉积的方式在垂直通孔359中形成导电材料，而后利用平坦化工艺，例如化学机械研磨工艺，去除垂直通孔359之外的导电材料，从而形成接触塞360。接触塞360的材料可以是铜或铝，可以是其他导电金属材料或非金属材料，例如可以是掺杂的硅。
在本申请实施例提供的一种半导体器件的制造方法中，提供完成键合的第一晶圆和第二晶圆，第一晶圆中包括第一介质层，第一介质层中具有第一连接盘，第二晶圆中包括第二介质层，第二介质层中具有第二连接盘，以第一连接盘为阻挡层，从第一晶圆从上往下进行刻蚀可以形成垂直通孔，垂直通孔贯穿第一晶圆至第一连接盘的上表面，且沿第一连接盘的侧壁贯穿第二晶圆至第二连接盘，并暴露第二连接盘的上表面和/或侧壁，在垂直通孔填充导电材料，以形成接触塞，也就是说，垂直通孔可以暴露第一晶圆的上表面，以及第二连接盘的上表面和/或侧壁，这样垂直通孔中的接触塞可以同时与第一连接盘和第二连接盘接触，从而实现第一连接盘和第二连接盘的电连接，接触塞作为第一连接盘和第二连接盘之间的信号传输通道，其路径较短，减小了信号延迟，同时垂直通孔利用刻蚀工艺形成，从第一连接盘的侧壁贯穿至第二连接盘，其中的接触塞可以从第一连接盘的周围与第二连接盘接触，从而利用简单的工艺实现接触塞与第二连接盘的可靠连接。此外，本申请实施例中仅存在一个金属塞，无需考虑两个金属塞之间的距离，因此可以在一定程度上缩 小横向尺寸，减小器件尺寸，提高器件的集成度。
需要说明的是，本申请实施例中的各个实施例之间可以相互参见，对于装置实施例而言，可以参考方法实施例的说明，方法实施例部分也可以参考装置实施例的说明。
以上为本申请的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种半导体器件，其特征在于，包括：第一晶圆、第二晶圆和接触塞；
    所述第一晶圆包括第一介质层，所述第一介质层中具有第一连接盘；
    所述第二晶圆与所述第一晶圆键合，所述第二晶圆包括第二介质层，所述第二介质层中具有第二连接盘；
    所述接触塞为填充于垂直通孔中的导电材料，用于电连接所述第一连接盘和所述第二连接盘；所述垂直通孔为通过刻蚀形成的贯穿所述第一晶圆且部分贯穿所述第二晶圆至所述第二连接盘的上表面和/或侧壁的通孔，所述第一连接盘位于所述垂直通孔中且位于所述第一连接盘之下的第一介质层未被刻蚀。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述第二连接盘与所述第一连接盘纵向正对设置，所述第二连接盘至少一侧的侧壁在横向上超出所述第一连接盘的侧壁，则所述垂直通孔暴露所述第二连接盘与所述第二连接盘至少一侧的侧壁相邻的上表面，或所述第二连接盘与所述至少一侧的侧壁及相邻的上表面。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述垂直通孔暴露所述第一连接盘的侧壁；或在所述垂直通孔中，所述第一连接盘的侧壁保留有第一介质层。
  4. 根据权利要求1或2所述的半导体器件，其特征在于，所述第二连接盘与所述第一连接盘纵向正对设置，所述第二连接盘至少一侧的侧壁与所述第一连接盘的侧壁齐平，则所述垂直通孔暴露所述第二连接盘的至少一侧侧壁，以及与所述第二连接盘齐平的所述第一连接盘侧壁。
  5. 根据权利要求1所述的半导体器件，其特征在于，所述第二连接盘与所述第一连接盘纵向交错设置，所述垂直通孔的顶部开口处的尺寸大于或等于所述第二连接盘与所述第一连接盘的横向距离。
  6. 根据权利要求1-5任意一项所述的半导体器件，其特征在于，还包括：第三晶圆；
    所述第三晶圆中具有第三连接盘；所述第三晶圆和所述第一晶圆键合，以实现所述第三连接盘与所述接触塞的电连接。
  7. 根据权利要求1-6任意一项所述的半导体器件，其特征在于，所述垂直通孔贯穿于所述第一连接盘的多侧侧壁方向。
  8. 一种半导体器件的制造方法，其特征在于，包括：
    提供完成键合的第一晶圆和第二晶圆；所述第一晶圆中包括第一介质层，所述第一介质层中具有第一连接盘；所述第二晶圆中包括第二介质层，所述第二介质层中具有第二连接盘；
    以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，所述垂直通孔贯穿所述第一晶圆至所述第一连接盘的上表面，且沿所述第一连接盘的侧壁贯穿所述第二晶圆至所述第二连接盘，并暴露所述第二连接盘的上表面和/或侧壁；
    在所述垂直通孔填充导电材料，以形成接触塞，所述接触塞用于实现所述第一连接盘和所述第二连接盘的电连接。
  9. 根据权利要求8所述的方法，其特征在于，所述第二连接盘与所述第一连接盘纵向 正对设置，则所述以所述第一连接盘为阻挡层，对所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
    从所述第一晶圆的上表面进行刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
    在所述第一开口的侧壁在横向上超出所述第一连接盘的位置底部刻蚀形成第二开口；
    以所述第一连接盘为阻挡层，一并加深所述第一开口和所述第二开口，以使加深后的所述第一开口暴露所述第一连接盘的上表面，使加深后的所述第二开口暴露所述第二连接盘的上表面和/或侧壁。
  10. 根据权利要求9所述的方法，其特征在于，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧在横向上超出所述第一连接盘的侧壁，加深后的所述第二开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
    和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧与所述第一连接盘的侧壁齐平，则加深后的所述第二开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
  11. 根据权利要求10所述的方法，其特征在于，所述第二连接盘的侧壁在横向上超出所述第一连接盘的侧壁的至少一侧中，加深后的所述第二开口中所述第一连接盘侧壁保留有第一介质层。
  12. 根据权利要求8所述的方法，其特征在于，所述第二连接盘与所述第一连接盘纵向正对设置，所述第一介质层中具有第三开口；则所述以所述第一连接盘为阻挡层，在所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
    从所述第一晶圆的上表面刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
    以所述第一连接盘为阻挡层，刻蚀所述第一开口底部的第一介质层和第二介质层，以使加深后的所述第一开口和所述第三开口连通，且刻蚀过程中加深所述第三开口；加深后的所述第一开口暴露所述第一连接盘的上表面，加深后的所述第三开口暴露所述第二连接盘的上表面和/或侧壁。
  13. 根据权利要求12所述的方法，其特征在于，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧在横向上超出所述第一连接盘的侧壁，加深后的所述第三开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
    和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧与所述第一连接盘的侧壁齐平，则加深后的所述第三开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
  14. 根据权利要求13所述的方法，其特征在于，所述第二连接盘的侧壁在横向上超出所述第一连接盘的侧壁的至少一侧中，加深后的所述第三开口中所述第一连接盘侧壁保留 有第一介质层。
  15. 根据权利要求8所述的方法，其特征在于，所述第二连接盘与所述第一连接盘纵向正对设置，则所述以所述第一连接盘为阻挡层，在所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
    从所述第一晶圆的上表面进行刻蚀得到第一开口；所述第一开口位于所述第一连接盘上方，且所述第一开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
    以所述第一连接盘为阻挡层，加深所述第一开口，以使加深后的所述第一开口暴露所述第一连接盘的上表面，以及所述第二连接盘的上表面和/或侧壁。
  16. 根据权利要求15所述的方法，其特征在于，所述第一开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧在横向上超出所述第一连接盘的侧壁，加深后的所述第一开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
    和/或，所述第一开口的侧壁在横向上超出所述第一连接盘的方向上，所述第二连接盘的侧壁至少一侧与所述第一连接盘的侧壁齐平，则加深后的所述第一开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
  17. 根据权利要求8所述的方法，其特征在于，所述第二连接盘与所述第一连接盘纵向正对设置，则所述以所述第一连接盘为阻挡层，在所述第一晶圆从上往下进行刻蚀形成垂直通孔，包括：
    从所述第一晶圆的上表面刻蚀得到第四开口；所述第四开口的至少一侧侧壁在横向上超出所述第一连接盘的侧壁；
    以所述第一连接盘为阻挡层，在所述第一连接盘上方和所述第四开口的底部进行刻蚀，以暴露所述第一连接盘的上表面，加深后的所述第四开口暴露所述第二连接盘的上表面和/或侧壁。
  18. 根据权利要求17所述的方法，其特征在于，所述第四开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧在横向上超出所述第一连接盘的侧壁，加深后的所述第四开口暴露所述第二连接盘的在横向上超出所述第一连接盘的侧壁相邻的上表面，或所述第二连接盘的在横向上超出所述第一连接盘的侧壁及其相邻的上表面；
    和/或，所述第四开口的侧壁在横向上超出所述第一连接盘的侧壁的方向上，所述第二连接盘的侧壁至少一侧与所述第一连接盘的侧壁齐平，则加深后的所述第四开口暴露所述第二连接盘的与所述第一连接盘齐平的侧壁。
  19. 根据权利要求8-18任意一项所述的方法，其特征在于，所述在所述垂直通孔填充导电材料，以形成接触塞，包括：
    利用电镀或沉积工艺在所述垂直通孔内，以及所述第一晶圆的上表面形成导电材料；
    利用平坦化工艺去除所述第一晶圆的上表面的导电材料，以形成所述垂直通孔内的接触塞。
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