CN114981962A - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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CN114981962A
CN114981962A CN202080093552.5A CN202080093552A CN114981962A CN 114981962 A CN114981962 A CN 114981962A CN 202080093552 A CN202080093552 A CN 202080093552A CN 114981962 A CN114981962 A CN 114981962A
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land
wafer
connecting disc
opening
sidewall
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赫然
何志宏
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L27/144—Devices controlled by radiation
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Electromagnetism (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体器件及其制造方法，半导体器件可以包括第一晶圆(300)、第二晶圆(400)和接触塞(360)，第一晶圆(300)中可以包括第一介质层(320)，第一介质层(320)中具有第一连接盘(330)，第二晶圆(400)和第一晶圆(300)键合，第二晶圆(400)包括第二介质层(420)，第二介质层(420)中具有第二连接盘(430)，接触塞(360)为填充于垂直通孔中的导电材料，用于电连接第一连接盘(330)和第二连接盘(430)，其中垂直通孔为通过刻蚀形成的贯穿第一晶圆(300)且部分贯穿第二晶圆(400)至第二连接盘(430)的上表面和/或侧壁的通孔，第一连接盘(330)位于垂直通孔中且位于第一连接盘(330)之下的第一介质层(320)未被刻蚀，接触塞(360)可以从第一连接盘(330)的周围与第二连接盘(430)接触，从而利用简单的工艺实现接触塞(360)与第二连接盘(430)的可靠连接。

Description

PCT国内申请，说明书已公开。

Claims (19)

  1. PCT国内申请，权利要求书已公开。
CN202080093552.5A 2020-04-17 2020-04-17 一种半导体结构及其制造方法 Pending CN114981962A (zh)

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PCT/CN2020/085375 WO2021208078A1 (zh) 2020-04-17 2020-04-17 一种半导体结构及其制造方法

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CN114981962A true CN114981962A (zh) 2022-08-30

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US (1) US20230031151A1 (zh)
EP (1) EP4131374A4 (zh)
JP (1) JP2023521483A (zh)
KR (1) KR20230002752A (zh)
CN (1) CN114981962A (zh)
WO (1) WO2021208078A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5899738A (en) * 1997-05-23 1999-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the alignment marks without requiring extra masking steps
CN104051423A (zh) * 2013-03-13 2014-09-17 台湾积体电路制造股份有限公司 互连装置和方法
US20190035734A1 (en) * 2017-07-31 2019-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure and Method
CN109449091A (zh) * 2018-11-05 2019-03-08 武汉新芯集成电路制造有限公司 半导体器件的制作方法
CN110767605A (zh) * 2019-11-04 2020-02-07 武汉新芯集成电路制造有限公司 一种金属衬垫的形成方法

Family Cites Families (8)

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US20130264688A1 (en) * 2012-04-06 2013-10-10 Omnivision Technologies, Inc. Method and apparatus providing integrated circuit system with interconnected stacked device wafers
JP2015524172A (ja) * 2012-06-07 2015-08-20 レンセレイアー ポリテクニック インスティテュート 三次元集積におけるシリコン貫通電極（ｔｓｖ）応力を低減するためのコンフォーマルコーティング弾性クッションの使用
CN104377164A (zh) * 2014-09-28 2015-02-25 武汉新芯集成电路制造有限公司 一种晶圆跨硅穿孔互连工艺
EP3531445B1 (en) * 2016-09-07 2020-06-24 IMEC vzw A method for bonding and interconnecting integrated circuit devices
US9748175B1 (en) * 2016-11-18 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive structure in semiconductor structure and method for forming the same
KR102538174B1 (ko) * 2017-12-26 2023-05-31 삼성전자주식회사 비아 플러그를 갖는 반도체 소자
CN109148360B (zh) * 2018-08-28 2019-12-03 武汉新芯集成电路制造有限公司 半导体器件制作方法
CN109192747A (zh) * 2018-10-31 2019-01-11 德淮半导体有限公司 图像传感器的形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5899738A (en) * 1997-05-23 1999-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal plugs in stacked vias for multilevel interconnections and contact openings while retaining the alignment marks without requiring extra masking steps
CN104051423A (zh) * 2013-03-13 2014-09-17 台湾积体电路制造股份有限公司 互连装置和方法
US20190035734A1 (en) * 2017-07-31 2019-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure and Method
CN109449091A (zh) * 2018-11-05 2019-03-08 武汉新芯集成电路制造有限公司 半导体器件的制作方法
CN110767605A (zh) * 2019-11-04 2020-02-07 武汉新芯集成电路制造有限公司 一种金属衬垫的形成方法

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EP4131374A1 (en) 2023-02-08
EP4131374A4 (en) 2023-05-31
US20230031151A1 (en) 2023-02-02
WO2021208078A1 (zh) 2021-10-21
KR20230002752A (ko) 2023-01-05
JP2023521483A (ja) 2023-05-24

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